JP2680864B2 - Channel control system - Google Patents

Description

The present invention relates to a channel control method for controlling a data transfer request from a channel.

[Conventional technology]

Conventionally, this type of channel control system, when receiving a data transfer request from a channel, issues a read or write request to the memory, and when a response signal is returned, the next data transfer is accepted, but the response signal is returned. If not, the value of each register flip-flop is held until it is returned and the next data transfer is not accepted.

[Problems to be solved by the invention]

The above-described conventional channel control method accepts a data transfer request from the channel, issues a read or write request to the memory, returns a response signal from the memory, and receives at least 2 machine cycles until the next data transfer request is accepted. is necessary. For this reason, when data transfer requests are simultaneously issued from a plurality of channels, there is a drawback that it takes a long time to complete the processing of a channel having a low priority and an overrun easily occurs.

Further, since each register flip-flop is controlled by the response signal from the memory, the machine cycle time cannot be shortened due to the limitation of the propagation time of the response signal. Therefore, the processing time of data transfer cannot be shortened, so that there is a drawback that the performance is not improved.

[Means for solving the problem]

The channel control method of the present invention includes a priority determination circuit that selects one of data transfer requests from a plurality of channels according to priority, and whether or not there is a response from a memory to a memory request based on the selected data transfer request. A non-responsive flip-flop that is reset and set by a second channel number register that is set in response to a reset of the non-responsive flip-flop, in which a channel number related to the selected data transfer request is set; A selector for selecting the number of the channel relating to the selected data transfer request or the second channel number register in response to the reset / set state of the response flip-flop; and accepting the output of the selector for the channel number The memory request is made, There is provided a first channel number register whose updating is suppressed when there is no response from the memory to the memory request, and a decoder which decodes the channel number of the second channel number register. The feature is that the data transfer request is canceled.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram of one embodiment of the present invention.

The (n + 1) channels 101 have channel numbers # 0 to # 0.
It has #n and sends out data transfer request signals a0 to an in a timely manner.

The priority determination circuit 102 selects the one having the highest priority from the data transfer request signals a0 to an sent from the channel 101, and sends the selected data transfer request signal b together with the channel number c. To do.

The second data transfer request F / F 107 is sent to the priority determination circuit 10
The data transfer request signal b sent from 2 is set,
When the non-response F / F 106 is set, it retains the value at that time and does not change until the non-response F / F 106 is reset.

The second channel number register 108 is set with the channel number c which generated the data transfer request signal b selected by the priority determination circuit 102, and holds the channel number at that time when the no-response F / F 106 is set. Do not change.

The first selector 109 selects the value of the second data transfer request F / F 107 when the non-reaction F / F is set, and otherwise the data transfer request signal b sent from the priority determination circuit 102. Is selected as the input of the first data transfer request F / F 102.

The second selector 110 selects the second channel number register 108 when the non-responsive F / F 106 is set, and otherwise selects the channel number c selected by the priority determination circuit 102, and the first selector 110 selects the first channel number c. Channel number register 104
Input.

Memory request F / F105 is the first data transfer request
It is set by the F / F 103 and reset by the response signal d from the memory.

The no-response F / F 106 is set when the memory request F / F 105 is set and the response signal d is not returned from the memory. If the memory request F / F105 is set and the response signal d is not returned from the memory,
The values of the first data transfer request F / F 103 and the first channel number register 104 are held and not changed.

The decoder 111 decodes the value of the second channel number register 108 to generate decode signals e0 to en. These decode signals e0 to en reset the data transfer request signals a0 to an of the channels 101 of the channel numbers # 0 to #n.

FIG. 2 is a time chart of the channel control system of this embodiment.

All registers and F / Fs operate in synchronization with the basic clock A.

In the period T1 in the figure, the priority of the data transfer request signals a0 to a3 is a0>a1>a2> a3, assuming that the smaller the channel number is, the higher the priority is. Data transfer request signal a0 is selected.

The value of the channel number c becomes # 0, the first data transfer request F / F103 and the second data transfer request F / F107 are set, and the first channel number register 104 and the second channel number register 108 are set. # 0 is set.

In the T2 cycle in the figure, when # 0 is set in the second channel number register 108, the decode signal e0 is generated, and the data transfer request signal a0 is generated by the decode signal e0.
Is reset, and the priority determination circuit 102 invalidates the data transfer request signal a0, so that a1>a2> a3.
As a result, the channel number c changes to # 1, and the first and second
# 1 is set in the channel number registers 104 and 108 of.

In the T3 cycle, the memory request F / F 105 is set, and when the response signal d is returned from the memory, each register F / F is updated, and the next data transfer request is accepted.

In the T4 cycle, if the memory request F / F 105 is set and the response signal d is not returned from the memory, the updating of the first data transfer request F / F 103 and the first channel number register 104 is suppressed, and the non-response F / F106 is set.

In the T5 cycle, if the no-response F / F106 is set, the second
Data transfer request F / F107 and update of the second channel number register 108 are suppressed, and the first selector 109 is set to the second
The second selector 110 selects the value of the second data transfer request F / F 107 from the second channel number register 108.

In the T6 cycle, the response signal d is returned from the memory, but the non-response F / F 106 is still set,
The second data transfer request is sent to the first data transfer request F / F 103.
The value of F / F107 is the first channel number register 104
Is set to the value # 3 of the second channel number register 108.

The data transfer request signal a3 from the channel has already been reset, but since it is held in the second data transfer request F / F 107 and the second channel number register 108, the data transfer request can be accepted.

In each cycle of T7 to T9, the data transfer request from the channel # 3 is accepted, the read or write request is sent to the memory, the response signal d is returned from the memory, the memory request F / F105 is reset, and the data transfer processing is performed. Ends.

〔The invention's effect〕

As described above, according to the present invention, by controlling the newly added second data transfer request F / F and the second channel number register by the newly added non-response F / F,
By reducing the machine cycle time without being limited to the propagation time of the response signal from the memory, and by invalidating the data transfer request from the channel with the decode signal generated by the decoder for the value of the second channel number register. When a plurality of data transfer requests are generated, the data transfer requests can be accepted for each machine cycle, so that the performance of data transfer between the memory and the channel can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
It is a time chart of a figure. 101 ... Channel, 102 ... Priority determination circuit, 103 ...
First data transfer request F / F, 104 ... First channel number register, 105 ... Memory request F / F, 106 ...
… No response F / F, 107 …… Second data transfer request F / F, 108…
... second channel number register, 109 ... first selector, 110 ... second selector, 111 ... decoder.

Claims (1)

(57) [Claims] 1. A priority order determination circuit for selecting one of data transfer requests from a plurality of channels according to a priority, and resetting depending on the presence or absence of a response from a memory to a memory request based on the selected data transfer request. A non-responsive flip-flop to be set, a second channel number register to which a channel number related to the selected data transfer request is set and which is updated in response to a reset of the non-responsive flip-flop, and the non-responsive flip-flop A selector for selecting the channel number or the second channel number register relating to the selected data transfer request in response to the reset / set state of the memory request, and the memory request for the channel number by receiving the output of the selector. The memory request There is provided a first channel number register for which updating is suppressed when there is no response from the memory to the strike, and a decoder for decoding the channel number of the second channel number register, and the data transfer of the channel by the output of the decoder. A channel control method characterized in that the request is canceled.