JPH0139136B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an access control method for data arranged at regular intervals in a memory composed of a plurality of banks in an information processing device.

Prior Art Conventionally, as a method for controlling access to a memory composed of multiple banks, in order to determine whether or not the bank to be accessed is in use, at least a flip-flop is installed to indicate that the bank is in use. Set the number of banks,
Check that the bank you are trying to access is not in use depending on the state of the flip-flop,
An access request is being sent to memory. Another method is to register the address information of the bank used, hold the bank access cycle time, and compare the address information of the bank you are trying to access with the registered address information. It confirms that it is not in use and sends an access request to the memory.

However, these methods have the disadvantage that in a memory configured with a large number of banks, the amount of hardware required to indicate that a bank is in use increases. In particular, in order to perform high-speed continuous access to multiple pieces of data on a memory, it is common to configure a memory with a large number of banks to avoid as much as possible access requests to the same bank within the bank access cycle time. However, the above-mentioned drawbacks are becoming more apparent.

OBJECTS OF THE INVENTION An object of the present invention is to provide a memory access control method that eliminates the above-mentioned drawbacks and enables bank management with a small amount of hardware. A method for controlling access to a memory composed of a plurality of accessible banks and addressed in the order of the banks, in which a plurality of data are arranged at regular intervals on the memory, and a means for deciphering the data intervals. , means for informing the number of banks of the memory, means for informing the bank access cycle time of the memory, and interval information decoded by the decoding means;
Based on the number of banks of the memory and the bank access cycle time of the memory, the cycle for sending access requests to the memory is determined so that no access request is sent to the same bank of the memory within the bank access cycle time. and means for determining.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes an inter-element distance register 1, a decoder circuit 2, a period determining circuit 3, a count register 4, a subtraction circuit 5, a detection circuit 6, a register, and an OR circuit 8. has been done. The inter-element distance of the vector data is supplied to the register 1 that holds the inter-element distance of the vector data via the connection 101, and when the connection 110 is logic "1", the inter-element distance is strobed,
The output is led to decoding circuit 2 via connection 102. The decoding circuit 2 decodes the inter-element distance of the vector data given from the connection 102, and the decoded inter-element distance information is sent to the circuit 3 via the connection 103.
guided by.

Based on the inter-element distance information given through the connection 103, the memory bank number information given through the connection 104, and the bank access cycle time information given through the connection 105, the circuit 3 performs the following operations. This is a circuit that determines the cycle for sending an access request signal to the memory, and the determined cycle is led to the register 4 via a connection 106. The register 4 is a register that selectively stores the period of transmitting the access request signal supplied via the connection 106 and the output of the subtraction circuit 5 supplied via the connection 108 according to the logical value of the connection 112. , the stored value is supplied to the subtraction circuit 5 via connection 107. The subtraction circuit 5 is a circuit that subtracts 1 from the contents of the register 4 supplied via a connection 107, and the subtraction result is provided to the register 4 and the detection circuit 6 via a connection 108. The detection circuit 6 is a circuit that detects that all bits of the output of the subtraction circuit 5 supplied via a connection 108 are 0, and the detection result is supplied to the OR circuit 8 via a connection 109 and is also sent to the memory. The request signal for is valid.

Flip-flop 7 is a flip-flop that holds the strobe signal of register 1 supplied via connection 110 for one clock cycle;
The held contents are led to the OR circuit 8 via the connection 111. The OR circuit 8 receives the contents held in the flip-flop 7 supplied via the connection 111 and the connection 1
09, and the logical sum result is led to the register 4 via a connection 112.

Referring to FIG. 2, the period determining circuit 3:
It is composed of a selection circuit 21, a round-up circuit 22, and a shift circuit 23.

Lines 103-0 to 103-5 transmit inter-element distance information, which is the output of the decoding circuit 2 in FIG.
(2m-1), 8 x (2m-1), 4 x (2m-1), 2
×(2m−1) (where m is a positive integer). The selection circuit 21 is a circuit that switches the distance information between the elements according to the memory bank number information supplied via the connection 104, and outputs the information from the connection 2.
Shift circuit 23 by 01-0 to 201-4
guided by. In this embodiment, it is assumed that the number of memory banks is 16 and 32 banks, and when configuring 16 banks, the connection 2 is
01-0 to 201-4 correspond to the contents of connections 103-1 to 103-5, and when 32 banks are configured, the contents of connections 103-0 to 103-4 correspond to connections 201-0 to 201-4, respectively, and the selection is made. It is selected by the circuit 21 and output. The information provided via connection 105 represents the bank access cycle time. In this embodiment, it is assumed that the bank access cycle time is within 16 clock cycles.
The time value on connection 105 is supplied to circuit 22 .
The circuit 22 rounds up the bank access cycle time to a power of 2 and supplies it to the shift circuit 23 via the connection 202. Shift circuit 2
3, shift information is supplied via connection 202, the contents of connections 201-0 to 201-4 are shifted in the direction of lower digits, the remaining bit positions are filled with 0, and the result is transferred to connection 106- 0~106-4
1 to register 4 in FIG. The number of digit shifts is 0 bit when the value of connection 202 is 16, that is, the bank access cycle time is 9 clock cycles to 16 clock cycles, and 0 bit when the value of connection 202 is 8, that is, the bank access cycle time is 5 clock cycles to 16 clock cycles. One bit is given when there are eight clock cycles, and two bits are given when the value of connection 202 is 4, ie, the bank access cycle time is three clock cycles and four clock cycles.

Next, the operation of the present invention will be explained in detail with reference to the time charts of FIGS. 3A and 3B.

It is assumed that both the example shown in FIG. 3A and the example shown in FIG. 3B have a memory configuration of 16 banks, and the memory addressing is as shown in FIG. 4. It is also assumed that the bank access cycle time is 16 clock cycles in each case.

FIG. 3A shows an example of operation when the distance D between elements (hereinafter the distance between elements is simply referred to as distance D) is 1.

Strobe signal 110 of register 1 at time t _-1
When becomes logic "1", the distance D, that is, 1, is taken into the register 1 at time _t0 , and the operation is started. When distance D=1, decoding circuit 2
A signal indicating that the distance D=1 is output from , the line 103-5 becomes logic "1", and the lines 103-0 to 103-4 all become logic "0". Since the number of memory banks is 16, the outputs 201-0 to 201-4 of the selection circuit 21 are supplied to the shift circuit 23 as 00001 in binary representation. The bank access cycle time t _c (hereinafter referred to simply as time t _c ) given via the line 105 is "10000" in binary representation, and the output of the circuit 22 on the line 202 is also 2.
It is "10000" in decimal notation, that is, 16 in decimal notation, and the shift number of the shift circuit 23 is 0 bits, and the output of the shift circuit 23 is 106-0 to 1.
06-4 is "00001" in bit representation, that is, the period for sending out the access request signal to the memory which is the output of the circuit 3 is 1, and is supplied to the register 4 via the line 106. When distance D = 1, if an access request signal is sent to the memory at cycle 1, that is, every clock cycle, in a memory with a 16-bank configuration, the access request signal will be sent to the same bank every 16 clock cycles. If the time t _c is later and the time t c is 16 clock cycles, no access request signal for the same bank will be sent within the time t _c . Since the line 110 is at logic "1" at time t _{- 1} , the state of flip-flop 7 is at logic "1" at time t0, so the output of OR circuit 8 becomes logic "1", and the register 4 has the logic "1". The output “1” of 3 is taken in. At time _t1 , the subtraction circuit 5 converts the value 1 held in the register 4 to 1
The output for subtracting becomes 0. Since "0" is supplied to the detection circuit 6, the output of the circuit 6 becomes logic "1", and the access request signal to the memory becomes valid. Also, since the line 110 is a signal that becomes logic "1" for one clock cycle, the time
At time t ₀ , the line 110 becomes a logic "0" and the register 1 continues to hold the distance D, i.e. "1". At time t ₁ , the line 107 becomes a logic "1", so the OR The output of the circuit 8 becomes logic "1", and the line 106 is taken into the register 4. At time _t1 , the value of the register 1 changes to the value at time t0 _.
Since the value is the same as that at time t ₁ , the line 106 at time t 1 is “1” as at time t ₀ . Therefore, from time t ₂ onwards, the same operation as at time t ₁ is performed and continues until a different distance D is stropped in the register 1.

FIG. 3B shows an example of operation when the distance D is 2.

When the register 1 strobe signal becomes logic "1" at time t _-1 , the distance D, ie, 2, is taken into the register 1 at time t ₀ and the operation is started.

When the distance D=2, the signal indicating that the distance D=2 from the decoding circuit 2, that is, the line 103-4 becomes logic "1", and the lines 103-0 to 103-3 and 103-5 become logic "0". ”Selection circuit 2
1. Since the number of memory banks is 16, the outputs 201-0 to 201-4 of the selection circuit 21 are "00010" in binary representation.
The signal is then supplied to the shift circuit 23. line 105
The time t _c given through is “10000” in binary representation
Since the output 202 of the circuit 22 is also "10000" in binary representation, that is, 16 in decimal representation, the shift number of the shift circuit 23 is 0 bits, and the outputs 106-0 to 106- of the shift circuit 23 are 4 is "00010" in bit representation, that is, the period 106 for sending out the access request signal to the memory which is the output of the circuit 3 is 2 and is supplied to the register 4.
When distance D = 2, if an access request signal is sent to the memory once every 2 cycles, that is, every 2 clock cycles, in a memory with a 16-bank configuration, the access request signal will be sent to the same bank. This is the element after 8 elements. Therefore, 16 clock cycles, which is the value obtained by multiplying 8 by 2, have passed, and if time t _c is 16 clock cycles, no access request signal for the same bank will be sent within time t _c . Since the line 110 is logic "1" at time t _-1 , the state of flip-flop 7 is logic "1" at time _t0 , and the output of OR circuit 8 is logic "1".
Then, the output of the circuit 3, which is "2", is taken into the register 4.

At time _t1 , the subtraction circuit 5 subtracts 1 from the value D held in the register 4, so the output becomes 1. Since the detection circuit 6 is supplied with 1 and not 0, the output of the circuit 6 becomes logic "0", and the access request signal to the memory is not valid. Also, since the line 110 becomes a logic "1" for one clock cycle, the line 110 becomes a logic "0" at time _t0 , and the distance D,
That is, "2" is continuously held. Since the state of the flip-flop 7 is logic "0" and the output of the detection circuit 6 is also logic "0",
The output of the OR circuit 8 is logic "0" and the register 4 receives the output "1" of the subtraction circuit 5.

At time _t2 , the value held in the register 4 is "1", and the subtraction circuit 5 subtracts "1" from "1", outputs "0", and outputs "0" to the detection circuit 6.
supplied to The output of the circuit 6 becomes logic "1", which makes the access request signal for the memory valid through the connection 109, and also makes the output of the OR circuit 8 logic "1", so that the output of the circuit 3 is sent to the register 4. Select and import. The register 1 continues to hold "2", and the output of the circuit 3 becomes "2" and is supplied to the register 4.

Since the state at time t ₃ is the same as the state at time t ₁ , the same operation as at time t ₁ is performed at time t ₃ . Therefore, the state at time _t4 is the same as the state at time _t2 , so the operation at time _t4 is the same as the operation at time _t2 . Therefore, after time _t3 , the operations at times _{t1 and t2} are repeated until the register 1 is strobed with a different distance D.

Effects of the Invention The present invention provides means for decoding the intervals between a plurality of pieces of data and determining the cycle for sending access requests so that access requests are not sent to the same bank within the bank access cycle time. This has the advantage that memory bank management in memory access of vector data can be performed using only a small amount of hardware.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing details of the circuit 3 shown in FIG. 1, and FIGS. 3A and 3B are time charts and diagrams for explaining the operation. FIG. 4 is a diagram showing the bank structure and addressing of the memory. 1 to 4, 1...inter-element distance register, 2...decoding circuit, 3...cycle determining circuit,
4... Count register, 5... Subtraction circuit, 6... Detection circuit, 7... Flip-flop, 8... OR circuit,
101... Inter-element distance, 110... Inter-element distance register strobe signal, 104... Memory bank number information, 105... Bank access cycle time information,
109...Memory access request valid signal, 102,
103, 106 to 108, 111, 112... Connection, 21... Selection circuit, 22... Rounding up circuit, 23...
Shift circuit, 201, 202... connection.

Claims (1)

[Scope of Claims] 1. A plurality of data is arranged at regular intervals on the memory, or access to the data is controlled, to a memory that is composed of a plurality of banks that can be accessed independently and is addressed in the order of the banks. A method for decoding data intervals, means for informing the number of banks of the memory, means for informing the bank access cycle time of the memory, and interval information decoded by the decoding means, Based on the number of banks of the memory and the bank access cycle time of the memory, determine a cycle for sending access requests to the memory so that no access request is sent to the same bank of the memory within the bank access cycle time. A memory access control method comprising means for controlling.