JPH0743690B2 - Access priority control system - Google Patents

Description

The present invention relates to a priority control system having a priority determination circuit for a plurality of access requests cascade-connected in multiple stages, wherein each of the priority determination circuits effectively and effectively busyes the access processing device. Is checked to determine the selection of the access request, it is possible to prevent the access request from the access requesting device at each stage from waiting in the access processing device.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a priority control system having an access request priority order determination circuit of access request devices connected in cascade in multiple stages in an information processing system or the like.

[Conventional technology]

In the information processing system, there is a memory access processing unit (hereinafter referred to as MCU) as an example of the access processing unit, and a central processing unit (hereinafter referred to as CPU) as the access requesting unit.
There is a) and channel processing device (hereinafter referred to as CHP). Since the processing time of the CPU is more important than that of the CHP, the applicant of the present application has previously proposed a priority determination circuit for access requests which is cascaded and connected in multiple stages, as disclosed in Japanese Patent Laid-Open No. 57-164338.

The above invention relates to a circuit for selecting and deciding only one access request from access requests issued by a large number of access requesting devices, and the selected access request is in a waiting state due to busy (access processing) by a preceding access request. It did not take into consideration the processing for becoming.

The reason is that in the MCU, if the memory device speeds up and the pipeline control is performed in the access process to improve the processing efficiency, the busy check may occur or the busy release may already occur during the access request selection decision depending on the type of access process. However, it was rather a waste of free time.

[Problems to be solved by the invention]

However, if the busy check is not taken into consideration as in the above-described conventional case, an access request selected with care in another type of access processing may be prohibited in the access processing device in a busy state due to the preceding access request. However, there is a problem in that the access requesting device that issued the access request has an idle time, and the throughput is reduced.

Further, since the access requests selected and decided by the subsequent priority order determination circuit are a large number of access requests narrowed down, the selection decision is made so that the priority order is higher in the preceding priority order determination circuit. In addition, since the access requesting device whose processing time becomes more important toward the front is connected, waiting for the access request of the latter part also means waiting for the access request of the access requesting device of the front part. There is a problem that the processing capacity is lowered.

The present invention has been made to solve the above problems, and in a priority determination circuit for access requests cascade-connected in multiple stages, an access request from a subsequent priority determination circuit is busy in an access processing device. It is an object of the present invention to provide an access priority control system for reducing the probability of being hit by a state, improving the throughput of each access requesting device, and improving its processing capability.

[Means for solving problems]

According to the present invention, a plurality of priority order determining circuits are connected in cascade, and one priority order determining circuit has access requests from a plurality of access requesting devices belonging to the circuit and a subsequent priority order determining circuit. And an access request, which is the output of the priority request, is output, the output from the highest priority determination circuit is input as an access request signal to the busy control unit of the access processing device, and The access processing device and each of the subordinate-connected priority order determination circuits are controlled by different clock cycles corresponding to different arrival times of busy signals from the access processing device, and the busy control unit Then, when inputting any of multiple types of access requests with different processing times, set the processing time corresponding to the access request. A busy signal indicating the type of access request that can be output to each priority determination circuit under pipeline processing for each clock cycle between the access processing device and each priority determination circuit. And the priority determination circuit determines the type of access request that can be output based on the busy signal.

[Action]

FIG. 1 shows the principle of the present invention. Here, the preceding priority determination circuit 4 is closest to the access processing device 3 and the determined access request arrives immediately, so a busy check can be performed in machine cycle units. However, if the latter priority determination circuit 4 is used, the printed circuit board mounting is also different, and the selection determination is made for these physical conditions by adding the difference in the clock cycle from the access processing device 3 and the selection determination processing time. It takes time for the access request thus made to reach the access processing device 3.

Therefore, the access processing apparatus adjusts the information of the type of access request that can be sent by the priority determination circuit at each clock cycle in the processing of the type corresponding to the access request to the clock cycle of each priority determination circuit. Send in the form of a busy signal.

As a result, even when the access request from the subsequent priority determination circuit is sent to the access processing device via the previous priority determination circuit, the corresponding access processing can be performed immediately. This significantly reduces the probability that an access request from the subsequent priority determination circuit will be kept waiting due to busy.

〔Example〕

 The present invention will be described in detail below with reference to the drawings and examples.

FIG. 2 is a block diagram for explaining one embodiment of the present invention, and FIG.
The figure is a block diagram of the busy controller.

First, the configurations of an information processing system and a priority order determination circuit to which the present invention is applied will be described.

In FIG. 2, the information processing system is configured such that a plurality of CPUs 1 which are access requesting devices and a plurality of CHP2 which are also access requesting devices issue access requests (hereinafter REQ) to an access processing device 3 which performs a memory access process. It is to access. Since these REQs compete with each other, priority determination circuits 4 and 4'are connected in two stages in a cascade connection. The CPU 1 whose access time is important is connected to the priority determination circuit 4'of the front, and the priority determination circuit 4'of the rear is connected.
Is connected to CHP2, whose access time is relatively unimportant.
Here, the REQ of CHP2 is narrowed down to one and input to the preceding priority determination circuit 4 '.

Since the input REQs are the REQs of a large number of CHP2s, the priority decision circuit 4'makes a selection decision at a high priority level.

The access processing device 3 decomposes the access processing into partial operations, and simultaneously executes a plurality of access processing at time intervals of the partial operations, a bank memory 6 having a bank structure, and access data from the access address to the buffer memory 6. A busy control for issuing a busy signal for determining whether or not a valid access request can be sent to the access processing device in each of the priority determining circuits 4 and 4'of the tag 7 for checking whether there exists It is composed of the unit 8 and the like.
The priority determining circuits 4 and 4'belong to the priority processing port units 9 and 9 ', respectively. In addition to this, the priority processing port units 9 and 9'correspond to the access requesting devices 1 and 2, a register 10 for latching REQ and an access address, and a busy signal issued from the address processing device 3 to a bank. It is composed of a flip-flop 11 (hereinafter referred to as FF11) that latches the data.

The priority determining circuits 4 and 4'see the above FF11 from the access address sent together with REQ, and if the relevant bank is busy so as to indicate that all access is prohibited, it does not make a REQ selection determination, and if it is busy or no busy otherwise. Only if the corresponding REQ selection decision is made.

Next, the configuration of the busy controller 8 will be described.

The busy control unit 8 for one bank shown in FIG. 3 first receives the REQ selected from the priority processing port 9 '(hereinafter, P port unit 9') and the write command from the pipeline 5, respectively. During 1τ ₁ of ₁ ), the first P-bus busy sending logic circuit 12 for issuing a busy signal of the corresponding bank to the P port section 9'and the control section set logic circuit cooperating with it, as well as 1τ ₁ after receiving REQ Via the second P-bank busy sending logic circuit 15 for issuing a busy signal of the corresponding bank to the P port section 9'after 1τ ₁ in response to a write command from the controller and the control section setting logic circuit 13. A control unit 14 that issues a control signal of the busy signal transmission time,
Bank busy sending logic circuit for CP that issues a busy signal for the corresponding bank to the subsequent priority processing port (CP port section) 9
It is composed of 16 etc.

The bank busy signal issued from the first P bank busy sending logic circuit 12 and the second P bank busy sending logic circuit 15 is sent to the P port unit 9 ′ via the ao gate 17. The control unit 14 is a PST flip-flop (PST-FF) set when the access is the partial store described later.
14a, an FST flip-flop (FST-FF) 14b that is set at the time of full store, and an initial value of the count are set in the same manner, and then a clock for access processing of one cycle period τ ₁ is set to the count value "3". It consists of a control count 14c that counts cyclically for as long as necessary. Note that in pipeline control, two or more access processes may simultaneously proceed at time intervals of partial operations. Therefore, when a plurality of control units are provided, such as control units 14 and 14 ', corresponding to each access process. There is also. The control unit 1 in this case
The control signal from 4, 14 'is ORed and sent to each bank busy sending logic circuit 15, 16.

The operation of this embodiment configured as described above will be described with reference to FIGS.
This will be described with reference to the drawings and based on FIGS. 4 to 6.

4 to 6 are time charts showing the logic of sending a busy signal for each access process.

The clock cycle τ ₂ of the CP port unit in FIG. ₂ is twice the clock cycle τ ₁ for access processing (τ ₂ = 2τ ₁ ), and they are assumed to be in synchronization with each other. Further, the P port unit 9'determines the state of FF11 and sends a valid REQ, and a busy signal for each cycle of processing in the access processing unit is sent from the busy control unit, which is FF11 of the P port unit 9 '. It is assumed that the time until it is latched in is within τ ₁ and the time corresponding to the above in the CP port unit 9 is within 2τ ₁ (τ ₂ ).

The access processing of the access processing device 3 includes fetch, full store, and partial store. Fetch is a read (read) from the buffer memory, full store is a write (write) to the buffer memory,
In the virtual store, for example, 8-byte data is read, and a part of the byte data is rewritten and written. In this embodiment, read and write are 3τ ₁
Finish within. From busy control unit 8 to each port unit 9,9 '
The busy signals issued to each of the above-mentioned arrival times are taken into consideration, and the busy signals necessary to enable the transmission of a valid REQ in the P port unit 9'and CP port unit 9 are coded as shown in the following busy value table. Created.

Here, the control counter 14C of the control unit is 0,1,2,3,0, ...
As described above, when the count value is 0, the busy signal is not transmitted in principle. Therefore, "00", which indicates the no-busy state in which all access can be processed, is output only when the count value is 0.

A busy value “11” signal indicating that all access is prohibited blocks any access request, but a busy value 01 is a full store even if partial store and fetch are prohibited, and a busy value 10 is full. Although the store request is prohibited, it indicates that partial store and fetch are possible, and 01 or 10 is sent when the count value is acceptable.

Further, the bank busy sending logic circuit 12 for P has a P port section 9 '.
When the REQ is received from the controller, the contents of the REQ at that time are judged together with the control unit setting logic circuit 13 and the busy signal for the first 1τ ₁ is sent out, and the busy signal sending function is started from the next cycle.
However, when the P bank busy sending logic circuit 12 receives a write command from the pipeline, the busy signal is sent to the OR gate 17 for 1τ ₁ .

The operation of the busy control unit will be described with reference to FIGS.

In the present embodiment, in the case of the fetch (read) shown in FIG. 4, the reading is started 1τ ₁ after receiving the REQ of the fetch, and the reading ends at 3τ ₁ , so 4τ until the reading is completed after receiving the REQ. Suppose it costs ₁ .

The full store (light) shown in Fig. 5 is
1τ ₁ after receiving REQ, a write command is sent from the pipeline 5 after a time of 2τ ₁ for referencing the tag 7, etc., and after 1τ ₁ time, the write ends in a machine cycle of 3τ ₁ , It takes 7τ ₁ from receiving REQ to completion of writing.

Also, the partial store shown in FIG.
Since some data is rewritten and written, the control is such that fetch and full store continue. Thus addition of 7τ ₁ required to 4τ ₁ and full stores needed to fetch, 1τ ₁ necessary to control between the fetch and full store
12 τ ₁ is required from the receipt of the partial store REQ to the end.

The time charts of FIGS. 4 (a) and 4 (b) show the busy signal transmission logic in the case of fetch. In FIG. 4 (b), the REQ from the P port 9'is synchronized with the clock of CHP2, that is, the clock of the CP port. Is accepted by the busy control unit 8 (hereinafter referred to as the case of EVEN), (b) is a case delayed by τ ₁ after that (hereinafter referred to as the case of ODD). In the case of fetch, PST-FF14a and FST-FF14b remain clear and are not set.

In the case of FIG. 4, since it is a fetch and a read (read) from the buffer memory, the read RE is performed as described above.
4 from receipt of Q by busy control unit 8 to completion of read
It becomes τ ₁ .

Therefore, in FIG. 3, the P port unit 9'determines from the state of FF11 that fetch (read) REQ can be sent, sends the fetch PEQ to the busy controller 8, and the P bank busy sending logic circuit 12 receives it. , A busy signal indicating that the fetch process requires 4τ ₁ together with the control unit set logic circuit 13 and the P port unit 9'can send out a full store REQ in each cycle of the first 2τ _1. It is determined that "01" should be sent, and in the third cycle, a busy signal "00" indicating that it is possible to send either REQ of all access processing, and as a result, it is determined in FIG. In the case of (a) EVEN, the clock
At time t _1, the bank busy transmission logic circuit 12 for P outputs “01”.
Then, from the P bank busy transmission logic circuit 15 at the time point t ₂ , “01” is similarly given, and at the time point t ₃ , “00” is sent via the OR gate 17 and the busy signal is given at the P port section 9 ′. Send to FF11 to latch.

Such "01", "00" state of 'being latched in FF11, and therefore P port 9' P port portion 9 at each cycle of the t _1, t ₂ point in the processing of full store access processor 3 Know that it is possible to send a REQ for. Also, it is known that REQ can be sent for all access processes in the cycle at time t ₃ .

Therefore, the fetch REQ is sent to the P bank busy sending logic circuit 1
When 2 is received, this circuit makes the above determination together with the control unit setting logic circuit 13, whereby the control counter 14C is controlled by the control unit setting logic circuit 13 and is set to 2.
When the count value is 2, the P bank busy sending logic circuit 12 sends "01" and the count value 3 sends "01" from the P bank busy sending logic circuit 15.

Next, as shown in the figure, 00 is sent out, which indicates no-busy status in which all access is possible when the count value is 0.

On the other hand, the CP bank busy signal is determined every 2τ ₁ in synchronization with the clock of CHP2, that is, the clock of the CP port unit 9, and the next R
The control by the EQ is started after t ₅ , and the access processing is already performed when the REQ arrives. Therefore, in the case of EVEN of (a), at the time of t ₂ , “ If "00" is sent to the CP port unit 9, t ₂
At that point, it is known that the REQ can be sent for any access. On the other hand, in the case of (b) ODD, t ₄
Will send "00" to the CP port.

That is, the busy value of the bank busy signal for the P port unit 9'is determined for each machine cycle τ ₁ , and the first busy value after receiving REQ is the set state of the control unit is not fixed. The bank busy sending logic circuit 12 of 1 determines the contents of REQ together with the control section setting logic circuit 13 and sends the first busy signal. However, in the case of the fetch of FIG. As described above, "01" and "00" are transmitted from the second bank busy transmission logic circuit 15 as the busy value of.

As described above, the busy controller 8 can send a timely effective busy signal to each port 9, 9 '.

The time charts of FIGS. 5A and 5B show the busy signal transmission logic in the case of full store. FF at P port 9 '
After checking the status of 11, it is judged that the full store REQ can be sent. When the full store REQ is sent, the full store REQ is sent, and then the write is completed after the full store REQ is received. Since 7τ ₁ is required up to this time, when the P bank busy sending logic circuit 12 of the busy control unit 8 receives this full store REQ, this 12 determines the contents of this REQ together with the control unit set logic circuit 13, and t ₇ At this time point, the control counter 14C is set to 2 so that the count value becomes 0, and control is performed so as to count in the order of 2,3,0,2,3,0. The control from the control unit sets a logic circuit 13, from t ₁
FST-FF is set up to the point of t _3. At time t ₁ when the count value of the control counter is 2, the P bank busy sending logic circuit 12 sends "11" indicating that all access is prohibited.

When the count value is 3, the bank busy sending logic circuit for P 15 continues to send "11" at time t ₂ .

Next, in the cycle from time t ₃ when the count value becomes 0, FS
The T-FF is reset, and the P bank busy signal indicating that it is possible to send another full store REQ is set to "01".

Next, when the write command receives the P bank busy sending logic circuit 12 as shown in the figure, "01" is sent from the P bank busy sending logic circuit 12 at the count value 2 as shown by the arrow from the write command in FIG. , "01" is sent again from the P bank busy sending logic circuit 15 at the count value 3, and "00" is sent at the next count value 0.

The bank busy signal for the CP port unit 9 is synchronized with the clock of the CP port unit 9 as in the case of fetch, and REQ
The control signal from the busy controller 8 is
In the case of EVEN, the count value is 3 and the next 0, and the busy value is "01".
Then, 2 and 3 become "00". In the case of ODD, as shown in the figure, the count value 0 and 2 are "01", and the next 3 and 0 are "00".
Becomes

The time charts of FIGS. 6A and 6B show the busy signal transmission logic in the case of partial store. As mentioned above, the partial store is 1 from receiving the REQ to the end of writing.
Requires 2τ ₁ . Therefore, when the P bank busy sending logic circuit 12 of the busy control unit 8 receives the partial store REQ, it determines the contents of REQ together with the control unit setting logic circuit 13, and at the time of t ₁ , the P bank busy sending logic circuit 12 determines ,
A busy signal "01" indicating that full store REQ transmission is possible is transmitted from the P port unit 9 ', and subsequently, the bank busy transmission logic circuit 15 for P similarly outputs "01" at the time t ₂ . After that, at times t ₃ , t ₄ , and t ₅ , fetch or REQ of another partial store can be sent. "Ten"
, And subsequently prohibit all access. At t ₈ after sending “11” for 2τ ₁ , a busy signal “01” indicating that a full store REQ can be sent is sent. At time t ₉ , a write command is issued from the pipeline, so P
The bank busy sending logic circuit 12 sends "01", and then the P bank busy sending logic circuit 15 gives "01" at the time t ₁₀ and all access signals at the time t _11. Send "00" indicating that the REQ can be sent.

For such control, PST-FF to the point of t ₈ from time point t ₁ the control than the control unit sets the logic circuit 13, also is set FST-FF to the point of t ₈ from the time point t _5, and the control counter 14C is set to 1 and counts as 1,2,3,0,1,2,3,0,2,3,0.

Therefore, the bank busy signal for P as described above is set in FF11 of the P port section 9 ', so that t ₁ ,
In each cycle of t ₂ , the full store REQ
In each cycle of t ₃ , t ₄ , and t ₅ , the partial store
REQ delivery is determined to be possible, it is impossible even delivery of what Naru REQ at each time point of a cycle of _{t 6, t 7, t 8} ~t
In cycle of each point in the ₁₀ knows that REQ full store, the cycle time of t ₁₂ fetches a full store, it is possible to delivery of one of the REQ Izure of partial store.

Also, as the bank busy signal for CP, in the case of (A) EVEN t ₂
“10” from time t to time t ₄ , “11” from time t ₄ to t ₆ , and “01” from time t ₆ to t ₈ and time t ₈ to t ₁₀ , respectively. , RE of “00” from t ₁₀ to t ₁₂
When a CP bank busy signal indicating that Q can be sent out is sent to the CP port unit 9, the CP port unit determines that the corresponding REQ can be sent out at each of the above cycles.

The CP bank busy signal in the case of ODD in FIG. 6B is also transmitted as shown. Therefore, for example, in (a) of FIG. 6, the busy signal "01" sent at the time of t ₁ is latched in the FF11 of the P port section 9 ', and accordingly, the full store is performed from the P port section 9'. Is sent to the busy control unit 8, the access process is started at time t ₂ , and after 4τ ₁ t
_The writing will be performed from the time point _{6 to} the time point t ₉ .

Further, in response to “01” at the time point t _2, when the full store REQ is sent to the busy control unit 8, t _{7 4} t ₁ after t ₃
The writing will be performed from time t to time t ₁₀ .

The Te also preparative cerebrospinal to P bank busy signal for "10" at the time of t _3, if sending the P port portion 9 'of the fetch REQ cycle time of t _3, the access processing from t ₄ time Is started, reading is performed from t ₅ to t ₈ after 1τ ₁ , and if a partial store REQ is sent, t
_The process is started from the time point of ₄ , and the reading is performed from the time point of t _{5 to} the time point of t ₈ after 1τ ₁ and the writing is further performed from the time point of t _{13 to} the time point of t ₁₆ .

That is, in the idle time other than the read and write processing time shown in FIG. 6 (a), "01", "10", "01" in the P bank busy signal transmitted every ₁ τ ₁ after time t _2. "Based on REQ from P port 9 ', full store, fetch,
Each processing of the partial store can be performed without overlapping.

The present invention is not limited to the above embodiments, and various modifications and applications are possible according to the gist of the present invention. For example, the values of the flip-flops and counters of the control unit 14 shown in FIG. 3 are supplied as they are to the priority determination circuits 4 and 4 ', and the circuits corresponding to the bank busy transmission logic circuits 15 and 16 are provided to the priority determination circuits. It may be provided on the side of 4, 4 '.

〔The invention's effect〕

As described above, according to the present invention, in the priority control system having the priority determination circuits for access requests cascade-connected in multiple stages, the access processing device has a timely effective busy state for the priority determination circuits of each stage. Since the signal is sent and checked at each stage to process the access request, the probability that the access request from the access requesting device will be busy waiting in the access processing device is reduced, and as a result, waiting for another access request It is also possible to improve the throughput of each access requesting device and improve the processing capacity.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining the principle of the present invention, FIG. 2 is a block diagram for explaining one embodiment of the present invention, FIG. 3 is a block diagram of a busy control unit, and FIGS. ) Is a time chart showing the busy signal transmission logic in the case of fetch,
FIGS. 6A and 6B are time charts showing the busy signal sending logic in the case of full store, and FIGS. 6A and 6B are time charts showing the busy signal sending logic in the case of partial store. . 1 ... Access request device (CPU) 2 ... Access request device (CHP) 3 ... Access processing device (memory access processing device) 4,4 '... Priority determination circuit 8 ... Busy control unit

Claims (1)

[Claims] 1. A plurality of priority determining circuits are cascade-connected in multiple stages, and one priority determining circuit has access requests from a plurality of access requesting devices belonging to the circuit and outputs of the subsequent priority determining circuits. The access request of which priority is determined is output, the output from the priority determination circuit of the highest priority is input as an access request signal to the busy control unit of the access processing device, and the access processing The device and each of the subordinately connected priority determination circuits are controlled by different clock cycles corresponding to different arrival times of busy signals from the access processing device, and in the busy control unit,
When inputting any of a plurality of types of access requests having different processing times, the processing time corresponding to the access request is determined, and each priority is given for each clock cycle between the access processing device and each priority determining circuit. Under the pipeline processing, the priority determination circuit sends a busy signal indicating the type of access request that can be output, and based on the busy signal, the priority determination circuit determines the type of access request that can be output. Access priority control system characterized by