JP2679343B2 - Loop processing method - Google Patents

Description

The present invention relates to a loop processing method, and more particularly to a hierarchical loop processing method.

[Conventional technology]

The loop handled in the present invention is a path that returns from a certain contact point to the original node via one or more branches. FIG. 7 shows an example of a loop, which starts from the node 701 and branches 705, 708, 706.
It shows a loop back to 701 via. Further, the processing related to the loop is called loop processing.

Macros are used as a method of expressing a hierarchical structure. FIG. 8 (a) shows a hierarchical structure of macros, and the hierarchy 801 is composed of contacts 802, 803, 804, 805 and macros 06, 807. FIG. 8 (b) shows the main body of the macro 807 of FIG. 8 (a), and 807 further has a macro 80 inside.
Contains eight.

Conventionally, when performing loop processing on a hierarchical structure, the following method has been used.

The first method is a method of expanding the entire hierarchical structure, converting it into a structure without a hierarchy, and performing a loop process on the structure without a hierarchy.

The second method is a method of performing a loop process across layers.

[Problems to be solved by the invention]

The above-mentioned first method has a drawback that hierarchical information is lost by expanding the hierarchical structure.

The above-mentioned second method has a drawback in that, when processing is performed across layers, the processing becomes more complicated than the processing for a circuit having no layers.

In addition, any of the methods has a drawback in that the load of the loop processing becomes large because one loop processing targets the data of all layers.

[Means for solving the problem]

A loop processing method according to the present invention includes at least a processing for searching a path starting from an arbitrary contact and returning to the original contact via one or more branches from circuit connection information described in a hierarchical structure. In, in the lowest layer, a closed loop is searched for in each layer, if a loop is found, a critical pulse in that layer is found, and a logic gate that cuts the loop while avoiding the critical path is inserted and Performs an intra-layer loop process that records the dependency of the I / O terminals of the layer and the delay time between the I / O terminals as attribute information, and uses the attribute information of the lower layer in the loop process of the upper layer to perform the intra-layer loop process. It is characterized by performing.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

In this example, it is assumed that a logical circuit having a hierarchy as a hierarchical structure is handled, and the numerical value indicating the hierarchy level increases as the highest hierarchy of the circuit becomes the first hierarchy level and becomes the lower hierarchy. The entire circuit is regarded as one macro and this macro is located at the 0th hierarchical level.

1 and 2 are flowcharts showing an embodiment of the present invention. In this embodiment, the processing for searching all the loops in the circuit is realized.

FIG. 1 shows the main routine. First, in step A1, the number of circuit layers is set in the variable n. Next, the nth
While there are unprocessed macros in the hierarchy level, loop processing of unprocessed macros is performed in step A3. If there are no unprocessed macros in the nth hierarchical level, the hierarchical level is raised by one step in step A4 and the processes of steps A2 and A3 are repeated.
At step A5, it is determined whether all the processing is completed.

FIG. 2 shows the loop processing for the unprocessed macro in step A3 in detail. In step B1, the closed loop is searched in the macro by using the attribute information of the lower hierarchy. In step B2, the dependency relationship of the input / output terminals, that is, the change in the input value of a certain input terminal affects the output value of which output terminal, is recorded as attribute information of the macro.

FIG. 3 is an example showing the internal structure of the macro. macro
101 is logic gate 102, 103, 104, macro 105, 106, 107, input terminal 108, 109, 110, 111, 112, 113, output terminal 114, 115, 11
It is composed of 6,117.

When the loop processing for the unprocessed macro of FIG. 2 is applied to the macro 101, the loop circuit processing of all the macros 105, 106, 107 already included in this macro is completed, and the dependency relationships 118, 119, 120 of the input / output terminals of each macro are respectively generated. Since it is recorded, macros and logic gates can be treated in the same way. Therefore, in the loop search process of step B1, the process for a circuit having no hierarchy can be applied as it is.

FIG. 4 shows the dependency of input / output terminals as a result of applying step B2 to the macro 101 of FIG.

FIG. 5 is a flow chart showing another embodiment of the present invention. Also in this embodiment, the loop cutting process is tested by using the main routine of FIG.

FIG. 5 shows the loop processing for the unprocessed macro in step A3 of FIG. In step C1, search for a loop in the macro, and if a loop exists, first find the critical path in the macro using the delay time between the input and output terminals of the lower macro in step C3, and then in step C4 select the critical pulse The loop disconnection process is performed in consideration of not increasing the delay value. When all the loops are disconnected, the dependency relationship between the input / output terminals is obtained in step C5, and the delay time between the input / output terminals is obtained in step C6 and recorded as macro attribute information.

FIG. 6 shows the result of applying steps C3 and C4 to the macro 101 of FIG. For the loop composed of the signal lines 121, 122, 123, 124 of FIG. 3, the signal lines 125, 121, 122, 123, 126
Considering not to increase the delay time of the critical path in the macro composed of, the loop is logically cut by inserting the logic gate 127 whose output value becomes a fixed value by the control signal 128. .

〔The invention's effect〕

As described above, according to the present invention, the loop processing method for a structure having no hierarchy can be applied in the loop processing for a hierarchical structure without expanding the hierarchical structure, thereby facilitating the processing. Further, by performing the loop processing on the macro, the circuit scale targeted for one loop processing is reduced, so that the load of the loop processing is reduced.

[Brief description of the drawings]

FIGS. 1 and 2 are flow charts showing an embodiment of the present invention, FIG. 3 is a macro diagram for explaining the operation shown in FIG. 2, and FIG. 4 is a diagram showing input / output terminals of the macro shown in FIG. It is a figure which shows a dependency relationship. FIG. 5 is a flow chart showing another embodiment of the present invention,
FIG. 6 is a macro diagram for explaining the operation shown in FIG. FIG. 7 is a diagram showing an example of a loop. 8 (a) and 8 (b) are diagrams showing an example of a hierarchy realized by a macro.

Claims (1)

(57) [Claims] 1. A loop processing method comprising at least a process of searching a circuit connection information described in a hierarchical structure for a route starting from an arbitrary contact and returning to the original contact via one or more branches. It searches for closed loops in each layer from the lower layers, finds a critical pulse in the layer when a loop is found, inserts a logic gate that cuts the loop avoiding a critical path, and has that layer. Performing an intra-layer loop process that records the dependency relationship between input / output terminals and delay time between input / output terminals as attribute information, and performing the intra-layer loop process by using the attribute information of the lower layer in the loop process of the upper layer A loop processing method characterized by.