JP2677248B2 - Active matrix liquid crystal display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal display panel, and more particularly to an active matrix liquid crystal display panel of a type having a light shielding layer which shields a channel portion of a thin film field effect transistor.

[0002]

2. Description of the Related Art An active matrix liquid crystal display panel (AMLCD) is a thin film field effect transistor (TF).
T) is a display device of a type that uses it as a switching element for a pixel electrode, and has a high quality image, and therefore is widely applied to a display unit of a portable computer, a light valve of a projection display device, and the like.

The AMLCD generally has two substrates called a TFT substrate and a counter substrate. In the TFT substrate, scanning lines and signal lines are arranged in a grid pattern on a transparent insulating substrate, thin film transistors (TFTs) and pixel electrodes driven by the TFTs are provided in each grid section, and these are arranged in a matrix pattern on the substrate. And an alignment film 15 is formed on the surface. Further, the counter substrate is a transparent insulating substrate having a transparent electrode formed on the entire surface and further having an alignment film 15 on the surface. A liquid crystal is sandwiched between both of these substrates, and a voltage between a pixel electrode whose potential is controlled by an external signal and a counter electrode which is maintained at a predetermined potential controls the amount of light transmitted through each pixel to display an image. To do.

FIG. 7 is a sectional view of a conventional AMLCD constructed as a direct-view display. This form of AML
In a CD, a backlight is generally provided behind the liquid crystal panel, and the TFT substrate 20 is placed on the backlight side and the counter substrate 2 is provided.
1 is placed on the display side. The illumination light 18 of the backlight is
The light is reflected by the black matrix 16 provided on the counter substrate to separate the boundaries between the pixels and improve the contrast, passes through the liquid crystal layer 19, and is emitted from above the TFT.

In the inverted staggered type TFT shown in FIG.
Since the gate electrode 4 is located on the transparent insulating substrate 7 side of the TFT substrate 20, the backlight irradiation light 18 is directly applied to the channel 1.
Although it does not enter 0, the light reflected by the black matrix 16 as described above enters the channel 10 and increases the leak current when the gate electrode 4 is turned off.
In general, the reflected light is not so strong that the increase in the off-current due to the reflected light does not particularly affect the display performance. However, when the backlight light is made stronger than usual, or when the number of scanning lines increases, the TF
When the OFF time is particularly longer than the ON time of T, the effect thereof becomes noticeable on the display and causes deterioration of image quality such as deterioration of display contrast. This means
The same applies not only to the display unit of a portable personal computer but also to a light valve of a projection display device.

In order to avoid the deterioration of the display contrast as described above, in the structure shown in FIG. 7, the inverted staggered T type is used.
An opaque light-shielding layer 11 is provided on the FT to suppress light incident on the channel. However, there is a problem in that the light shielding layer 11 itself is electrostatically charged and, in some cases, affects the channel 10 of the TFT as a so-called back channel and increases the leak current at the time of off. In order to avoid this problem, the light shielding layer 11 is connected to the scanning line, the signal line or the pixel electrode 5 and the potential of the light shielding layer 11 is stabilized to suppress an increase in leak current due to charging of the light shielding layer 11. Is proposed.

[0007]

In the above proposed method, when the light shielding layer is connected to any of the scanning line, the signal line or the pixel electrode, there are the following drawbacks.
First, when connecting the light shielding layer 11 to the signal line, the TFT
Since the drain electrode 9 of is connected to the pixel electrode 5,
During the charge retention period, the potential of the light-shielding layer 11 is 10 at maximum, which is lower than the source potential or the drain potential, whichever is lower.
It may be as high as V. When this influence extends to the back channel 10, the back gate effect increases the leak current at the time of off, and the desired effect cannot be obtained. Therefore, in this case, it is necessary to increase the film thickness of the protective insulating film 13 to, for example, about 1 μm or more so that the distance between the light shielding layer 11 and the back channel 10 becomes sufficiently long. This is the same when the light shielding layer 11 is connected to the pixel electrode 5. However, the provision of such a thick protective insulating film 13 causes a complicated process and a reduced yield in etching for forming a contact hole, wiring formation in the contact hole, and the like, which is a factor of cost increase. Becomes

On the other hand, when the light shielding layer 11 is connected to the scanning line (gate electrode 4), there are the following problems. During the charge retention period, the potential of the light shielding layer 11 is kept sufficiently lower than the lower one of the source voltage and the drain voltage of the TFT. Therefore, the back gate effect acts in the direction of reducing the leak current, and thus the protective insulating film 13
Can be thin. However, when this configuration is adopted, the gate insulating film 8 and the protective insulating film 13 are interposed between the light shielding layer 11 and the scanning line, and the total thickness of these is, for example, about 700 nm. Become. In all pixels, it is very difficult to form a contact hole through this large-thickness insulating film and connect the light-shielding layer and the scanning line with the wiring layer, and it is highly probable that a defect will occur at this connection portion. Quite expensive. In a pixel having a poor connection, when the gate voltage changes from on to off, the pixel potential fluctuates due to the electrostatic capacitance between the gate electrode 4 and the drain electrode 9, that is, a so-called feedthrough amount is different from that of a normal pixel. Will be different and will be visually recognized as an abnormal point. Therefore, the liquid crystal display panel adopting such a structure has a high probability of including defects, lowers the manufacturing yield, and causes a cost increase.

In view of the above, it is an object of the present invention to form a light-shielding layer in an active matrix liquid crystal display panel, which can suppress an increase in leak current due to a back gate effect, in a simple process and at a high yield. An object is to provide an active matrix liquid crystal display panel that can be manufactured at low cost.

[0010]

In order to achieve the above object, the active matrix liquid crystal display panel of the present invention comprises:
A first transparent insulating substrate in which pixel electrodes and thin film field effect transistors are formed in a matrix in each lattice portion formed by a plurality of scanning lines and a plurality of signal lines, and facing the first transparent insulating substrate. A second transparent insulating substrate that is disposed and has a transparent electrode at a position facing each of the pixel electrodes, a liquid crystal layer enclosed between the two transparent insulating substrates, and at least covers a channel portion of the thin film field effect transistor. In an active matrix liquid crystal display panel having an opaque conductive light-shielding layer formed by: forming an electrostatic capacitance portion between the scanning line and the scanning line. And a part of the light shielding layer is arranged to face the auxiliary layer via an insulating layer, and the light shielding layer and the auxiliary layer are connected via a contact hole. That And butterflies.

Here, in a preferred embodiment of the active matrix liquid crystal display panel of the present invention, the auxiliary layer is formed as a conductive layer at the same level as the pixel electrode and is insulated from the pixel electrode. In this case, it is not necessary to provide a special step for forming the auxiliary layer, and the entire manufacturing process is simplified. The auxiliary layer may be formed for each pixel, or one auxiliary line may be provided for each scanning line and may be commonly provided for the pixel groups in each row.

Further, the auxiliary layer can be formed as a conductive layer having the same level as the source electrode and the drain electrode of the thin film field effect transistor and can be insulated from the source electrode and the drain electrode. Similarly, the manufacturing process is simplified. Further, in this case, it is preferable that the light shielding layer is formed as a conductive layer having the same level as the signal line, and the signal line and the source electrode are connected by a contact hole.

[0013]

In the active matrix liquid crystal display panel of the present invention, an auxiliary layer forming an electrostatic capacitance portion is provided between the scanning electrode and the light shielding layer and the auxiliary layer are connected to each other. Since the potential is stably maintained at substantially the same potential as that of the scanning line, the back gate effect of the light shielding layer acts in the direction of suppressing the leak current, and the leak current of the TFT during the charge holding period can be suppressed to be small. I can. Further, since the back gate effect due to the light shielding layer does not occur, the insulating layer can be formed thin and the yield in the etching process for forming the contact hole is improved.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in more detail based on preferred embodiments of the present invention with reference to the drawings. FIG. 1 is a plan view showing an active matrix liquid crystal display panel (AMLCD) according to a first embodiment of the present invention, FIGS. 2 (a) and 2 (b).
2A and 2B are cross-sectional views taken along lines AA 'and BB' of FIG. 1, respectively.
This embodiment will be described with reference to FIGS. 1 and 2.

On the main surface of the first light-transmissive insulating substrate 7 made of a glass plate or the like, a large number of scanning lines 1 and a large number of signal lines 2 are crossed with each other to form a first light-transmissive insulating substrate. 7 main surfaces are divided into a grid. Within each grid, a set of active pixel elements each including a TFT arranged near the intersection of the scanning line 1 and the signal line 2 and a pixel electrode 5 driven by this TFT is arranged. The TFT has a gate electrode 4
And a channel portion formed of the island-shaped amorphous silicon film 10 provided on the gate electrode 4 with the insulating film 8 interposed therebetween, and provided on the surface of the amorphous silicon film 10 and the surface of the insulating film 8. It is composed of a source electrode 3 and a drain electrode 9. Here, the gate electrode 4 of the TFT is formed integrally with the scanning line 1, and the source electrode 3 is formed integrally with the signal line 2.

The pixel electrode 5 is connected to the drain electrode 9, and above the scanning line 1 adjacent to the corresponding gate electrode 4, a conductive light-shielding auxiliary layer formed in the same layer as the pixel electrode 5 ( An auxiliary layer) 12 is provided. Light-shielding auxiliary layer 1
2 has a substantially rectangular shape with a width slightly smaller than the width of the scanning line 1, and is separated from the scanning line 1 by an insulating film 8. A protective insulating film 13 is provided to cover the entire TFT array except the central portion 14 of the pixel electrode 5 and the peripheral terminal portion. Further, a conductive light shielding layer 11 is formed on the protective insulating film 13, and the light shielding layer 11 is formed by the amorphous silicon film 10.
And a projection portion extending above the light shielding auxiliary layer 12 from the substantially rectangular portion. The light shielding layer 11 and the light shielding auxiliary layer 12 are the protective insulating film 1
3 are connected through a contact hole 6 formed inside. Here, the light shielding layer 11 and the light shielding auxiliary layer 12 are not fixed to any potential by the metal wiring.

In the structure shown in FIG. 1, the light shielding auxiliary layer 12
Of the gate insulating film 8 is ε and d, respectively.
Then, between the light shielding auxiliary layer 12 and the scanning line 1, _CHG
There is a capacitance of εS / d. That is, the light shielding auxiliary layer 12 and the scanning line 1 form a capacitance section. Here, the light shielding layer 1
1 is the capacitance between the source electrode 3 and C _LS , and the light shielding layer 11
The capacitance between the drain electrode 9 and the drain electrode 9 is C _LD , and the light shielding layer 11
And the capacitance between the back channel 10 of the TFT and C _LB
And At this time, when the charge amount of the light blocking layer 11 and the light blocking auxiliary layer 12 is Q, the potential V _L and the source potential V _S of the light blocking layer 11, the drain potential V _D, the gate potential V _G, between the back channel potential V _B Have a relationship represented by the following equation. _{V L = (Q + C HG} V G + C LS V S + C LD V D + C LB V B) / (C HG + C LS + C LD + C LB) ·· (1)

In the above equation, if the electrostatic capacitance C _HG is set sufficiently larger than the other electrostatic capacitances, the potential V _{L of the} light shielding layer is set even if the entire light shielding layer 11 is positively charged. Gate potential V _G
Can be close enough to. In the structure of this embodiment,
Since the electrostatic capacitance C _HG between the light shielding auxiliary layer 12 and the scanning line 1 can be easily increased, this condition can be satisfied. Therefore, the light shielding layer 11 can be maintained / fixed at substantially the same potential as the scanning line 1.

The gate potential V _G is
Since it is sufficiently negative with respect to the drain voltage and the source voltage, V _L <V _B , and the back gate effect acts to reduce the leak current. Therefore, even if the thickness of the protective insulating film 13 between the back channel 10 and the light shielding layer 11 is reduced to about 200 nm, the leak current does not increase. Further, by making the protective insulating film 13 thin, the connection between the light shielding layer 11 and the light shielding auxiliary layer 12 in all the pixels can be surely performed without inducing defects, and the process is facilitated. . Further, according to this structure, since the light shielding layer 11 is not connected to the signal line 2, the pixel electrode 5 or the scanning line 1 by the contact hole, the problem of the conventional technique which occurs when they are connected to each of them. It can be avoided.

Instead of the above structure, the source electrode 3 and the drain electrode 9 of the TFT and the light-shielding auxiliary layer 12 can be formed at the same time with a transparent metal layer of the same layer as the pixel electrode 5. In this case, after forming the transparent metal layer, the light-shielding layer 11 and the signal line 2 are formed at once by the metal layer of the same layer having sufficiently low resistance, and through the contact hole formed in the protective insulating film 13, The signal line 2 and the source electrode 3, and the light shielding layer 11 and the light shielding auxiliary layer 12 are connected to each other. According to this structure, a TFT substrate having a light shielding layer with stable potential can be manufactured without increasing the number of steps compared with the manufacturing process of a TFT substrate having no light shielding layer.

3 (a) to 3 (c) are plan views sequentially showing respective process steps of the AMLCD in the method for manufacturing the AMLCD of the first embodiment. First, a chromium film is deposited to a thickness of 100 nm on a translucent insulating substrate by a sputtering method and patterned. As a result, the gate electrode 4 and the scanning line 1 are obtained. Then, a silicon nitride film which covers the entire surface and becomes the gate insulating film 8 is deposited to a thickness of 400 nm. Further, a 250-nm-thick non-doped amorphous silicon film and a 20-nm-thick N-type amorphous silicon film are sequentially deposited, and these are patterned to form an island-shaped amorphous silicon film on the gate electrode 4. Form 10. Next, a chromium film is further deposited to a thickness of 100 nm and patterned to form the signal line 2 and the source electrode 3 and the drain electrode 9 formed integrally with the signal line 2, and the structure shown in FIG. To get

Next, an ITO film is deposited to a thickness of 100 nm and patterned, and is insulated from the pixel electrode 5 connected to the drain electrode 9 and the scanning line 1 above the scanning line 1 through the insulating film 8. And a light shielding auxiliary layer 12 having a substantially rectangular shape. Then, a protective insulating film 13 having a thickness of 200 nm is deposited on the entire surface, and the protective insulating film 13 is removed by etching in a region 14 on the pixel electrode 5, and at the same time, a part of the light shielding auxiliary layer 12 is contacted. The holes 6 are formed to obtain the structure shown in FIG.

Further, a chromium film of 200 nm is deposited and patterned to obtain a light shielding layer 11 extending above the channel portion of the TFT and above the light shielding auxiliary layer 12. By being formed in this way, the light shielding layer 11 is connected to the light shielding auxiliary layer 12 through the contact hole 6. As a result, the structure shown in FIG. 3C is obtained.

In the above manufacturing process, the light shielding layer 11
The step when connecting the light shielding auxiliary layer 12 and the light shielding auxiliary layer 12 is approximately 200 nm, which is equal to the thickness of the protective insulating film 13. As a thickness for connecting the step, the thickness of the chromium film is 200 n
m is sufficient, so that the formation of a connection via a contact hole has a high probability of success. Therefore, the light shielding layer 11
The occurrence of defects due to poor connection between the light shielding auxiliary layer 12 and the light shielding auxiliary layer 12 can be ignored.

The size of each pattern formed in the above embodiment differs depending on, for example, the standard of the applied liquid crystal panel. As an example, when applied to a color display having a diagonal size of about 20 cm and a number of pixels of 640 × 480, one pixel has a horizontal length of about 100 μm and a vertical length of 300 μm in FIG. It is a degree. In this case, the TFT can be designed with a channel length of 4 μm and a channel width of 12 μm. Further, the overlapping area of the light shielding layer 11 with the drain electrode 9, the source electrode 3 and the back channel of the TFT is set to 2 μm for the overlapping length of the source electrode 3 and the drain electrode 9 and the light shielding layer 11, respectively. If the protruding length of the longitudinal direction from the source electrode 3 and the drain electrode 9 of the island-shaped amorphous silicon film 10 and 2 [mu] m, a ² order of 128 .mu.m.

On the other hand, when the width of the scanning line 1 is about 14 μm, the width of the light shielding auxiliary layer 12 can be about 12 μm and the length of the scanning line 1 in the extending direction can be about 32 μm. In this case, the area of the light shielding auxiliary layer is 384 μm ² . By doing so, the sum of the capacitances of the light shielding layer 11, the source electrode 3, the drain electrode 9 and the back channel is 128 μm.
2, the capacitance between the light-shielding auxiliary layer 12 and the scanning line 1 is about 1.5 times. Under this condition, as can be easily understood from the formula (1), even if positive static electricity is charged on the light shielding layer,
Since the electrostatic capacitance due to the overlapping area S of the scanning line 1 and the light-shielding auxiliary layer 12 is sufficiently large, the potential of the light-shielding layer 11 is lower than the potentials of the source electrode 3, the drain electrode 9 and the channel 10 during the charge retention period. Therefore, the phenomenon that the off-current increases due to the back channel effect can be avoided.

Next, an AMLCD according to the second embodiment of the present invention will be described. FIG. 4 is a plan view of the AMLCD of this embodiment,
5A and 5B are cross-sectional views taken along the lines AA ′ and BB ′ of FIG. 4, respectively.

On the first translucent insulating substrate 7 made of a glass plate or the like, the scanning lines 1 including the gate electrodes 4 and the signal lines 2 are arranged in a grid pattern so as to intersect each other, and the scanning lines 1 and the signal lines 2 are arranged in each grid. Pixels are formed. Within each grid, a TFT arranged near the intersection of the scanning line 1 and the signal line 2 and a pixel electrode 5 driven by this TFT are arranged. The TFT includes a gate electrode 4 formed integrally with the scanning line 1, a channel portion formed of an island-shaped amorphous silicon film 10 provided on the gate electrode 4 via an insulating film 8, and an amorphous silicon film. The source electrode 3 and the drain electrode 9 are provided on the surface of the insulating film 8 including a part of the surface 10.

Here, the source electrode 3 and the drain electrode 9 of the TFT, the pixel electrode 5 formed integrally with the drain electrode 9, and a portion above the scanning line 1 are insulated from the scanning line 1 via an insulating film 8. The light shielding auxiliary layer 12 is formed as a metal layer made of the same layer. A protective insulating film 13 is provided so as to cover the whole of the pixel electrode 5 except for the central portion 14 and the peripheral terminal portion. A contact hole is formed in the protective insulating film 13 on the light shielding auxiliary layer 12 and the source electrode 3. On this protective insulating film 13,
A light-shielding layer 11 covering the channel part of the TFT and a signal line 2 formed of the same layer as the light-shielding layer 11 are formed. The light-shielding layer 11 and the light-shielding auxiliary layer 12 and the signal line 2 and the source electrode 3 are respectively provided via contact holes 6. It is connected.

FIGS. 6A to 6C are plan views sequentially showing respective process steps of the AMLCD in the method for manufacturing the AMLCD of the second embodiment. First, a chromium film is deposited to a thickness of 100 nm on a translucent insulating substrate by a sputtering method and patterned. As a result, the scanning line 1 including the gate electrode 4 is obtained. Then, a silicon nitride film serving as a gate insulating film is deposited on the surface to a thickness of 400 nm, and a non-doped amorphous silicon film having a thickness of 250 nm and an N-type amorphous silicon film having a thickness of 20 nm are sequentially deposited on the silicon nitride film. Then, the island-shaped amorphous silicon film 10 is formed on the gate electrode 4 by depositing it on the gate electrode 4 and patterning it. Subsequently, an ITO film having a thickness of 100 nm is laminated and patterned to form a source electrode 3, a drain electrode 9, a pixel electrode 5 formed integrally therewith, and a portion above the scanning line 1 via an insulating film. The light shielding auxiliary layer 12 to be insulated is formed of the same metal layer. Thereby, the structure shown in FIG. 6A is obtained.

Next, a protective insulating film 13 having a thickness of 200 nm is deposited on the surface, and the protective insulating film 13 is removed by etching in a region 14 on the pixel electrode 5, and at the same time, a part of the light shielding auxiliary layer 12 is formed. Then, a contact hole 6 is formed in a part of the source electrode to obtain the structure shown in FIG.

After that, a chromium film of 200 nm is further deposited and patterned to form the light shielding layer 11 and the signal line 2 in the same layer. Light-shielding layer 11 formed in this way
Are connected to the light shielding auxiliary layer 12 through the contact holes 6. Similarly, the signal line 2 is connected to the source electrode 3 via a contact hole. As a result, FIG.
The structure shown in (c) is obtained.

In the above manufacturing process, the light shielding layer 11
And the light-shielding auxiliary layer 12, and the step when connecting the signal line 2 and the source electrode 3 through the contact holes, respectively,
It is equal to the thickness of the protective insulating film 13 and is approximately 200 nm. The thickness of the chromium film of 200 nm is sufficient as the thickness for connecting the steps, and the connection through these contact holes is successful with a high probability, so that the pixel defects due to the connection failure hardly occur. .

Further, according to the second embodiment, since the signal line and the light shielding layer can be formed by the same layer, a structure having almost the same performance as that of the first embodiment is formed, exposed and etched. The number of steps can be reduced once compared to the first embodiment. Therefore, the manufacturing cost can be significantly reduced as compared with the first embodiment.

Although the preferred embodiments of the present invention have been described in the above description of each embodiment, the present invention can be modified and changed in various ways from the configuration of the above embodiment.

[0036]

As described above in detail, according to the active matrix liquid crystal display panel of the present invention, a TFT substrate having a potential-stable light shielding layer can be formed with a small number of steps and a high yield. The invention has a remarkable effect of realizing a low-cost liquid crystal panel having good display characteristics.

[Brief description of the drawings]

FIG. 1 is a plan view showing the structure of an AMLCD according to a first embodiment of the present invention.

2A and 2B are cross-sectional views taken along the lines AA ′ and BB ′ of FIG. 1, respectively.

3 (a) to 3 (c) are plan views of the AMLCD manufacturing method in FIG.

FIG. 4 is a plan view showing the structure of an AMLCD according to a second embodiment of the present invention.

5A and 5B are cross-sectional views taken along lines AA ′ and BB ′ of FIG. 4, respectively.

6 (a) to 6 (c) are plan views of the AMLCD manufacturing method shown in FIG.

FIG. 7 is a sectional view of a conventional AMLCD.

[Explanation of symbols]

 1 scanning line 2 signal line 3 source electrode 4 gate electrode 5 pixel electrode 6 contact hole 7 insulating substrate 8 insulating film 9 drain electrode 10 amorphous silicon film 11 light shielding layer 12 light shielding auxiliary layer 13 protective insulating film 14 protection on pixel electrode Area for removing insulating film 15 Alignment film 16 Black matrix 17 Transparent electrode 18 Illumination light 19 Liquid crystal layer 20 TFT substrate 21 Counter substrate

Claims (4)

(57) [Claims] 1. A first transparent insulating substrate in which pixel electrodes and thin film field effect transistors are formed in a matrix in each lattice portion formed by a plurality of scanning lines and a plurality of signal lines,
A second transparent insulating substrate which is arranged so as to face the first transparent insulating substrate and has a transparent electrode at a position facing each of the pixel electrodes; and a liquid crystal layer which is sealed between the both transparent insulating substrates. An active matrix liquid crystal display panel having at least an opaque conductive light-shielding layer formed so as to cover the channel portion of the thin film field effect transistor, the scanning being provided so as to face the scanning line via an insulating layer. A conductive auxiliary layer that forms a capacitance portion between the light shielding layer and a line, and a part of the light shielding layer is arranged to face the auxiliary layer with an insulating layer interposed therebetween. An active matrix liquid crystal display panel, characterized in that the layers are connected through contact holes. 2. The active matrix liquid crystal display panel according to claim 1, wherein the auxiliary layer is formed as a conductive layer having the same level as the pixel electrode and is insulated from the pixel electrode. 3. The auxiliary layer is formed as a conductive layer at the same level as the source electrode and the drain electrode of the thin film field effect transistor, and is insulated from the source electrode and the drain electrode. Active matrix liquid crystal display panel. 4. The light shielding layer is formed as a conductive layer having the same level as the signal line, and the signal line and the source electrode are connected via a contact hole.
4. The active matrix liquid crystal display panel according to 1.