JP2674150B2 - Layout method of semiconductor integrated circuit - Google Patents
Layout method of semiconductor integrated circuitInfo
- Publication number
- JP2674150B2 JP2674150B2 JP63276462A JP27646288A JP2674150B2 JP 2674150 B2 JP2674150 B2 JP 2674150B2 JP 63276462 A JP63276462 A JP 63276462A JP 27646288 A JP27646288 A JP 27646288A JP 2674150 B2 JP2674150 B2 JP 2674150B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- pair
- integrated circuit
- semiconductor integrated
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路のレイアウト方法に関し、特
に特性のそろった１対の回路を有する半導体集積回路の
レイアウト法に関する。The present invention relates to a layout method of a semiconductor integrated circuit, and more particularly to a layout method of a semiconductor integrated circuit having a pair of circuits with uniform characteristics.
〔従来の技術〕 従来、この種の半導体集積回路は平衡型増幅回路を構
成するために個々の回路を有する半導体チップを個別に
形成し、ペレッタイズした後に特性のそろった１対の半
導体チップを選別して組合せることにより実現してい
た。[Prior Art] Conventionally, in this type of semiconductor integrated circuit, a semiconductor chip having individual circuits is individually formed to form a balanced amplifier circuit, and after pelletizing, a pair of semiconductor chips with uniform characteristics are selected. It was realized by combining them.
このように従来の半導体集積回路は、ペレッタイズ後
に特性のそろった１対の半導体チップを選別して平衡型
増幅回路を構成していたので、特性のそろった１対の半
導体チップを見出すのに手間がかかるという欠点があ
る。As described above, in the conventional semiconductor integrated circuit, since a pair of semiconductor chips with uniform characteristics are selected after pelletizing to form a balanced amplifier circuit, it is troublesome to find a pair of semiconductor chips with uniform characteristics. There is a drawback that it costs.
本発明の半導体集積回路は、入力電極と出力電極を対
向する２辺の近傍にそれぞれ配置し、バイアス電極と接
地電極を他の１辺の近傍に配置した素子領域を有する半
導体チップを、電極を配置していない残りの１辺に関し
て線対称に配置して対をなすレイアウトを有している。In the semiconductor integrated circuit of the present invention, an input electrode and an output electrode are respectively arranged in the vicinity of two opposite sides, and a bias electrode and a ground electrode are arranged in the vicinity of another side. It has a layout in which the remaining one side which is not arranged is arranged line-symmetrically to form a pair.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を説明するための半導体チ
ップのレイアウト図である。FIG. 1 is a layout diagram of a semiconductor chip for explaining an embodiment of the present invention.
図に示すように、スクライブ領域１により囲まれた素
子形成領域２の内に入力電極3,出力電極4,ゲートバイア
ス電極5,接地電極6,ドレインバイアス電極７をそれぞれ
設けたGaAsMESFETを含むモノリシック化マイクロ波１段
増幅回路を設け、Ａ−Ａ′線に対して線対称で同一パタ
ーンを有する一対の回路を形成する。ここで、素子形成
領域２のＡ−Ａ′線に面する辺の近傍には電極を設けて
いない。As shown in the figure, a monolithic structure including a GaAs MESFET in which an input electrode 3, an output electrode 4, a gate bias electrode 5, a ground electrode 6, and a drain bias electrode 7 are provided in an element formation region 2 surrounded by a scribe region 1 A microwave one-stage amplifier circuit is provided to form a pair of circuits which are line-symmetric with respect to the line AA ′ and have the same pattern. Here, no electrode is provided in the vicinity of the side of the element formation region 2 facing the line AA ′.
このようにして、Ａ−Ａ′線では半導体チップを切断
しないで使用することにより、半導体ウェーハ内の隣接
した素子形成領域に形成した回路の特性がほぼ等しくな
ることを利用して平衡型増幅回路を実現できるため、従
来のように分割された半導体チップの集合より特性のそ
ろった１対の半導体チップを探す手間がない。また、近
年、GaAsMESFETのゲート長をサブミクロンの寸法で形成
するために電子ビームによるウェーハ直接露光（EB直
描）法が使用されているが、この方法では、数個のチッ
プ毎に目合せを行なう必要があるので、従来に増して隣
接する回路の特性が等しくなる傾向があるので本発明は
さらに有効となる。In this way, by using the semiconductor chip on the line AA ′ without cutting it, the characteristics of the circuits formed in the adjacent element forming regions in the semiconductor wafer become substantially equal, which makes use of the balanced amplifier circuit. Therefore, there is no need to search for a pair of semiconductor chips having more uniform characteristics than a conventional set of divided semiconductor chips. In recent years, a wafer direct exposure (EB direct writing) method using an electron beam has been used to form a GaAs MESFET gate length in a submicron dimension. In this method, alignment is performed for several chips. Since it is necessary to carry out the present invention, the characteristics of adjacent circuits tend to be more equal than in the conventional case, and the present invention is more effective.
第２図は本発明による半導体チップを使用した増幅回
路の一例を示すブロック図である。FIG. 2 is a block diagram showing an example of an amplifier circuit using a semiconductor chip according to the present invention.
図において、半導体チップ8,9は第１図に示す１対の
増幅回路を有する半導体チップを分割したものであり、
半導体チップ10は第１図に示す増幅回路対である。半導
体チップ８の入力電極３に入力された入力信号は半導体
チップ8,9の増幅回路で増幅された後、3dB結合器11を介
して半導体チップ10の平衡型増幅回路でさらに増幅さ
れ、高出力電力を得た後3dB結合器12を経て出力され
る。In the figure, semiconductor chips 8 and 9 are obtained by dividing the semiconductor chip having a pair of amplifier circuits shown in FIG.
The semiconductor chip 10 is the amplifier circuit pair shown in FIG. The input signal input to the input electrode 3 of the semiconductor chip 8 is amplified by the amplifier circuit of the semiconductor chips 8 and 9, and then further amplified by the balanced amplifier circuit of the semiconductor chip 10 via the 3 dB coupler 11, resulting in high output. After obtaining the power, it is output through the 3 dB coupler 12.
本実施例では本発明の平衡型回路を高出力電力を目的
として使用しているのみならず、増幅回路対を有する半
導体チップを分割し、それらを初段及び２段目の増幅の
ために使用している。このように、本発明は、特性のそ
ろった平衡回路対を提供するのみならず、必要な場合に
は対を分割して使用することも可能ならしめるという効
果があり、多数のチップを使用して目的の特性を得るマ
イクロ波回路モジュールの設計の自由度を増すことがで
きる。In this embodiment, not only the balanced circuit of the present invention is used for the purpose of high output power, but also the semiconductor chip having the amplifier circuit pair is divided and used for the first and second stage amplification. ing. As described above, the present invention not only provides a balanced circuit pair with uniform characteristics, but also has the effect of allowing the pair to be divided and used when necessary, and a large number of chips are used. It is possible to increase the degree of freedom in designing a microwave circuit module that obtains desired characteristics.
さらに、平衡回路対の一方がオンウェーハ測定で不良
であることが判明すれば、これを分割して他方を単体の
回路として使用でき、チップの有効利用を可能ならしめ
るという効果もある。Further, if one of the balanced circuit pairs is found to be defective in the on-wafer measurement, it can be divided and the other can be used as a single circuit, which has the effect of enabling effective use of the chip.
以上説明したように本発明は、入力電極と出力電極を
対向する２辺の近傍にそれぞれ配置し、バイアス電極と
接地電極を他の１辺の近傍に配置したチップを、電極を
配置していない残りの１辺に関して線対称に配置して対
をなすレイアウトを採用することにより、特性がそろっ
た平衡対が容易に得られる、平衡対を分割しても使用で
きるのでモジュール設計等の自由度が増す、及び平衡対
の一方が不良の場合は分割して他方を単体として使用し
チップの有効利用を可能ならしめるという効果がある。As described above, according to the present invention, the chip in which the input electrode and the output electrode are arranged in the vicinity of two opposite sides and the bias electrode and the ground electrode are arranged in the vicinity of the other one side is not arranged. By adopting a layout in which the remaining one side is arranged in line symmetry to form a pair, a balanced pair with uniform characteristics can be easily obtained. Since the balanced pair can be used even if it is divided, the degree of freedom in module design etc. is increased. If one of the balanced pairs is defective, there is an effect of dividing and using the other as a single unit to enable effective use of the chip.
第１図は本発明の一実施例を説明するための半導体チッ
プのレイアウト図、第２図は本発明による半導体チップ
を使用した増幅回路の一例を示すブロック図である。 １……スクライブ領域、２……素子形成領域、３……入
力電極、４……出力電極、５……ゲートバイアス電極、
６……接地電極、７……ドレインバイアス電極、8,9,10
……半導体チップ、11,12……3dB結合器。FIG. 1 is a layout diagram of a semiconductor chip for explaining an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of an amplifier circuit using the semiconductor chip according to the present invention. 1 ... scribe region, 2 ... element forming region, 3 ... input electrode, 4 ... output electrode, 5 ... gate bias electrode,
6 ... Ground electrode, 7 ... Drain bias electrode, 8, 9, 10
…… Semiconductor chip, 11,12 …… 3dB coupler.
Claims (1)
レアウト方法において、入力電極と出力電極を対向する
２辺の近傍にそれぞれ配置し、バイアス電極と接地電極
を他の１辺の近傍に配置した素子領域を有する半導体チ
ップと、前記電極を設けた３辺以外の残りの１辺に関し
て線対称に配置して対をなして設けた素子領域を有する
半導体チップを有することを特徴とする半導体集積回路
のレイアウト方法。1. A method for laying out a semiconductor integrated circuit formed on a semiconductor substrate, wherein an input electrode and an output electrode are arranged in the vicinity of two opposing sides, and a bias electrode and a ground electrode are arranged in the vicinity of another side. And a semiconductor chip having a device region having a pair of device regions arranged symmetrically with respect to the remaining one side other than the three sides provided with the electrodes. Circuit layout method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63276462A JP2674150B2 (en) | 1988-10-31 | 1988-10-31 | Layout method of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63276462A JP2674150B2 (en) | 1988-10-31 | 1988-10-31 | Layout method of semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02122559A JPH02122559A (en) | 1990-05-10 |
| JP2674150B2 true JP2674150B2 (en) | 1997-11-12 |
Family
ID=17569782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63276462A Expired - Lifetime JP2674150B2 (en) | 1988-10-31 | 1988-10-31 | Layout method of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2674150B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4091838B2 (en) * | 2001-03-30 | 2008-05-28 | 富士通株式会社 | Semiconductor device |
-
1988
- 1988-10-31 JP JP63276462A patent/JP2674150B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02122559A (en) | 1990-05-10 |
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