CN111294002A - Integrated circuit capable of simultaneously preparing multiple-channel high-precision operational amplifier - Google Patents
Integrated circuit capable of simultaneously preparing multiple-channel high-precision operational amplifier Download PDFInfo
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Abstract
The invention relates to an integrated circuit capable of simultaneously preparing multiple channels of high-precision operational amplifiers, when an operational amplifier unit block is integrally packaged, a reference oscillator circuit is selected as an oscillator unit of the high-precision operational amplifier through an oscillator signal processing circuit between unit bodies, so that the high-precision operational amplifier carries out required operational amplification according to an oscillator signal of the selected oscillator unit; when the operational amplifier unit bodies in the operational amplifier unit blocks are cut by using the scribing channels and are respectively packaged, the reference unit high-precision operational amplifier and the non-reference unit high-precision operational amplifier can be simultaneously obtained, the reference unit high-precision operational amplifier performs required operational amplification according to an oscillator signal of a reference oscillator circuit, the non-reference unit high-precision operational amplifier performs required operational amplification according to an oscillator signal of a non-reference oscillator circuit, different channel packaging and manufacturing of the required high-precision operational amplifier can be realized, the packaging and manufacturing cost is reduced, and the packaging and manufacturing method is safe and reliable.
Description
Technical Field
The invention relates to an integrated circuit, in particular to an integrated circuit capable of simultaneously preparing multiple-channel high-precision operational amplifiers, belonging to the technical field of high-precision operational amplifiers.
Background
Operational amplifiers (operational amplifiers) are widely used in integrated circuits, and commonly used operational amplifiers generally include single-channel operational amplifiers, dual-channel operational amplifiers, and four-channel operational amplifiers.
Currently, high-precision operational amplifiers are generally manufactured in the form of integrated circuits. For the high-precision operational amplifiers, the circuit also comprises oscillator units capable of generating clock signals, namely at least one oscillator unit exists in each high-precision operational amplifier; for example, during design, an oscillator unit can be designed in a single-channel high-precision operational amplifier and a double-channel high-precision operational amplifier. In the process of an integrated circuit, a single-channel high-precision operational amplifier can be directly packaged to obtain a double-channel high-precision operational amplifier, at the moment, two oscillator units exist in the obtained double-channel high-precision operational amplifier, generally, the frequencies of clock signals generated by the two oscillator units are deviated to some extent, so that the two oscillator units in the double-channel high-precision operational amplifier obtained by the single-channel high-precision operational amplifier can generate intermodulation during working, interference is generated, and the work of the packaged double-channel high-precision operational amplifier is influenced.
In order to ensure the working reliability of the dual-channel high-precision operational amplifier, the process of the dual-channel high-precision operational amplifier can be directly designed in the integrated circuit design, only one oscillator unit is arranged in the dual-channel high-precision operational amplifier obtained in the packaging process, namely, the dual-channel high-precision operational amplifier and the single-channel high-precision operational amplifier adopt two independent mask plates to respectively carry out two independent integrated circuit designs, so that the integrated circuit in the state can not be used for packaging to obtain the single-channel operational amplifier, and the design and manufacturing cost can be increased.
For the design of an integrated circuit with a single-channel high-precision operational amplifier and a double-channel high-precision operational amplifier sharing a set of mask, one layer of mask needs to be modified finally, and under the condition, the method for modifying the mask can be used for realizing the packaging and manufacturing of the single-channel high-precision operational amplifier or the packaging and manufacturing of the double-channel high-precision operational amplifier, but the modification of the mask can also increase the design and manufacturing cost. In addition, for the double-channel high-precision operational amplifier obtained by packaging the single-channel high-precision operational amplifier, the oscillator unit in the double-channel high-precision operational amplifier can be set in a wire bonding mode during packaging so as to ensure the working reliability of the double-channel high-precision operational amplifier; but the cost is also increased by wire bonding.
It is well known to those skilled in the art that, similar to the relationship between the two-channel high-precision operational amplifier and the single-channel high-precision operational amplifier, the four-channel high-precision operational amplifier and the two-channel high-precision operational amplifier have the same problem in package manufacturing, that is, the high-precision operational amplifiers of different channels cannot be simultaneously and effectively prepared without significantly increasing the design and manufacturing cost.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, provides an integrated circuit capable of simultaneously preparing multiple channels of high-precision operational amplifiers, has compact structure, can simultaneously prepare the packaging and manufacturing of the required channels of high-precision operational amplifiers, reduces the packaging and manufacturing cost, and has wide application range, safety and reliability.
According to the technical scheme provided by the invention, the integrated circuit capable of realizing the multi-channel high-precision operational amplifier comprises a wafer body and a plurality of operational amplifier unit blocks prepared on the wafer body, wherein each operational amplifier unit block comprises two operational amplifier unit bodies and a scribing channel for spacing the operational amplifier unit bodies, and the operational amplifier unit bodies are positioned on two sides of the scribing channel; each operational amplifier unit body comprises an operational amplification circuit and an oscillator circuit matched with the operational amplification circuit;
an inter-unit oscillator signal processing circuit is further provided in each operational amplifier unit block, and in the operational amplifier unit block, one operational amplifier unit is set as a reference unit operational amplifier and the other operational amplifier unit is set as a non-reference unit operational amplifier; in the reference unit operational amplifier, a reference oscillator circuit is in adaptive connection with a reference operational amplifying circuit and an inter-unit oscillator signal processing circuit; in the non-reference unit operational amplifier, a non-reference operational amplification circuit is in adaptive connection with a non-reference oscillator circuit through an inter-unit oscillator signal processing circuit;
when the operational amplifier unit block is integrally packaged to obtain the required high-precision operational amplifier, a reference oscillator circuit is selected as an oscillator unit of the high-precision operational amplifier through an inter-unit oscillator signal processing circuit, so that the high-precision operational amplifier performs required operational amplification according to an oscillator signal of the selected oscillator unit;
when the operational amplifier unit bodies in the operational amplifier unit blocks are cut by using the dicing streets and are respectively packaged, the reference unit high-precision operational amplifier and the non-reference unit high-precision operational amplifier can be simultaneously obtained, the reference unit high-precision operational amplifier performs required operational amplification according to the oscillator signal of the reference oscillator circuit, and the non-reference unit high-precision operational amplifier performs required operational amplification according to the oscillator signal of the non-reference oscillator circuit.
The inter-unit oscillator signal processing circuit comprises a selection signal generating circuit and a signal selecting circuit arranged on the non-reference unit operational amplifier, wherein the selection signal generating circuit, the reference oscillator circuit and the non-reference oscillator circuit can be connected with the non-reference operational amplifier circuit through the signal selecting circuit;
the selection signal generating circuit comprises a reference unit circuit arranged in the reference unit operational amplifier, a scribing channel conducting wire arranged in the scribing channel and a non-reference unit circuit arranged in the non-reference unit operational amplifier, wherein the reference unit circuit is connected with the non-reference unit circuit through the scribing channel conducting wire;
when the operational amplifier unit block is integrally packaged to obtain the required high-precision operational amplifier, the reference unit part circuit is kept connected with the non-reference unit part circuit through a scribing channel conducting wire, the selection signal generating circuit loads a reference oscillator circuit selection signal to the signal selection circuit, and the signal selection circuit enables the non-reference operational amplifier circuit to receive an oscillator signal of the reference oscillator circuit according to the reference oscillator circuit selection signal;
when the operational amplifier unit bodies in the operational amplifier unit blocks are cut and respectively packaged by using the scribing streets, the scribing street conducting wires are in a disconnected state, and the connection between the reference unit part circuit and the non-reference unit part circuit and the electrical connection between the reference oscillator circuit and the signal selection circuit are disconnected through the scribing street conducting wires; the selection signal generating circuit loads a non-reference oscillator circuit selection signal to the signal selection circuit, and the signal selection circuit enables the non-reference operational amplification circuit to receive an oscillator signal of the non-reference oscillator circuit according to the non-reference oscillator selection signal.
The signal selection generating circuit comprises an inverter U1 and an inverter U2, wherein the output end of the inverter U1 is connected with the input end of the inverter U2, and the output end of the inverter U1 and the output end of the inverter U2 are both connected with the signal selection circuit;
the input end of the phase inverter U1 is connected with one end of a capacitor C1, one end of a scribing channel wire and the drain end of a PMOS tube P2, the other end of the capacitor C1 is grounded, the other end of the scribing channel wire is grounded through a resistor R1, the gate end of the PMOS tube P2 is connected with the gate end of the PMOS tube P1 and the drain end of the PMOS tube P1, the drain end of the PMOS tube P1 is grounded through a current source I1, and the source end of the PMOS tube P1 and the source end of the PMOS tube P2 are both connected with a power supply VDD.
The signal selection circuit comprises an AND gate U3, an AND gate U4 and an OR gate U5, wherein the input end of the AND gate U3 is connected with the output end of the inverter U1 and the output end of the reference oscillator circuit, the input end of the AND gate U4 is connected with the output end of the inverter U2 and the output end of the non-reference oscillator circuit, the output end of the AND gate U3 and the output end of the AND gate U4 are connected with the input end of the OR gate U5, and the output end of the OR gate U5 is connected with the non-reference operational amplification circuit.
The operational amplifier unit body is a single-channel high-precision operational amplifier or a multi-channel high-precision operational amplifier.
The width of the scribing channel is 60-80 μm.
The invention has the advantages that: setting an inter-cell oscillator signal processing circuit in each operational amplifier unit block, and when the operational amplifier unit block is integrally packaged to obtain a required high-precision operational amplifier, selecting a reference oscillator circuit as an oscillator unit of the high-precision operational amplifier through the inter-cell oscillator signal processing circuit so that the high-precision operational amplifier performs required operational amplification according to an oscillator signal of the selected oscillator unit; when the operational amplifier unit bodies in the operational amplifier unit blocks are cut by using the scribing channels and are respectively packaged, the reference unit high-precision operational amplifier and the non-reference unit high-precision operational amplifier can be simultaneously obtained, the reference unit high-precision operational amplifier performs required operational amplification according to an oscillator signal of a reference oscillator circuit, the non-reference unit high-precision operational amplifier performs required operational amplification according to an oscillator signal of a non-reference oscillator circuit, the packaging and manufacturing of the required channel high-precision operational amplifier can be simultaneously prepared, the packaging and manufacturing cost is reduced, the application range is wide, and the method is safe and reliable.
Drawings
FIG. 1 is a schematic view of a wafer according to the present invention.
Fig. 2 is a block diagram of an operational amplifier cell according to the present invention.
Fig. 3 is a schematic circuit diagram of the signal selection generating circuit of the present invention.
Fig. 4 is a circuit schematic diagram of the signal selection circuit of the present invention.
Description of reference numerals: 1-wafer bulk, 2-reference cell op-amp, 3-non-reference cell op-amp, 4-scribe lane, 5-scribe lane wire and 6-op-amp cell block.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
As shown in fig. 1 and 2: in order to realize the packaging and manufacturing of the high-precision operational amplifier with the required channel and reduce the packaging and manufacturing cost, the invention comprises a wafer body 1 and a plurality of operational amplifier unit blocks 6 prepared on the wafer body 1, wherein each operational amplifier unit block 6 comprises two operational amplifier unit bodies and a scribing channel 4 for spacing the operational amplifier unit bodies, and the operational amplifier unit bodies are positioned at two sides of the scribing channel 4; each operational amplifier unit body comprises an operational amplification circuit and an oscillator circuit matched with the operational amplification circuit;
an inter-cell oscillator signal processing circuit is further provided in each operational amplifier unit block 6, and in the operational amplifier unit block 6, one operational amplifier cell is set as a reference cell operational amplifier and the other operational amplifier cell is set as a non-reference cell operational amplifier; in the reference unit operational amplifier, a reference oscillator circuit is in adaptive connection with a reference operational amplifying circuit and an inter-unit oscillator signal processing circuit; in the non-reference unit operational amplifier, a non-reference operational amplification circuit is in adaptive connection with a non-reference oscillator circuit through an inter-unit oscillator signal processing circuit;
when the operational amplifier unit block 6 is integrally packaged to obtain a required high-precision operational amplifier, a reference oscillator circuit is selected as an oscillator unit of the high-precision operational amplifier through an inter-unit oscillator signal processing circuit, so that the high-precision operational amplifier performs required operational amplification according to an oscillator signal of the selected oscillator unit;
when the operational amplifier unit bodies in the operational amplifier unit block 6 are cut and packaged by using the scribe lane 4, a reference-unit high-precision operational amplifier and a non-reference-unit high-precision operational amplifier can be obtained at the same time, the reference-unit high-precision operational amplifier performs required operational amplification according to an oscillator signal of a reference oscillator circuit, and the non-reference-unit high-precision operational amplifier performs required operational amplification according to an oscillator signal of a non-reference oscillator circuit.
Specifically, the wafer body 1 may be made of a conventional semiconductor material, and the operational amplifier unit blocks 6 may be fabricated on the wafer body 1 by a conventional integrated circuit technology, generally, a large number of operational amplifier unit blocks 6 may be fabricated on one wafer body 1, each operational amplifier unit block 6 may have the same structural form, and the process of fabricating the operational amplifier unit blocks 6 by using the wafer body 1 is well known to those skilled in the art, and will not be described herein again. In specific implementation, each operational amplifier unit block 6 has two operational amplifier unit bodies and scribe lanes 4 therein, and the scribe lanes 4 of the operational amplifier unit blocks 6 in the same column correspond to each other, that is, all the scribe lanes 4 of the operational amplifier unit blocks 6 in the same column are aligned on the same straight line. Each operational amplifier unit in the operational amplifier unit block 6 has a function of a complete operational amplifier, and of course, the operational amplifier unit block 6 also has a function of a complete operational amplifier, the specific circuit form of the operational amplifier unit block may be selected as required, and the specific position relationship and function between the scribe line 4 and the operational amplifier unit block are consistent with those in the prior art, which are well known to those skilled in the art and will not be described herein again.
As can be known from the description of the background art, for a high-precision operational amplifier, each operational amplifier unit includes an operational amplifier circuit and an oscillator circuit, wherein the operational amplifier circuit can implement an operational amplification function, the oscillator circuit can provide a clock signal required by the operational amplifier circuit, and a matching relationship between the operational amplifier circuit and the oscillator circuit is consistent with that in the existing high-precision operational amplifier, which is well known to those skilled in the art and is not described herein again.
In the embodiment of the present invention, an inter-cell oscillator signal processing circuit is further provided in each operational amplifier cell block 6. For convenience of explanation, when any one of the two operational amplifier units in the operational amplifier unit block 6 is set as the reference operational amplifier 2, the other operational amplifier unit in the operational amplifier unit block 6 automatically becomes the non-reference operational amplifier 3. In a specific implementation, after the reference cell operational amplifier 2 is set, the operational amplifier circuit in the reference cell operational amplifier 2 is a reference operational amplifier circuit, and the oscillator circuit in the reference cell operational amplifier 2 is a reference oscillator circuit. Similarly, after the non-reference cell operational amplifier 3 is obtained, the operational amplifier circuit in the non-reference cell operational amplifier 3 becomes a non-reference operational amplifier circuit, and the oscillator circuit in the non-reference cell operational amplifier 3 becomes a non-reference oscillator circuit. As is clear from the description of the related art, the frequency of the clock signal generated by the reference oscillator circuit is deviated from the frequency of the clock signal generated by the non-reference oscillator circuit.
In the reference unit operational amplifier 2, a reference oscillator circuit is connected to a reference operational amplifier circuit, and the reference oscillator circuit is also connected to an inter-unit oscillator signal processing circuit. In the non-reference operational amplifier 3, a non-reference oscillator circuit is connected to an inter-unit oscillator signal processing circuit, the inter-unit oscillator signal processing circuit is connected to a non-reference operational amplifier circuit in the non-reference operational amplifier 3, that is, in the reference cell operational amplifier 2, the oscillator signal of the reference operational amplifier circuit is directly supplied from the reference oscillator circuit, in the non-reference operational amplifier 3, the oscillator signal of the non-reference operational amplifier circuit is provided after being processed by the inter-cell oscillator signal processing circuit, and generally, the oscillator signal provided by the inter-cell oscillator signal processing circuit to the non-reference operational amplifier circuit is an oscillator signal of a reference oscillator circuit or an oscillator signal of a non-reference oscillator circuit, and is selected according to actual conditions, which will be described in more detail below.
It is well known in the art that when a packaged high-precision operational amplifier is manufactured by using the wafer 1, the corresponding high-precision operational amplifier can be obtained by integrally packaging the operational amplifier unit block 6, or by separately packaging the reference unit operational amplifier 2 and the non-reference unit operational amplifier 3, and the high-precision operational amplifiers of different types of channels can be obtained by different types of specific packages. Generally, the operational amplifier unit is a single-channel high-precision operational amplifier or a multi-channel high-precision operational amplifier, that is, after the operational amplifier unit is packaged separately, a single-channel high-precision operational amplifier or a multi-channel high-precision operational amplifier can be obtained, and the number of channels of the multi-channel high-precision operational amplifier is greater than or equal to two. Specifically, when the operational amplifier unit body is packaged to obtain a single-channel high-precision operational amplifier, the operational amplifier unit block 6 is integrally packaged to obtain a double-channel high-precision operational amplifier; when the operational amplifier unit body is packaged to obtain the dual-channel high-precision operational amplifier, the operational amplifier unit block 6 is integrally packaged to obtain the four-channel high-precision operational amplifier, and the rest conditions are analogized in turn, and detailed description is omitted here. The channel form of the high-precision operational amplifier obtained after the reference unit operational amplifier 2 and the non-reference unit operational amplifier 3 are specifically and independently packaged can be selected according to needs, and is generally designed and determined in advance in the design and manufacturing process of the wafer 1, and the specific design and determination process is consistent with the prior art, is specifically known by those skilled in the art, and is not described herein again.
In the embodiment of the invention, when the operational amplifier unit block 6 is integrally packaged to obtain the required high-precision operational amplifier, the reference oscillator circuit is selected as the oscillator unit of the high-precision operational amplifier through the inter-unit oscillator signal processing circuit, so that the high-precision operational amplifier performs required operational amplification according to the oscillator signal of the selected oscillator unit, namely, the high-precision operational amplifier integrally packaged in the operational amplifier unit block 6 only receives the oscillator signal of the reference oscillator circuit, thereby avoiding the interference easily caused by the inter-modulation of the oscillator signals when the reference oscillator circuit and the non-reference oscillator circuit exist in the integrated circuit at the same time, and ensuring the reliability of the operation of the packaged high-precision operational amplifier.
Further, when the operational amplifier unit bodies in the operational amplifier unit block 6 are cut and packaged separately by the dicing lane 4, the reference-unit high-precision operational amplifier and the non-reference-unit high-precision operational amplifier can be obtained at the same time, and the reference-unit high-precision operational amplifier performs a desired operational amplification based on the oscillator signal of the reference oscillator circuit, and the non-reference-unit high-precision operational amplifier performs a desired operational amplification based on the oscillator signal of the non-reference oscillator circuit.
In the embodiment of the present invention, the reference cell operational amplifier 2 and the non-reference cell operational amplifier 3 may be packaged separately, and at this time, the dicing street 4 needs to be cut and packaged, and at this time, the reference cell operational amplifier 2 may be used to obtain the reference cell high-precision operational amplifier, and the non-reference cell operational amplifier 3 may be used to obtain the non-reference cell high-precision operational amplifier. After the operational amplifier unit block 6 is cut and packaged by the scribing channel 4, the reference unit high-precision operational amplifier can perform operational amplification according to an oscillator signal of the reference oscillator circuit, and the non-reference unit high-precision operational amplifier performs operational amplification according to an oscillator signal of the non-reference oscillator circuit, namely, when the operational amplifier unit block 6 is cut and packaged by the scribing channel 4, normal use and operation of the obtained reference unit high-precision operational amplifier and the non-reference unit high-precision operational amplifier are not influenced.
In specific implementation, the process of integrally packaging the operational amplifier unit block 6 on the wafer 1, or cutting and packaging the operational amplifier unit block 6 by using the scribe line 4 is consistent with the existing process, which is well known to those skilled in the art and will not be described herein again. As can be seen from the above description, in the prior art, when packaging, the oscillator unit needs to be set correspondingly by wire bonding or the like for the multi-channel high-precision operational amplifier, but in the embodiment of the present invention, the operational amplifier unit block 6 is packaged integrally, or the operational amplifier unit block 6 is packaged after being cut by the scribe line 4, and the package can be directly manufactured without wire bonding, so that the package of the high-precision operational amplifiers of different channels can be realized without increasing the package cost, and a chip manufacturer can package the high-precision operational amplifiers of different channels as required.
As can be seen from the above description, the structures of the operational amplifier unit block 6, the scribe lane 4, and the like are prepared by using a common integrated circuit process, and when high-precision operational amplifiers with different channels are obtained by packaging, only the inter-unit oscillator signal processing circuit needs to be added, and the inter-unit oscillator signal processing circuit is connected with the reference unit operational amplifier 2 and the non-reference unit operational amplifier 3 in an adaptive manner, so that the method is compatible with the existing process, and the cost for realizing the packaging of the high-precision operational amplifiers with multiple channels is effectively reduced.
Furthermore, the inter-unit oscillator signal processing circuit comprises a selection signal generating circuit and a signal selecting circuit arranged on the non-reference unit operational amplifier, wherein the selection signal generating circuit, the reference oscillator circuit and the non-reference oscillator circuit can be connected with the non-reference operational amplifier circuit through the signal selecting circuit;
the selection signal generating circuit comprises a reference unit circuit arranged in the reference unit operational amplifier, a scribing way lead 5 arranged in the scribing way 4 and a non-reference unit circuit arranged in the non-reference unit operational amplifier, wherein the reference unit circuit is connected with the non-reference unit circuit through the scribing way lead 5;
when the operational amplifier unit block 6 is integrally packaged to obtain the required high-precision operational amplifier, the reference unit circuit is kept connected with the non-reference unit circuit through the scribing guide wire 5, the selection signal generating circuit loads a reference oscillator circuit selection signal to the signal selection circuit, and the signal selection circuit enables the non-reference operational amplifier circuit to receive an oscillator signal of the reference oscillator circuit according to the reference oscillator circuit selection signal;
when the operational amplifier unit bodies in the operational amplifier unit blocks 6 are cut and respectively packaged by using the scribe lanes 4, the scribe lane lead 5 is in a disconnected state, and the connection between the reference unit part circuit and the non-reference unit part circuit and the electrical connection between the reference oscillator circuit and the signal selection circuit are disconnected by the scribe lane lead 5; the selection signal generating circuit loads a non-reference oscillator circuit selection signal to the signal selection circuit, and the signal selection circuit enables the non-reference operational amplification circuit to receive an oscillator signal of the non-reference oscillator circuit according to the non-reference oscillator selection signal.
In the embodiment of the present invention, the inter-cell oscillator signal processing circuit includes a selection signal generating circuit and a signal selecting circuit, wherein the selection signal generating circuit, the reference oscillator circuit, and the non-reference oscillator circuit are all connected to the signal selecting circuit, and the signal selecting circuit is connected to the non-reference operational amplifier circuit in the non-reference cell operational amplifier 3, that is, the signal selecting circuit can select the oscillator signal of the reference oscillator circuit or the oscillator signal of the non-reference oscillator circuit according to the selection signal generating circuit.
Specifically, the reference cell portion circuit is located in the reference cell operational amplifier 2, the non-reference cell portion circuit is located in the non-reference cell operational amplifier 3, a scribe lane wire 5 is provided in the scribe lane 4, and the reference cell portion circuit is connected to the non-reference cell portion circuit through the scribe lane wire 5. In addition, a connection line group is further disposed on the scribe lane 4, the connection line group includes a connection line connecting the reference oscillator circuit and the signal selection circuit, and an AVDD connection line and an AGND connection line connecting the reference cell operational amplifier 2 and the non-reference cell operational amplifier 3, that is, the AVDD connection line of the reference cell operational amplifier 2 is electrically connected to the AVDD connection line of the non-reference cell operational amplifier 3 through a corresponding scribe lane wire 5, the AGND connection line of the reference cell operational amplifier 2 is electrically connected to the AGND connection line of the non-reference cell operational amplifier 3 through a corresponding scribe lane wire 5, the AVDD connection line, the AGND connection line, and the connection line connecting the reference oscillator circuit and the signal selection circuit are independent connection lines, as shown in fig. 2, the relationship and arrangement of the specific connection lines are consistent with those of the prior art, and are not. Generally, the scribe lanes 4 are 60 μm to 80 μm, and the scribe lane wires 5 and the corresponding bonding wire groups can be conveniently arranged by using the width of the scribe lanes 4.
When the operational amplifier unit block 6 is packaged as a whole, the operational amplifier unit block 6 does not need to be cut by using the scribe lane 4, at this time, the scribe lane wires 5 and the connection line groups in the scribe lane 4 all keep corresponding connection states, at this time, the selection signal generation circuit loads a reference oscillator circuit selection signal to the signal selection circuit, the signal selection circuit can select an oscillator signal of the reference oscillator circuit according to the reference oscillator circuit selection signal, and the signal selection circuit can enable the non-reference operational amplification circuit to receive the oscillator signal of the reference oscillator circuit.
When the operational amplifier unit bodies in the operational amplifier unit blocks 6 are cut and respectively packaged by using the scribe lanes 4, the scribe lane lead 5 is in a disconnected state, and the connection between the reference unit part circuit and the non-reference unit part circuit and the electrical connection between the reference oscillator circuit and the signal selection circuit are disconnected by the scribe lane lead 5; the selection signal generating circuit loads a non-reference oscillator circuit selection signal to the signal selection circuit, the signal selection circuit selects an oscillator signal of the non-reference oscillator circuit according to the non-reference oscillator selection signal, and the signal selection circuit enables the non-reference operational amplification circuit to receive the oscillator signal of the non-reference oscillator circuit.
As shown in fig. 3, the signal selection generating circuit includes an inverter U1 and an inverter U2, an output terminal of the inverter U1 is connected to an input terminal of the inverter U2, and an output terminal of the inverter U1 and an output terminal of the inverter U2 are both connected to the signal selection circuit;
the input end of the inverter U1 is connected with one end of a capacitor C1, one end of a scribe lane lead 5 and the drain end of a PMOS tube P2, the other end of the capacitor C1 is grounded, the other end of the scribe lane lead 5 is grounded through a resistor R1, the gate end of the PMOS tube P2 is connected with the gate end of the PMOS tube P1 and the drain end of the PMOS tube P1, the drain end of the PMOS tube P1 is grounded through a current source I1, and the source end of the PMOS tube P1 and the source end of the PMOS tube P2 are both connected with a power supply VDD. The PMOS transistor P1 and the PMOS transistor P2 have the same gate voltage, and the mirror currents of the PMOS transistor P1 and the PMOS transistor P2 are 1: 1.
in the embodiment of the present invention, the PMOS transistor P1, the PMOS transistor P2, the capacitor C1, the inverter U1, and the inverter U2 may constitute a reference cell circuit or a non-reference cell circuit, and when the PMOS transistor P1, the PMOS transistor P2, the capacitor C1, the inverter U1, and the inverter U2 may constitute a reference cell circuit, the resistor R1 may constitute a non-reference cell circuit, and when the resistor R1 constitutes a reference cell circuit, the PMOS transistor P1, the PMOS transistor P2, the capacitor C1, the inverter U1, and the inverter U2 may constitute a non-reference cell circuit. The output terminal of the inverter U1 outputs a reference oscillator circuit selection signal EN _ B, and the output terminal of the inverter U2 outputs a non-reference oscillator circuit selection signal EN. In fig. 2, CTRL1 is a connection point of the scribe line 5 and the reference cell portion circuit, and CTRL2 is a connection point of the scribe line 5 and the non-reference cell portion circuit.
When the scribe lane 4 is cut, the scribe lane wire 5 is disconnected, and at this time, an infinite impedance is formed at the drain terminal of the PMOS transistor P2 and the input terminal of the inverter U1, and the input voltage of the inverter U1 is close to the voltage of the power supply VDD, so that the reference oscillator circuit selection signal EN _ B output by the inverter U1 is low, and the non-reference oscillator circuit selection signal EN output by the output terminal of the inverter U2 is high.
As shown in fig. 4, the signal selection circuit includes an and gate U3, an and gate U4, and an or gate U5, an input terminal of the and gate U3 is connected to an output terminal of the inverter U1 and an output terminal of the reference oscillator circuit, an input terminal of the and gate U4 is connected to an output terminal of the inverter U2 and an output terminal of the non-reference oscillator circuit, an output terminal of the and gate U3 and an output terminal of the and gate U4 are connected to an input terminal of the or gate U5, and an output terminal of the or gate U5 is connected to the non-reference operational amplifier circuit.
In the embodiment of the present invention, the and gate U3 receives the reference oscillator circuit selection signal EN _ B and the oscillator signal OSC1 of the reference oscillator circuit, the and gate U4 receives the non-reference oscillator circuit selection signal EN and the oscillator signal OSC2 of the non-reference oscillator circuit, and the output terminal of the or gate U5 outputs the oscillator selected signal OSCT.
When the operational amplifier cell block 6 is not cut and the scribe lane conductive line 5 is kept connected, the reference oscillator circuit selection signal EN _ B output from the inverter U1 is made high by the current source I1, but the reference oscillator circuit selection signal EN is made low, and the oscillator post-selection signal OSCT is kept identical to the oscillator signal OSC1 of the reference oscillator circuit by the cooperation of the and gate U3 and the or gate U5. The current source I1 is a constant current source, and the working current of the current source I1 can be 1 muA.
When the operational amplifier unit block 6 is cut by using the scribe lane 4, the scribe lane wires 5 and the connection wire group in the scribe lane 4 are both in an off state, at this time, the oscillator signal OSC1 of the reference oscillator circuit cannot be applied to the input terminal of the and gate U3, and at the same time, the non-reference circuit selection signal EN of the inverter U2 is at a high level, and the oscillator selected signal OSCT is consistent with the oscillator signal OSC2 of the non-reference oscillator circuit by the cooperation of the and gate U4 and the or gate U5.
In summary, by the signal selection generating circuit and the signal selection circuit being cooperated, the non-reference operational amplifier 3 can be enabled to receive the oscillator signal OSC1 of the reference oscillator circuit or the oscillator signal OSC2 of the non-reference oscillator circuit respectively according to the cutting state of the operational amplifier unit block 6 by the scribe lane 4, thereby ensuring the stability and reliability of the operation of the high precision operational amplifier under different packaging conditions. In the specific implementation, in the integrated design stage of the wafer 1, the required signal selection generating circuit and signal selection circuit can be designed synchronously, and in the process of preparing the operational amplifier unit block 6, the signal selection generating circuit and the signal selection circuit can be obtained simultaneously, so that the complexity of the operational amplifier unit block 6 is not increased. In addition, the areas of the signal selection generating circuit and the signal selection circuit are generally much smaller than the area of the operational amplifier unit block 6, and the integration degree of the wafer 1 in integrating the operational amplifier unit block 6 is not affected.
Claims (6)
1. An integrated circuit capable of simultaneously preparing multiple channels of high-precision operational amplifiers comprises a wafer body (1) and a plurality of operational amplifier unit blocks (6) prepared on the wafer body (1), wherein each operational amplifier unit block (6) comprises two operational amplifier unit bodies and a scribing channel (4) used for spacing the operational amplifier unit bodies, and the operational amplifier unit bodies are positioned on two sides of the scribing channel (4); each operational amplifier unit body comprises an operational amplification circuit and an oscillator circuit matched with the operational amplification circuit; the method is characterized in that:
an inter-cell oscillator signal processing circuit is further provided in each operational amplifier unit block (6), and in the operational amplifier unit block (6), one operational amplifier cell is set as a reference cell operational amplifier (2), and the other operational amplifier cell is set as a non-reference cell operational amplifier (3); in the reference unit operational amplifier (2), a reference oscillator circuit is in adaptive connection with a reference operational amplification circuit and an inter-unit oscillator signal processing circuit; in the non-reference unit operational amplifier (3), a non-reference operational amplification circuit is in adaptive connection with a non-reference oscillator circuit through an inter-unit oscillator signal processing circuit;
when the operational amplifier unit block (6) is integrally packaged to obtain a required high-precision operational amplifier, a reference oscillator circuit is selected as an oscillator unit of the high-precision operational amplifier through an inter-unit oscillator signal processing circuit, so that the high-precision operational amplifier performs required operational amplification according to an oscillator signal of the selected oscillator unit;
when the operational amplifier unit bodies in the operational amplifier unit block (6) are cut and respectively packaged by using the scribing channel (4), a reference unit high-precision operational amplifier and a non-reference unit high-precision operational amplifier can be simultaneously obtained, the reference unit high-precision operational amplifier carries out required operational amplification according to an oscillator signal of a reference oscillator circuit, and the non-reference unit high-precision operational amplifier carries out required operational amplification according to an oscillator signal of a non-reference oscillator circuit.
2. The integrated circuit capable of simultaneously fabricating multiple channel high precision operational amplifiers of claim 1, wherein: the inter-unit oscillator signal processing circuit comprises a selection signal generating circuit and a signal selecting circuit arranged on the non-reference unit operational amplifier, wherein the selection signal generating circuit, the reference oscillator circuit and the non-reference oscillator circuit can be connected with the non-reference operational amplifier circuit through the signal selecting circuit;
the selection signal generating circuit comprises a reference unit circuit arranged in a reference unit operational amplifier (2), a scribing way lead (5) arranged in a scribing way (4) and a non-reference unit circuit arranged in a non-reference unit operational amplifier (3), wherein the reference unit circuit is connected with the non-reference unit circuit through the scribing way lead (5);
when the operational amplifier unit block (6) is integrally packaged to obtain the required high-precision operational amplifier, the reference unit circuit is kept connected with the non-reference unit circuit through a scribing guide wire (5), a selection signal generating circuit loads a reference oscillator circuit selection signal to a signal selection circuit, and the signal selection circuit enables the non-reference operational amplifier circuit to receive an oscillator signal of the reference oscillator circuit according to the reference oscillator circuit selection signal;
when the operational amplifier unit bodies in the operational amplifier unit blocks (6) are cut and respectively packaged by using the scribing streets (4), the scribing street conducting wires (5) are in a disconnected state, and the connection between the reference unit part circuit and the non-reference unit part circuit and the electrical connection between the reference oscillator circuit and the signal selection circuit are disconnected through the scribing street conducting wires (5); the selection signal generating circuit loads a non-reference oscillator circuit selection signal to the signal selection circuit, and the signal selection circuit enables the non-reference operational amplification circuit to receive an oscillator signal of the non-reference oscillator circuit according to the non-reference oscillator selection signal.
3. The integrated circuit capable of simultaneously manufacturing multiple channel high precision operational amplifiers of claim 2, wherein: the signal selection generating circuit comprises an inverter U1 and an inverter U2, wherein the output end of the inverter U1 is connected with the input end of the inverter U2, and the output end of the inverter U1 and the output end of the inverter U2 are both connected with the signal selection circuit;
the input end of the inverter U1 is connected with one end of a capacitor C1, one end of a scribe lane lead wire (5) and the drain end of a PMOS tube P2, the other end of the capacitor C1 is grounded, the other end of the scribe lane lead wire (5) is grounded through a resistor R1, the gate end of the PMOS tube P2 is connected with the gate end of the PMOS tube P1 and the drain end of the PMOS tube P1, the drain end of the PMOS tube P1 is grounded through a current source I1, and the source end of the PMOS tube P1 and the source end of the PMOS tube P2 are both connected with a power supply VDD.
4. The integrated circuit capable of simultaneously manufacturing multiple channel high precision operational amplifiers of claim 3, wherein: the signal selection circuit comprises an AND gate U3, an AND gate U4 and an OR gate U5, wherein the input end of the AND gate U3 is connected with the output end of the inverter U1 and the output end of the reference oscillator circuit, the input end of the AND gate U4 is connected with the output end of the inverter U2 and the output end of the non-reference oscillator circuit, the output end of the AND gate U3 and the output end of the AND gate U4 are connected with the input end of the OR gate U5, and the output end of the OR gate U5 is connected with the non-reference operational amplification circuit.
5. The integrated circuit capable of simultaneously manufacturing multiple-channel high-precision operational amplifiers as claimed in claim 1, 2, 3 or 4, wherein: the operational amplifier unit body is a single-channel high-precision operational amplifier or a multi-channel high-precision operational amplifier.
6. The integrated circuit capable of simultaneously manufacturing multiple-channel high-precision operational amplifiers as claimed in claim 1, 2, 3 or 4, wherein: the width of the scribing way (4) is 60-80 μm.
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