JP2672695B2 - Bonding equipment for integrated circuits - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an integrated circuit bonding apparatus, and more particularly to an apparatus for performing bonding according to the quality of an integrated circuit chip formed on a semiconductor wafer.

[Prior Art] In an integrated circuit, a large number of integrated circuit chips formed on one semiconductor wafer are individually divided, and then the integrated circuit chips are mounted on a package, and a lead for external connection and an integrated circuit chip pad are placed between them. It is assembled by connecting and sealing the integrated circuit chip.

Generally, this assembly is accomplished by the following steps.

(A) Dicing for individually dividing an integrated circuit chip formed on a single semiconductor wafer.

(A) Die bonding for mounting the divided individual integrated circuit chips in a package.

(C) Wire bonding for connecting pads on the integrated circuit chip and external leads on the package using Au wires or Al wires.

(D) Sealing that protects the integrated circuit chip from contamination and damage from the outer atmosphere.

Then, a wafer probing test is usually performed in which a probe is mechanically brought into contact with a bonding pad of each integrated circuit chip in a semiconductor wafer state before the dicing step to measure electrical characteristics. Then, the quality of each integrated circuit chip is ranked by this wafer probing test, and only the integrated circuit chips which have reached a predetermined rank are judged as non-defective products, and the assembly process is completed to complete the assembly.

[Problems to be Solved by the Invention] As described above, in the related art, the electrical characteristics of the integrated circuit chip produced before the assembly process is tested,
There is a problem that it is extremely difficult to improve the final yield because only the integrated circuit chips that have obtained a certain level of quality in this test are die-bonded and further wire-bonded.

That is, an integrated circuit chip formed on a semiconductor wafer is manufactured by sequentially undergoing an exposure step, an etching step, an electrode wiring step, and an insulating step, but each step is controlled to the utmost limit, A high degree of breakthrough is required to improve the yield in each process.

The present invention has been made in view of the above conventional problems, and an object thereof is to provide an integrated circuit chip that has not been assembled as a conventional defective product by performing bonding according to a quality test result performed before the assembly process. Another object of the present invention is to provide a bonding apparatus for an integrated circuit, which can improve the yield by performing bonding so that a constant quality level can be obtained.

[Means for Solving the Problems] In order to achieve the above object, a bonding apparatus for an integrated circuit according to the present invention is a bar code reader for reading an identification number recorded on a semiconductor wafer to be bonded, and this bar code reader. Based on the identification number read in, the information about the quality of the integrated circuit chip formed on the semiconductor wafer is retrieved from the memory in which the information about the quality of the integrated circuit chip of the corresponding semiconductor wafer is retrieved and mounted on the package. Characterized by having a die bonding controller that evaluates the quality of each integrated circuit chip and a wire bonding controller that connects the integrated circuit chips mounted in the package according to the quality evaluated by the die bonding controller. There is.

[Operation] The bonding apparatus for an integrated circuit of the present invention has such a configuration, and the bar code reader reads the identification number of the semiconductor wafer to be bonded from them.
Then, the read identification number is sent to the die bonding controller that mounts the integrated circuit chip on the package.

The die bonding controller identifies the integrated circuit chip to be die-bonded based on the identification number sent from the bar code reader, and the corresponding information is stored in the memory in which the information about the quality of the integrated circuit chip obtained in advance by the wafer probing test is stored. Search for the information you want.
Then, quality evaluation corresponding to each integrated circuit chip that has been die-bonded is performed, and the information is sent to the wire bonding controller.

In the wire bonding controller, the pads on the integrated circuit chip and the external leads on the package are connected according to the quality evaluation result of each integrated circuit chip mounted on the package sent from the die bonding controller,
Wiring is performed so that a desired quality can be obtained even for an integrated circuit chip for which a certain quality cannot be obtained in the wafer probing test.

As described above, by appropriately changing the wire bonding method according to the quality evaluation result, it is possible to improve the yield by also bonding an integrated circuit chip that has not been bonded as a defective product in the past. .

[Embodiment] A preferred embodiment of the bonding apparatus for an integrated circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of this embodiment. The semiconductor wafer 10 is fixed to the metal ring 14 by the adhesive film 12, and after the wafer probing test is performed, it is carried into the integrated circuit bonding apparatus of this embodiment.

A bar code in which the identification number of this semiconductor wafer is recorded on the metal ring 14 to which the semiconductor wafer 10 is fixed.
16 is attached, and this bar code 16 is read by the bar code reader 18 of the apparatus of this embodiment.

The wafer probing test result of each integrated circuit chip on the semiconductor wafer 10 is stored in the memory 20 such as a floppy disk together with the identification number of the semiconductor wafer 10. As the wafer probing test result, for example, the quality of each integrated circuit chip may be divided into three stages of rank A, rank B, and rank C and stored together with the address of each integrated circuit chip.

Semiconductor wafer read by barcode reader 18
The identification number of 10 is sent to a die bonding controller 22 that performs die bonding to attach the integrated circuit chip on the semiconductor wafer 10 to the position of the die pad of the ceramic package or the lead frame.

The die bonding controller 22 accesses the memory 20 based on the identification number of the semiconductor wafer 10 sent from the bar code reader 18 and retrieves information regarding the quality of the integrated circuit chip having the corresponding identification number.

As described above, the memory 20 stores the results of the wafer probing test performed before the assembly process, and ranks A to C are assigned to the individual integrated circuit chips formed on each semiconductor wafer. .
When the die bonding controller 22 mounts the individual integrated circuit chips formed on the semiconductor wafer 10 in a package and performs die bonding, the quality of rank A to rank C is determined based on the quality information retrieved from the memory 20. Make an evaluation.

Then, the die bonding controller 22 carries the integrated circuit chip mounted on the package or the wire bonding controller 24, and connects the pad on the integrated circuit chip and the external lead on the package by using an Au wire or an Al wire.

At this time, a characteristic feature of this embodiment is that wire bonding is performed according to the quality evaluation of each integrated circuit chip die-bonded by the die-bonding controller 22. That is, as a result of the quality evaluation, the wire bonding of the die-bonded integrated circuit chip evaluated as rank A and the wire bonding of the die-bonded integrated circuit chip evaluated as rank C are different from each other.

The wire bonding process in this embodiment will be described below with reference to the circuit diagram of FIG.

FIG. 2 shows a simple integrated circuit including an amplifier 30, a filter circuit 32, and an integrating circuit 34.
IN, output pad OUT, power supply pad Vcc, ground pad
Each pad of GND and a switching pad for gradually changing the filter frequency characteristic of the filter circuit 32 are provided.

Now, the integrated circuit chip having such a circuit configuration is quality-inspected by a wafer probing test before the assembly process, and when the die bonding is performed by the die bonding controller 22, the variation of the filter frequency is large or small, for example, the standard center frequency is 38 kHz. Variation is 2
If the frequency is less than kHz, it is ranked as rank A, and the others are ranked as ranks B and C. However, if the quality is evaluated as rank A, the wire bonding controller 24 selects a pad to perform wire bonding. A control signal is sent to the selection wire bonder 26 to select a pad from among the pads (1) to (3) of the filter circuit 32, and the pad is connected to the external lead of the package.

On the other hand, when the integrated circuit chip die-bonded by the die-bonding controller 22 is evaluated as rank B, the wire-bonding controller 24 sends a control signal to the pad selection wire bonder 26, and the filter circuit
By selecting a pad from among the 32 pads and connecting it to an external lead, it is changed to be within a predetermined frequency variation.

Furthermore, the die bonding controller 22 ranks C
In the case of an integrated circuit chip that has been evaluated as "quality", by selecting a pad from among the pads of the filter circuit 32, wiring is performed so that the filter frequency has a frequency variation of rank A or so.

As described above, according to the integrated circuit bonding apparatus of the present embodiment, the quality of the integrated circuit chip, which has hitherto been determined as a defective product that does not reach a certain quality level, is improved by performing wire bonding according to the quality evaluation. Maintain
Assembling is performed, and it becomes possible to produce an integrated circuit chip from one semiconductor wafer without waste.

[Advantages of the Invention] As described above, according to the integrated circuit bonding apparatus of the present invention, the yield is remarkably increased by performing the bonding depending on the quality of the individual integrated circuit chips formed on the semiconductor wafer. It is possible to improve.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an embodiment of an integrated circuit bonding apparatus according to the present invention, and FIG. 2 is a circuit diagram of an integrated circuit in the same embodiment. 10 …… Semiconductor wafer 16 …… Bar code 18 …… Bar code reader 20 …… Memory 22 …… Die bonding controller 24 …… Wire bonding controller 26 …… Pad select wire bonder

Claims (1)

(57) [Claims] 1. A bar code reader for reading an identification number recorded on a semiconductor wafer to be bonded in a bonding apparatus for an integrated circuit in which a plurality of integrated circuit chips formed on a semiconductor wafer are individually mounted in a package and connected. And information on the quality of the integrated circuit chip of the semiconductor wafer corresponding to the quality of the integrated circuit chip formed on the semiconductor wafer based on the identification number read by the bar code reader. A die bonding controller that searches and evaluates the quality of each integrated circuit chip mounted in the package, and a wire bonding controller that connects the integrated circuit chips mounted in the package according to the quality evaluated by this die bonding controller. ,, according to quality, A bonding apparatus for an integrated circuit, which bonds a product circuit chip.