JPH077057A - The kgd array (known good die array) and its manufacture - Google Patents

Abstract

PURPOSE: To provide a KGD array, conducting an AC test and a burn-in test through the use of a common IC chip separated from a wafer, without forming a wax bump, and to provide its manufacture method. CONSTITUTION: A lead frame 30 provided with plural die pads 32 which are supported by tie-bars 38 and are regularly arranged, an adhesive 35 applied on the die pads 32 on the lead frame 30 and plural KGDs without defects, which are adhered by individual die on the respective die pads 32, on which adhesive is applied and whose final test is terminated, are provided.

Description

Detailed Description of the Invention

[0001]

This invention relates to a KGD array (Know).
n Good Die Array) and its manufacturing method, more specifically, a plurality of integrated circuit chips separated from a wafer are collectively AC-processed using a normal semiconductor assembly process.
(Alternating Current) test or burn-in (Burn
-In) The present invention relates to a KGD array capable of performing mass production of defect-free KGD arrays and a manufacturing method thereof.

[0002]

2. Description of the Related Art Generally, it is essential that an integrated circuit chip (hereinafter referred to as an IC chip) be subjected to an AC test or a burn-in test in order to detect a defective IC chip in advance from the manufacturing process of a semiconductor device.

By the way, in an ordinary IC chip state separated from a wafer, an AC test or a burn-in test is almost impossible because a test pattern generating circuit and an electric signal line cannot be connected.

Therefore, in the normal AC test and burn-in test, as shown in FIG.
It is carried out with the package molded in.

Referring to FIG. 5, an external lead 12 connected to a chip pad (not shown) is protruded from a sidewall of the package 10.

The test socket 15 in which the package 10 can be mounted is formed by a plurality of socket holes 14 corresponding to the external leads 12 and the lower end portion of the socket holes 14 protruding outward. Each of them has a hard lead 16 formed therein.

After the package 10 with the external leads 12 protruding is mounted in the socket hole 14 of the test socket 15, the test socket 15 is mounted on a separate burn-in board (not shown).

Therefore, the AC test and the burn-in test are performed with the package 10 mounted in the test socket 15 as described above.

In the AC test and the burn-in test, a test signal is input to the IC chip at a high temperature and a high voltage higher than the normal operating condition. Then, it is checked whether or not a defect is generated in which IC chip with the test signal applied.

For example, in the case of a DRAM, a defective memory circuit, a defective memory cell, a defective connection, etc. are usually checked.

As a result, such defects (breakdown of the insulating film of the gate oxide film, etc.) are inevitably generated in the burn-in test of the IC chip, which may cause a failure when used in a normal state. By the way, an IC chip in which a defect is detected during the burn-in test is processed as a defective product. By thus removing the defective IC chip before shipment, the reliability of the product is guaranteed.

However, in the burn-in test using the test socket as described above, since the burn-in test is performed with the semiconductor chip packaged, the IC chip once treated as a defective product cannot be reused. It has the drawback of being impossible.

By the way, in recent years, a multi-chip technique using a flip chip for thermally mounting a plurality of bare chips on a ceramic board without using a single chip package has been developed.

The multi-chip technology has been proposed by various integration methods that enable large scale integration while achieving high speed, high capacity and small size. One of these, a typical method is a multi-chip module integration method.

The multi-chip module obtains an ultra-large scale of integration, and for multi-layered ceramics or plastic boards that are densely wired below,
A plurality of IC chips are interconnected and internally mounted. Currently, multi-chip modules have been successfully applied to supercomputers and the like by companies such as IBM, DEC, Hitachi and others.

However, the multi-chip module is
It is technically and economically restricted for the following reasons. That is, as compared with the conventional single-chip package technology, the integration scale of the multi-chip module in which a large number of IC chips are installed is large, but the production yield is significantly reduced, and the production cost is greatly increased. There is a point.

By the way, as with all packaging technologies, multi-chip modules face difficulties in securing a sufficient market for the reasons mentioned above. The most difficult issue with multi-chip modules is that of KGD (an IC chip that has not been packaged but has been tested and proven to be as reliable as conventional packaging technology), which is directly related to production yield. There is sufficient security.

The present invention relates to ensuring sufficient KGD. Hereinafter, a defect-free bare chip after all tests are defined as KGD. Here, a bare chip means a flip chip, a wire chip, or the like.
An unpackaged ordinary IC chip separated from a wafer as a single chip.

A more detailed concept for the KGD is:
Microelectronic and Computer technology Corporat
ion) Potential Project Report (Potential
Project Report) is often represented in the 1992 edition.

Although the importance of KGD applied to the multi-chip module is increasing, mass production of low-priced KGD is currently quite difficult.

That is, since a single bare chip separated from a wafer has no external lead, it is impossible to use a test socket applicable to a chip test. Therefore, the AC test and the burn-in test cannot be performed before the IC chip is mounted on the circuit board in a bare chip state.

As a technique for solving such a problem, a flip chip test socket adapter (Fili) for enabling AC and burn-in tests in a bare chip state in which a solder bump is formed for each electrode pad of the chip is used.
p chip test socket adapter) has been proposed. Such a technique is disclosed in, for example, US Pat. No. 5,0067,792, and such an example is shown in FIGS. 6 and 7.

FIG. 6 is a perspective view of a flip chip having a solder bump according to the above technique, and FIG. 7 is a sectional view of the flip chip shown in FIG. 6 mounted on a test socket adapter.

As shown in FIG. 6, the IC chip 22 has a plurality of solder bumps 24 formed on its bonding pad, and is inserted into a dedicated test socket adapter as shown in FIG. 7 to be tested.

As shown in FIG. 7, the test socket adapter 20 has a solder bump 24 of the IC chip 22 inserted therein.
Cantilever beams 2 connected to
6 is formed, and the substrate 28 is housed in the case 20. Here, reference numeral 23 is a lead connected to the cantilever beam 26, reference numeral 27 is a lead protruding to the outside of the case 20, and reference numeral 2
Reference numeral 5 is a guide bar for supporting the IC chip 22 so as to stabilize it when it is inserted.

Therefore, the IC chip test method using the test socket adapter having the above structure enables the test under the condition of the bare chip before the package.

However, this prior art uses a single IC chip 22 separated from the wafer.
A solder bump 24, which is a metal protrusion, must be formed on each electrode pad of the C chip 22, and a chip test and burn-in must be performed in a bare chip state.
However, in the process of forming a bump on the electrode pad of a single IC chip, there is a disadvantage that high precision is required and expensive equipment is required due to a fine pitch between the electrode pads due to high integration. .

Further, since one IC chip is handled at the time of testing, there is a problem that chip handling becomes difficult.

The problems in manufacturing the KGD according to the prior art can be summarized as follows.

Since an ordinary IC chip itself cannot undergo an AC test, a burn-in test, etc., it is necessary to form a solder bump or the like and use a dedicated test socket, which makes mass production difficult. Because it is handled, it is very difficult to handle at the chip level, the KGD is very expensive compared to the packaged IC chip, it is difficult to make a test jig, and there is no standardized IC chip. Is.

[0031]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a KGD array capable of AC test and burn-in test using a normal IC chip separated from a wafer without forming a wax pump, and a KGD array thereof. It is to provide a manufacturing method.

Another object of the present invention is to provide a KGD array capable of collectively performing AC test and burn-in test on a plurality of IC chips and a manufacturing method thereof.

Another object of the present invention is to provide a KGD array capable of performing AC test and burn-in test with a device used in an existing IC assembly, and a method of manufacturing the same.

[0034]

To achieve the above object, in a KGD array according to the present invention, a lead frame having a plurality of regularly arranged die pads supported by tie bars, and Adhesive applied to each die pad of the lead frame, and a plurality of defect-free KGDs that have undergone the final test in which individual adhesives are adhered to each die pad to which this adhesive is applied.
And are provided.

The plurality of IC chips may have bumps formed on their respective electrode pads, and the adhesive may be made of a conductive material such as a wax, a thermosetting resin or a thermoplastic resin depending on the purpose of use. The plurality of IC chips may be used as an individual KGD in a state in which the die pad is attached to the bottom surface by cutting the tie bar, and the die pad is , Can be used as a heat sink.

In order to achieve the above object, the method of manufacturing a KGD array according to the present invention includes a plurality of leads and a plurality of die pads which are supported by tie bars and are regularly arranged. Manufacturing a lead frame, attaching an adhesive tape to fix the die pad on the leads of the lead frame, and having a plurality of electrode pads separated from the wafer on each die pad of the lead frame. Die-attaching the IC chip through an adhesive, wire-bonding each electrode pad of the IC chip to an end of each lead corresponding thereto, and wire-bonding with the lead frame. The trimming process to electrically separate the trimmed leads If, after the trimming process step, the steps for implementing the AC test and burn-in test by inserting the lead frame of the resulting structure Tesutojiku,
After the AC test and the burn-in test are completed,
It is characterized by including a step of checking a defective IC chip and a step of cutting an upper portion of each wire ball bonded by a cutting means.

As the adhesive tape, a polyimide-based adhesive having excellent adhesiveness can be used, and the height of the cutting means depends on the size of the cutting and the size of the cutting wire remaining at the step of cutting the bonding wire. It can be adjusted to control the size of the wire ball. In addition, the adhesive is a conductive substance such as wax according to the purpose of use,
It may include any one of a thermosetting resin or a thermoplastic resin. Further, the plurality of IC chips can be used as an individual KGD in a state where a tie bar is cut and a die pad is attached to the bottom surface.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a KGD array and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a plan view of a lead frame used in manufacturing the KGD array according to the present invention, wherein the lead frame is formed by a normal lead frame tethering method.

As shown in FIG. 1, the lead frame 30
Includes a large number of regularly arranged die pads 32 of the same size and a plurality of leads 34 arranged on both sides of each of the plurality of die pads 32.

Further, since the lead frame 30 is not for an ordinary IC chip package, it is characteristic that a dam bar is not formed. Here, reference numeral 36
Is an opening for preventing deformation of the lead 34 during the trimming process, and reference numeral 38 is a tie bar for supporting the die pad 32.

FIG. 3 is a perspective view of a KGD according to the present invention provided in an array on the lead frame 30 of FIG. In the KGD array according to the present invention, an AC test and a burn-in test are collectively performed in a state in which a plurality of KGDs are arranged on the lead frame 30 shown in FIG. 1 for wire-bonding the electrode pads of the IC chip 31 to the leads. Will be provided after being done.

Here, for convenience of description, the structure of the KGD array will be described later, and first, a method of manufacturing the KGD array will be described.

2A and 2B are manufacturing process diagrams for manufacturing the KGD array according to the present invention.

First, as shown in FIG. 2A, a lead frame 30 as shown in FIG. 1 formed by a normal lead frame design method is prepared. An adhesive tape is attached on the leads 34 of the lead frame 30 thus prepared in order to fix them. As the adhesive tape 39, a polyimide-based adhesive tape having excellent adhesiveness is used.

Next, as shown in FIG. 2B, the IC chip 3 having a plurality of electrode pads separated from the wafer on the individual die pads 32 of the lead frame 30.
Die attach 1. Here, at the time of die attach, the adhesive for die attachment may be a conductive material such as wax, a thermosetting resin, or a thermoplastic resin depending on the purpose of use.

When using a conductive substance such as the above wax,
An appropriate amount of wax is supplied onto the die pad 32, and the IC chip is hot-pressed. The reason for using conductive material such as wax is
When the back surface is used as a grounding part, a current is allowed to flow from the lead frame, or a die pad is attached to the bottom surface of the separated KGD so that it functions as a heat sink. This will be described later.

On the other hand, as the thermosetting resin, epoxy resins and polyamino acids which are cured with polyimide can be used.

Further, a thermoplastic resin can be used as an adhesive for obtaining a pure KGD instead of attaching a die pad to the bottom surface of the KGD. At this time, as the thermoplastic resin, polyarylene, polyester, polysulfone resin, polyarylet resin, or the like can be used. Since it has fluidity when reflowed at a predetermined temperature, KGD must be easily separated from the die pad. I have to.

After the die attachment is completed, the electrode pads of the IC chip 31 and the ends of the leads 34 corresponding thereto are wire-bonded using gold Au by a hot pressing method. Here, the material of the bonding wire 37 is not particularly limited, and any material that can be bonded to an aluminum electrode pad of a normal IC chip 31 such as aluminum Al capable of ultrasonic wire bonding can be used. Is.

After wire bonding, a trimming process is performed to electrically separate the lead frame 30 and the wire-bonded leads 34. At this time, the opening 36 facilitates the trimming process.

After the trimming process for lead isolation, an AC test and a burn-in test are performed. The reason why the leads connected to the electrode pads of the IC chip 31 are electrically isolated by performing the normal IC assembly process such as the wire bonding and the trimming process using the lead frame 30 as described above is that the test can be performed. It is just a series of tasks to do.

In the above test, the individual chips are not separated because they are tested, but the leads 3 are not separated.
The entire lead frame 30 on which a plurality of arrays of the IC chips 31 wire-bonded with 4 are mounted is tested at one time.

At this time, a test jig suitable for testing the entire lead frame 30 at a time can be designed and used.

Here, the electrode pads of each IC chip 31 are connected to the leads 34 through the bonding wires 37.
Since the lead 34 serves as an electrode terminal for testing, the design of the test jig is easier than in the conventional design of the test socket adaptor by forming the fine bumps.

By using the test jig, about 16 IC chips 31 are provided on one lead frame 30.
It becomes possible to perform a batch test with the installed. During the AC and burn-in tests, defects I were generated.
A C chip is detected, and such an IC chip is processed as a defective product.

Next, as the final step of the KDG array manufacturing method according to the present invention, which is the most important step for producing KGD, after the AC test and the burn-in test are completed, the electrode pads of the IC chip 31 and A step of cutting the bonding wires 37 electrically connecting the respective leads 34 corresponding thereto is performed.

The bonding wire 37 is provided to provide an electrode terminal for a test during the AC test and the burn-in test, and is not directly necessary for the KGD array according to the present invention, so it is removed.

In the step of cutting the bonding wire, a cutting device 40 as shown in FIG. 4 (a) is used. This cutting device 40 has a chisel shape and has a sharp force at its tip portion to coat a tungsten carbide blade with diamond.

The cutting device 40 is fixed to the arm and moved up and down by a high stepping motor having an allowable error limit of 1 μm. The forward / backward / leftward / rightward movement is adjusted by a highly accurate XY horizontal table.

FIG. 4 (a) is a usage state diagram of the cutting device 40 used in manufacturing the KGD array according to the present invention. As shown in FIG. 4A, the cutting device 40 is moved so as to be close to the central surface of the IC chip 31 bonded and wire-bonded on the lead frame 30.

Wire ball 3 of bonding wire 37
The left / right adjustment to cut the upper part of 7a is XY
It is arranged by a horizontal table, and the lead frame is fixed by a vacuum chuck on the XY horizontal table for precise adjustment of the wire balls.

After cutting the bonding wire 37,
As shown in FIG. 4B, only the cut wire ball 33 remains on the electrode pad of the IC chip 31. The cut wire ball 33 can be used as a pump. At this time, whether or not the bump can be formed and the height thereof can be easily solved by adjusting the descending height of the cutting device 40.

On the other hand, the upper surface of the cut wire ball 33 can be wire-bonded again, and bumping can be performed a plurality of times on the bonding pad as necessary. In order to confirm the reliability of the chip after wire bonding, the wire was cut and then rebonded to perform a pull test. as a result,
The same good data as in the first bonding was obtained. Further, as a result of repeating the experiment 5 times, it was revealed by the experiment of the present inventor that the same data having no defect was obtained.

After the bonding wire cutting step, the resulting structure has the bonding wire, adhesive tape and leads all removed, as shown in FIG.
AC is formed by simply interposing an adhesive 35 on the lead frame 30.
Only the defect-free IC chip 31 that has undergone the test and burn-in test is bonded.

Finally manufactured KGD according to the invention
In the array, a single KGD as shown in FIG. 3 is mounted on the lead frame 30 as a plurality of arrays.
Some sheets of these leadframes 30 are mounted on the currently used leadframe magazine,
Can be shipped to the market. Alternatively, the chips that have been tested can be packaged in a disposable magazine with a low price and transmitted to the purchaser. After being transmitted to the purchaser, a number of IC chips are cut into tie bars, and the individual K chips are attached with the die pad attached to the bottom surface.
It can be used as a GD. As mentioned above,
The die pad can be used as a heat sink.

As described above, according to the present invention, since the IC chips are not individually handled, it is possible to minimize defects that tend to occur during handling of the base chip.

Needless to say, the present invention is not limited to this embodiment without departing from the technical idea of the present invention, and various modifications can be made.

[0069]

As described above, the effects of the KGD array and the manufacturing method thereof according to the present invention are summarized as follows.

It is possible to mass-produce defect-free KGD which has been subjected to the AC test and the burn-in test while using an ordinary IC chip. After shipping the chips to the buyer, the tie bar can be cut, which makes handling at the chip level much easier. Since the equipment used for the existing IC assembly is directly used in the present invention, no additional device is required. It is easy to make a test jig. Standardization is possible. I at the request of the buyer
C chips can be easily classified into those for wire bonding, those for flip chips, and those for bumps. Since the cost of the KGD can be innovatively reduced, the applicable range of the multi-chip module and the ASIC module can be expanded from the currently applied supercomputer to the personal computer.

Therefore, according to the KGD array and the manufacturing method thereof according to the present invention, at least one or more KGDs are mounted on the lead frame as a plurality of arrays,
A large amount of KGD can be obtained in one test process.
Further, the plurality of IC chips can be used as an individual KGD in a state where the tie bar is cut and the die pad is attached to the bottom surface.

[Brief description of drawings]

FIG. 1 is a plan view of a lead frame used in manufacturing a KGD array according to the present invention.

2A and 2B are KGD according to the present invention.
It is a manufacturing-process figure for manufacturing an array.

3 is a perspective view of a KGD according to the present invention provided in an array on the lead frame shown in FIG. 1. FIG.

FIG. 4 (a) is a state view of a cutting device used in manufacturing a KGD array according to the present invention. Figure 4
(B) is a sectional view showing that the cut wire ball 33 remains on the electrode pad of the IC chip after the cutting of the bonding wire.

FIG. 5 is a perspective view of a conventional test socket.

FIG. 6 is a perspective view of a flip chip having a solder bump according to the related art.

7 is a cross-sectional view of a state in which the flip chip shown in FIG. 6 is mounted on a test socket adapter.

[Explanation of symbols]

 30 Lead Frame 31 IC Chip 32 Die Pad 33 Wire Ball 34 Lead 35 Adhesive 38 Tie Bar 37 Bonding Wire 40 Cutting Device

Claims (10)

[Claims] 1. A lead frame provided with a plurality of die pads which are supported by a tie bar and which are regularly arranged, an adhesive agent applied on each die pad of the lead frame, and the adhesive agent applied. A KGD array comprising: a plurality of defect-free KGDs, each of which is bonded to each die pad by an individual die and which has been subjected to a final test. 2. The KGD array according to claim 1, wherein bumps are formed on the respective electrode pads of the plurality of IC chips. 3. The KGD array according to claim 1, wherein the adhesive contains any one of a conductive material such as a wax, a thermosetting resin, or a thermoplastic resin, depending on the purpose of use. . 4. The KGD array according to claim 1, wherein the plurality of IC chips can be used as an individual KGD in a state where the tie bar is cut and a die pad is attached to the bottom surface. 5. The KGD array according to claim 1, wherein the die pad is used as a heat sink. 6. A method of manufacturing a lead frame having a plurality of leads and a plurality of regularly arranged die pads supported by tie bars, and fixing the die pads on the leads of the lead frame. A step of attaching an adhesive tape to each of the lead frames, a step of die-attaching an IC chip having a plurality of electrode pads separated from the wafer on each die pad of the lead frame through an adhesive, and each of the IC chips. Wire-bonding the electrode pads to the corresponding ends of the leads, and performing a trimming process to electrically separate the lead frame and the wire-bonded leads, After the trimming process step, insert the resulting leadframe into the test jig. A method for implementing the AC test and burn-in test and, after the AC test and burn-in test is completed,
KG, which has a step of checking a defective IC chip and a step of cutting an upper portion of each wire ball bonded by a cutting means.
D array manufacturing method. 7. The polyimide-based adhesive having excellent adhesiveness is used as the adhesive tape.
A method for producing the described KGD array. 8. The step of cutting the bonding wire, wherein the height of the cutting means is adjusted to control the size of the cutting and the size of the remaining wire balls to form a pump. The method for manufacturing the KGD array according to claim 6. 9. The K according to claim 6, wherein the adhesive includes one of a conductive material such as a wax, a thermosetting resin, and a thermoplastic resin according to the purpose of use.
Method for manufacturing GD array. 10. The method of manufacturing a KGD array according to claim 6, wherein the plurality of IC chips are used as individual KGDs in a state in which a tie bar is cut and a die pad is attached to a bottom surface.