JP2671650B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit using a MOS field effect transistor (hereinafter referred to as MOS transistor). Dynamic MOS RAM is currently 64
Although mass production of K (D) RAM and development of 256 (D) RAM have been carried out, compared with 16K (D) RAM, the power supply voltage of the recent DRAM is reduced from 12V to 5V by less than 1/2. ing. This is because it was decided to use a single 5V power supply because of the single power supply and TTL compatibility. Further, in general, when the power supply voltage is high in the MOS integrated circuit, the delay time of the basic circuit is reduced and it is easy to achieve high speed. However, the low voltage due to the external factor described above is to speed up the circuit. Is a heavy burden. In addition to setting the voltage high, measures to achieve higher speed include increasing the conductance by shortening the gate channel and increasing the conductance by decreasing the threshold voltage. The increase in the number of contacts has become very important in combination with the development of fine processing technology. Further, along with the development of these fine processing techniques, an important technical subject for increasing the speed is to reduce the resistance of wiring. The scaling rule proposed by Dinard et al. Also pointed out that the CR time constant is deteriorated because the wiring resistance is not scaled down due to the miniaturization. However, the improvement of the transistor characteristics and the increase of the wiring resistance are important for the speedup. It contains a contradiction. FIG. 4 shows a conventional dynamic MOS RAM.
FIG. In the figure, 1 is a clock input terminal to which an external signal is input, 2a to 2n are operated by the input of this external signal, and n-th first to n-th φ1 clock generation circuits 3 to output φ0 signals respectively, Figure 5
A φ1 signal generation circuit for outputting the drive signal φ1 shown in FIG. 5A, and a φ2 for outputting the drive signal φ2 shown in FIG. 5B.
A signal generating circuit, 5 is a φ3 signal generating circuit which outputs the driving signal φ3 shown in FIG. 5C, 6 is a φ4 signal generating circuit which outputs the driving signal φ4 shown in FIG. 5D, and 7 is FIG. ), A φ5 signal generation circuit for outputting a driving signal φ5, 8a is a memory array, 9a to 9f are resistors having resistance values R1 to R6, 10a to 10g are capacitors, 11 is a sense amplifier circuit, and 12a and 12b are transistors. is there. The resistors 9b and 9d represent bit line resistances, and the capacitors 10c and 10d represent bit line capacitances. Further, φ6 is a drive signal shown in FIG. Next, the operation of the semiconductor integrated circuit having the above structure will be described. First, the drive signal φ1 is
Not only is it used as a trigger signal for the two-signal generation circuit 4, but also serves as a signal (word line drive signal) for driving the memory array 8. However, the drive signal φ1 is transmitted to the φ2 signal generating circuit 4 in the next stage, which acts as a trigger, with a small delay, but the internal drive signal φ1a (see FIG. 5A) input to the memory array 8 is generated by the resistor 9a and the resistor 9a. The capacitor 10a causes a delay. Therefore, the peripheral circuit uses the short channel MOST to achieve high speed, but the wiring resistance deteriorates the matching with the delay of the memory array 8. In addition, the delay due to the bit line resistance 9b and the bit line capacitance 10c is guaranteed, and then φ2
It is necessary to activate the signal generation circuit 4 and generate the drive signal φ2 (drive signal of the sense amplifier circuit 11). Moreover, the drive signal φ2 is delayed due to the resistor 9c and the capacitor 10b, and the sense amplifier circuit 11
Phenomenon of slowing down the latch time occurs. On the other hand, the φ3 signal generating circuit 5 drives the driving signal φ2.
Therefore, since the driving can be performed without a signal delay, the mismatching between the peripheral circuit and the memory array 8 also occurs here.
Next, it is necessary to generate the drive signal φ3 for taking out the stored information of the memory cell from the memory array 8 to the peripheral circuit, and the drive signal φ3 (I
/ 0 control signal) is generated. At this time as well, a signal delay is caused by the bit line resistance 9d and the bit line capacitance 10d, and also in the drive signal φ3, due to the resistance 9e and the capacitance 10e, the internal drive signal φ3a (FIG. 5C).
(See reference). Further, the output signal from the memory cell also causes signal delay due to the resistor 9f and the capacitor 10f, and it is easy to cause a mismatch between the drive signal φ4 and the drive signal φ6. This phenomenon of mismatching is sensitive to the power supply voltage. For example, M
When the OST operates in a pentode (saturation region), the conductance of this MOST can be simply expressed by the following equation (1). _{gm ≒ β (V G -V th} ) (1) and therefore. gm increases almost in proportion to V _G , and by shortening the channel, gm increases (β increases). Further, the resistance values R1 to R6 of the resistors 9a to 9f
Can be expressed by the following equation (2). R = ρ · l / W (2) where ρ is the sheet resistance value, l is the length, and W is the width.
Therefore, in order to reduce the resistance value R, it is necessary to decrease ρ and decrease l. However, the decrease of l becomes difficult as the memory array capacity, that is, the integration density of the memory is increased. It becomes important. However, this reduction of ρ becomes a problem of the material itself, so that it is difficult for a highly integrated LSI, and in particular, reduction of the resistance of the diffusion layer has become difficult due to the balance of the characteristics of the MOST. Therefore, the decrease of the conductance gm of the MOST and the increase or the stabilization of the resistance R are remarkable, and the mismatch between the peripheral circuit and the memory array 8 is increased. FIG. 6 is a diagram showing the voltage dependence of the timing, in which the vertical axis represents the power supply voltage V _CC and the horizontal axis represents the time t as the mismatching state as the power supply voltage dependence. is there. For example, when the power supply voltage V _CC is V1, the drive signal φ1 is t2, the drive signal φ3 is t6, and the drive signal φ is
4 is generated at t8 and the drive signal φ6 is generated at t7, but the power supply voltage V _CC rises and V2 (where V2> V
In the case of 1), the driving signal φ1 is t1 and the driving signal φ3 is t1.
3, the drive signal φ4 is generated at t4 and the drive signal φ5 is generated at t5, so that the generation times of the drive signals φ4 and φ6 are reversed. Further, when the power supply voltage V _CC is V1, the time between the drive signal φ3 and the drive signal φ4 is Δt1, but when the power supply voltage V _CC rises to V2, a delay time determined only by the performance of the φ4 signal generation circuit 7 is generated. Therefore, drive signal φ3
From the drive signal φ4 becomes Δt2 which is a very small delay time. However, since the drive signal φ6 depends on the power supply voltage and the delay of the resistor, the drive signal φ6 is further Δ than the time Δt2.
The drive signal φ4 and the drive signal φ6 are inverted with respect to the power supply voltages V1 and V2. In this case, obviously, a circuit defect will occur at the power supply voltage V2. This is easy to understand according to the following equation (3) to qualitatively explain the mismatching. RT = [1 / β (V _G −V _th )] + RC (3) That is, the first term is the resistance component due to the conductance of the transistor of the signal circuit, and the second term is the resistance component due to the wiring resistance. Therefore, the total output impedance of the signal circuit can be expressed by equation (3). The first term is power source dependent, while the second term is power source independent.
Therefore, it can be considered that the reversal of the signal generation times of the drive signal φ4 and the drive signal φ6 occurs. The above will be further described using the signal generation circuit shown in FIG. In FIG. 7, 13a to 13g are MOS transistors, 14a is a signal line for transmitting the φ11 signal shown in FIG. 8B, 14b is a signal line for transmitting the φ11 bar signal shown in FIG. 8A, and 15 is a diagram. A signal line for outputting the φ12 signal shown in 8 (c) and 16 are capacitors. Next, the operation of the signal generating circuit having the above configuration will be described with reference to FIGS. 8 (a) to 8 (c).
First, at time t1, since the low level φ11 signal shown in FIG. 8B is input to the gate of the MOS transistor 13a, the MOS transistor 13a is turned off, while the gates of the MOS transistors 13b and 13c are connected to each other. Since the high level φ11 bar signal shown in FIG. 8A is input, the MOS transistors 13b and 13c are turned on. Therefore, the node N1 is discharged and the node N2 is precharged. In this state, at time t2, as shown in FIG.
11 bar signal becomes low level, and φ1 shown in FIG.
Since one signal goes high, the MOS transistor 13
Both a and 13e are turned on, and both MOS transistors 13b and 13c are turned off. Therefore, the nodes N1 and N3 are charged. Therefore, M
Both the OS transistors 13d and 13f are turned “on” and the node N2 is discharged, but the node N4, that is, the φ12 signal becomes high level as shown in FIG. 8C.
As described above, the time from the input of the φ11 signal to the rising of the φ12 signal is the same as that of the MOS transistors 13a and 13a.
It is controlled by the conductance of d. That is, it is controlled by the resistance component corresponding to the first term of the equation (3). As described above, in the conventional semiconductor integrated circuit, as described in the signal generating circuit shown in FIG. 4, the generation time of the φ11 signal to the φ12 signal is controlled by the MOS transistor. Since it is controlled only by the conductance, the voltage dependency becomes large, and as described above, there is a drawback that the possibility of causing a mismatch matching between the peripheral circuit and the memory array becomes large. Therefore, an object of the present invention is to provide a semiconductor integrated circuit capable of guaranteeing a circuit defect caused by a mismatching of delays between peripheral circuits and a memory array when a power supply voltage is changed. In order to achieve such an object, according to the present invention, an input signal is supplied to one control terminal and the other input terminal is delayed by a delay circuit. In a semiconductor integrated circuit including a matching circuit activated by supplying a predetermined delay signal,
The delay circuit has one terminal connected to the power supply potential.
The other terminal is connected to the first connection point
A first switching element that conducts between both terminals and one of
One terminal is connected to earth potential and the other terminal is
The other of the first switching elements is connected via the first connection point.
Connected to the terminal and between both terminals by the inverted logic signal of the input signal
The second switching element that conducts the
Is connected to the source potential and the other terminal is the second connection point
Connected to and connected to both terminals by an inverted logic signal
Switching element and one terminal connected to ground potential
And the other terminal is connected to the third terminal via the second connection point.
Connected to the other terminal of the switching element of the first connection
4th switch that conducts between both terminals by the signal from the point
And the connection of one of the terminals to the input signal.
The other terminal is connected to the third connection point for power supply potential
Accordingly, a fifth switching element which conducts between both terminals,
One terminal is connected to the power supply potential and the other terminal
Is connected to the fourth connection point for outputting the delayed signal and connected to the third connection point.
The sixth switch that conducts between both terminals by the signal from the continuation point
Connected in series between the ching element and the third and fourth connection points
Capacitor element and one terminal at the fourth connection point
And the other terminal is connected to earth potential.
7th which conducts between both terminals by the signal from the 2nd connection point
Switching element, first switching element and power supply
Between the potential or the first connection point or the second switch
Between the switching element and the ground potential or the first connection point,
Alternatively, the third switching element and the power supply potential or
Between the second connection point or the fourth switching element
To the ground potential or the second connection point, or
Between the connection point 1 and the fourth switching element, or
Is between the second connection point and the seventh switching element.
It is characterized in that it is composed of resistance elements connected in series to each other. The signal is delayed by the impedance element, and is matched with the input signal to be output. FIG. 1 is a circuit diagram showing an embodiment of a semiconductor integrated circuit according to the present invention, and more specifically, a circuit diagram showing an example of a signal generating circuit. In the figure, 17 is a resistor having one end connected to the node N2 and the other end connected to the drain of the MOS transistor 13d. The transistors 13e to 13g and the capacitor 16 form a matching circuit that matches the signal φ11 with the signal from the node N2. Next, the operation of the signal generating circuit having the above configuration will be described. 2 is a graph showing β (source-drain impedance) vs. gate voltage of the MOS transistor 13d in FIG. 1, and is a node N1 in FIG.
(This voltage typically consisting of a power supply voltage V _CC to a value obtained by subtracting the thread hold voltage V _th) of the voltage and Vg, which is a graph showing the impedance between node N2 and ground. Here, for example, the impedance between the node N2 and GND at the power supply voltage V _CC = 5V is about 130.
When set to 0Ω (this impedance is the combined impedance of the resistor 17 and the MOS transistor 13d), the V _CC dependency of the impedance can be shown by the curve A in FIG. It can be seen from this curve A that the voltage dependence of the impedance is greatly reduced. In this case, the size of the MOS transistor 13d is L = 3μ
When m, W = 40 μm, and the size of the resistor 17 is l =
80 μm, W = 4 μm and ρs = 50Ω. Incidentally, V _CC dependency of the impedance of the conventional signal generating circuit, as shown by curve B in FIG. 2, it can be seen that a large circuit arrangement of very dependence on the supply voltage V _CC. In this case, the MOS transistor 13d has L = 3 μm and approximately W =
The size is equivalent to 10 μm. That is, it is shown that when L and W are adjusted in the conventional circuit and the voltage of the node N1 changes, the resistance between the source and the drain changes greatly. This is because the resistance between the node N1 and GND is adjusted to 1300Ω by adjusting the impurity concentration.
The same is true for the case. However, insert the resistor 17,
This shows that if the combined impedance of the transistor when the gate voltage is 5 V is set to 1300Ω, the voltage dependence characteristic becomes small. As described above, in the signal generating circuit shown in FIG. 1, the voltage dependency of the impedance between the node N2 and GND can be reduced, so that the voltage dependency of the delay time from the generation of the φ11 signal to the φ12 signal is reduced. You can
Therefore, for example, the dynamic MOS R shown in FIG.
When the signal generating circuit shown in FIG. 1 is used for the AM φ4 signal generating circuit 6, the φ4 signal and the φ4 signal as described in FIG.
It is possible to eliminate the inversion phenomenon due to the voltage of the signal generation time of the 6 signals. Therefore, it is possible to prevent the mismatching of the delay time between the peripheral circuit and the memory cell array and improve the operation margin of the dynamic MOS RAM. Although the resistor 17 is inserted between the node N2 and the drain of the MOS transistor 13d in the above embodiment, the present invention is not limited to this, and it is inserted between the power supply voltage V _CC and the drain of the MOS transistor 13a. Even if it does, the same effect can be exhibited. At this time, the impedance between power supply voltage V _CC and node N1 can be increased to reduce the voltage dependence of the charging time of node N1. Of course, the resistor 17 may be inserted in another position. FIG. 3 is a circuit diagram showing another embodiment of the signal generating circuit shown in FIG. In the figure, 18a to 18f
Is a resistance position that can be inserted to reduce the voltage dependence of the rise time of the φ11 signal and the φ12 signal.
Shows the case where the resistor 17 is inserted in the resistance position 18d.
Further, 19a to 19d are resistance positions that can be inserted to reduce the voltage dependence of the rise time of the φ11 bar signal to the φ12 signal. The resistance positions 18c and 1
8f is a position where a resistor can be inserted so that the voltage dependence of the rise time of the φ11 bar signal to the φ12 signal can be reduced. That is, this resistor may be inserted in a portion where the output signal component of the inverter exists. Further, the resistance positions 18c and 18f can reduce the voltage dependency both at the rising and falling sides, but if only one of them is desired, for example, at the rising time, the resistance positions 18a, 18b, 18d and 18 are formed.
It is necessary to insert a resistor in e and to insert a resistor in 19a to 19d at the fall. Further, when a resistor is inserted at the source end of the MOS transistor (for example, at the resistance position 18e), the source potential with respect to the MOS transistor 13d becomes high, so that it is necessary to pay sufficient attention to the adjustment of the delay time. Further, in the above description, the resistance positions 18a to
Although the case where resistors are inserted in 18f and 19a to 19d is shown, it goes without saying that a device such as a depletion MOS transistor or a load MOS transistor having a constant gate voltage may be used. Also, the resistive device can be formed of polysilicon and a diffusion layer. As described above in detail, according to the present invention, a resistor is inserted in the portion where the output signal component of the inverter exists, and the input signal and the output signal of the inverter are matched. As a result, both can significantly reduce the power supply voltage dependency of the impedance of each part on the circuit, and can reduce the voltage dependency of the delay time of the generation between each signal. There is an effect that mis-matching due to array delay can be eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing voltage dependence of impedance in the circuits of FIGS. 1 and 2. FIG. 3 is another embodiment. FIG. 4 is a schematic diagram showing a conventional dynamic MOS RAM. FIG. 5 is a diagram showing waveforms of respective parts in FIG. 4 FIG. 6 is a diagram for explaining the operation of FIG. 4 FIG. 8 is a circuit diagram showing the signal generating circuit in FIG. 4. FIG. 8 (a) to FIG. 8 (c) are diagrams showing waveforms of respective portions in FIG. 7 [Description of symbols] 1 clock input terminals 2a to 2n φ1 clock Generating circuit 3 φ1 signal generating circuit 4 φ2 signal generating circuit 5 φ3 signal generating circuit 6 φ4 signal generating circuit 7 φ5 signal generating circuit 8 Memory arrays 9a to 9f, 17 Resistors 10a to 10g, 16 Capacitor 11 Sense amplifiers 12a, 12b, 13a ~ 13g transistor

Claims (1)

(57) [Claims] Is supplied the input signal to the one control terminal, the predetermined delayed its input signal by the delay circuit to the other control terminal
In the semiconductor integrated circuit having a matching circuit activated by being supplied with the delay signal of, the delay circuit has one terminal connected to a power supply potential and the other terminal.
Is connected to the first connection point and is connected between the two terminals by an input signal.
And a first switching element that conducts the
The terminal is connected to the first switching element via the first connection point.
Connected to the other terminal and input by the inverted logic signal of the input signal
A second switching element that conducts between both terminals, and one terminal is connected to the power supply potential and the other terminal
Is connected to a second connection point, and both ends are connected by an inverted logic signal.
A third switching element that conducts between the child and one terminal connected to the ground potential and the other end
The child is connected to the other of the third switching element via the second connection point.
The signal from the first connection point connected to one of the terminals
A fourth switching element that conducts between both terminals and one terminal connected to an input signal and the other terminal
Is connected to the third connection point, and both of
A fifth switching element that conducts between the terminals and one terminal connected to the power supply potential and the other terminal
Is connected to the fourth connection point for outputting the delayed signal and connected to the third connection point.
A sixth switch that conducts between both terminals by a signal from the continuation point.
A switching element and a capacitor connected in series between the third and fourth connection points.
Device and one terminal is connected to the fourth connection point and the other
The terminal is connected to the ground potential and the signal from the second connection point
A seventh switching element for electrically connecting between the two terminals
And the first switching element and the power supply potential or the first connection point
Between the second switching element and the ground potential or the first connection
Point, or the third switching element and the power supply potential or the second connection point
, Or the fourth switching element and the ground potential or the second connection
Between the points, or between the first connection point and the fourth switching element , or
Is between the second connection point and the seventh switching element.
A semiconductor integrated circuit comprising a resistive element connected in series to a crab .