JPH0614613B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit using a MOS field effect transistor (hereinafter referred to as a MOS transistor).

[Prior art]

Dynamic MOS RAM is currently mass production of 64K (D) RAM, 256 (D) RA
M is being developed, but compared to 16K (D) RAM,
In recent DRAMs, the power supply voltage has been reduced from 12V to 5V by less than 1/2. This is because it was decided to use a single 5V power supply due to the single power supply and TTL compatibility. In addition, in general, when the power supply voltage is high in a MOS integrated circuit, the delay time of the basic circuit decreases and it is easy to achieve high speed, but the lower voltage due to the external factors described above achieves higher circuit speed. Is a heavy burden. In addition to setting the voltage high, measures to achieve higher speed include increasing the conductance by shortening the gate channel and increasing the conductance by decreasing the threshold voltage. The increase in the number of contacts has become very important in combination with the development of fine processing technology. Further, along with the development of these fine processing techniques, an important technical subject for increasing the speed is to reduce the resistance of wiring. The scaling rule proposed by Dennard et al. Also pointed out that the CR time constant is deteriorated because the wiring resistance is not scaled down due to miniaturization. There is a big contradiction for the change.

FIG. 1 is a schematic configuration diagram showing a conventional dynamic MOS RAM. In the figure, (1) is a clock input terminal to which an external signal (Ext · clock) is input, and (2a) to (2n) are operated by the input of this external signal and each of the n-th stage outputs φ ₀ signal 1st to nth φ ₀ clock generation circuits, (3) a φ ₁ signal generation circuit for outputting the drive signal φ ₁ shown in FIG. 2 (a), (4) a drive signal shown in FIG. 2 (b) φ ₂ signal generating circuit for outputting φ ₂ , (5) φ for outputting drive signal φ ₃ shown in FIG. 2 (c)
₃ signal generation circuit, (6) outputs the drive signal φ ₄ shown in FIG. 2 (d), ₄ signal generation circuit, and (7) outputs the drive signal φ ₅ shown in FIG. 2 (e) ₅ signal generation circuit, (8) a memory array, (9a) to (9f) having resistances R _{1 to} R ₆ , respectively,
(10a) to (10g) are capacitors, (11) is a sense amplifier circuit,
(12a) and (12b) are transistors.

The resistors (9b) and (9d) represent bit line resistances, and the capacitors (10c) and (10d) represent bit line capacitances. Further, φ ₆ is a drive signal shown in FIG. 2 (f).

Next, the operation of the semiconductor integrated circuit having the above configuration will be described. First, the drive signal φ ₁ is used not only as a trigger signal for the φ ₂ signal generation circuit (4) in the next stage, but also as a signal (word line drive signal) for driving the memory array (8). However, this drive signal φ ₁ is transmitted to the φ ₂ signal generation circuit (4) of the next stage which acts as a trigger with a small delay, but the internal drive signal φ input to the memory array (8)
_1a (see FIG. 2 (a)) is a resistor (9a) and a capacitor (10a).
Delay is caused by a). Therefore, the peripheral circuit can achieve high speed by using the short channel MOST, but the wiring resistance deteriorates the matching with the delay of the memory array (8). In addition, the φ ₂ signal generation circuit (4) is activated after guaranteeing the delay due to the bit line resistance (9b) and the bit line capacitance (10c), and the drive signal φ ₂ (drive signal of the sense amplifier circuit (11)) Need to be generated. Moreover, the drive signal φ ₂ is delayed due to the resistor (9c) and the capacitor (10b), and the sense amplifier circuit (11)
Phenomenon of slowing down the latch time occurs. On the other hand, since the φ ₃ signal generation circuit (5) can be driven by the drive signal φ ₂ without any signal delay, the mismatch circuit between the peripheral circuit and the memory array (8) also occurs here. Next, it is necessary to generate a driving signal phi ₃ for retrieving information stored in the memory cell to the peripheral circuits from the memory array (8), as a trigger a drive signal phi _2, the driving signals phi _{3 (I} / 0 control signal ) Is generated. Also at this time, a signal delay occurs due to the bit line resistance (9d) and the bit line capacitance (10d), and the drive signal φ
_{Also in 3} , the internal drive signal φ _3a (see FIG. 2 (c)) is delayed due to the resistance (9e) and the capacitance (10e). Also, in the output signal from the memory cell, a signal delay occurs due to the resistance (9f) and the capacitance (10f), and it is easy to cause a mismatching between the drive signal φ ₄ and the drive signal φ ₆ . The phenomenon of this mismatching is
Appears sensitively. For example, if the MOST is operating in a pentode (saturation region), the conductance of this MOST is
It can be easily expressed by equation (1).

_{gmβ (V G -V th) (} 1) Thus, gm is increased substantially in proportion to _{V G,} also, (beta is increased) by short channelization gm increases. In addition, the resistance values of resistors (9a) to (9f) (R ₁ ) to (R ₆ )
Can be expressed by the following equation (2).

R = ρ · l / w (2) where ρ is the sheet resistance value, l is the length, and w is the width.
Therefore, in order to reduce the resistance value R, it is necessary to decrease ρ and decrease l. However, the decrease of l becomes difficult as the memory array capacity, that is, the integration density of the memory increases, and thus ρ decreases. Is important. However, since the reduction of ρ becomes a problem of the material itself, it is difficult for highly integrated LSIs, and in particular, reduction of the resistance of the diffusion layer has become difficult due to the balance of the characteristics of MOST. Therefore, it is obvious that the conductance gm of the MOST is reduced and the resistance R is increased or made constant, and the mismatch between the peripheral circuit and the memory array (8) is increased. FIG. 3 is a diagram showing the voltage dependence of timing, in which the vertical axis represents the power supply voltage Vcc, and the horizontal axis represents the state of mismatching when the time t is taken as the power supply voltage dependence. For example, power supply voltage Vc
When c is V ₁ , the drive signal φ ₁ is t ₂ and the drive signal φ ₃
Is t ₆ , the driving signal φ ₄ is t ₈ , and the driving signal φ ₆ is t ₇
Power supply voltage Vcc rises and V ₂
(However, when V ₂ > V ₁ ), the drive signal φ ₁ is t
₁ , the driving signal φ ₃ is generated at t ₃ , the driving signal φ ₄ is generated at t ₄ , and the driving signal φ ₆ is generated at t _5.
The generation times of ₄ and φ ₆ are reversed. Further, when the power supply voltage Vcc is V ₁ , the drive signal φ ₃ to the drive signal φ ₄
Although the time during a Delta] t _1, when the power supply voltage Vcc rises to V _2, phi ₄ for the signal generation circuit (7) the delay time determined only by the performance of, the driving signal phi ₃ between the driving signals phi ₄ The time becomes Δt ₂ , which is a very small delay time. However, the drive signal φ ₆ is generated after a delay of Δt ₃ from the time Δt ₂ due to the delay of the resistor that does not depend on the power supply voltage, and the drive signal φ ₄ and the drive signal φ ₆ are generated by the power source voltages V ₁ and V 6. It reverses at ₂ . In this case, obviously, a circuit defect will occur at the power supply voltage V ₂ . This is described in (3) below to qualitatively explain the mismatch.
It is easy to understand according to the formula.

That is, the first term is the resistance component due to the conductance of the transistor of the signal circuit, and the second term is the resistance component due to the wiring resistance. Therefore, the total output impedance of the signal circuit can be expressed by equation (3). The first term is power source dependent, while the second term is power source independent. Therefore, it can be considered that the reversal of the signal generation times of the drive signal φ ₄ and the drive signal φ ₆ occurs. Fourth of the above
Further description will be given using the signal generating circuit shown in the figure. This 4th
In the figure, (13a) to (13g) are MOS transistors, (14a) is a signal line for transmitting the φ ₁₁ signal shown in FIG. 5 (b), and (14b) is shown in FIG. 5 (a). Signal line for signal transmission, (15) is φ ₁₂ shown in Fig. 5 (c)
A signal line for outputting a signal, and (16) is a capacitor. Next, FIG. 5 shows the operation of the signal generating circuit having the above configuration.
This will be described with reference to (a) to FIG. 5 (c). At time t _1, FIG. 5 to the gate of the MOS transistor (13a) (b)
Since the low level φ ₁₁ signal shown in is input,
While the transistor (13a) is turned off, the gates of the MOS transistors (13b) and (13c) have the high level shown in FIG. 5 (a). Since a signal is input, this MOS transistor (13b) and
(13c) is turned on. Therefore, the node N ₁ is discharged and the node N ₂ is precharged. In this state, at time t ₂ , as shown in FIG. 5 (a), Since the signal becomes low level and the φ ₁₁ signal shown in FIG. 5 (b) becomes high level, the MOS transistors (13a) and (13
e) are both turned on, and the MOS transistor (13b) and
Both (13c) are turned off. Therefore, the node N ₁ and the node N ₃ are charged. Therefore, the MOS transistors (13d) and (13f) are both turned on, and the node N
₂ is discharged, but the node N _4, that is, the φ ₁₂ signal becomes high level as shown in FIG. 5 (c). Thus, φ
The time from the input of ₁₁ signal to the rise of φ ₁₂ signal is
It is controlled by the conductance of the MOS transistors (13a) and (13d). That is, it is controlled by the resistance component corresponding to the first term of the equation (3).

As described above, in the conventional semiconductor integrated circuit as described in the signal generating circuit shown in Figure 4, from phi ₁₁ signal phi
_Since the control of the generation time of the ₁₂ signal is controlled only by the conductance of the MOS transistor, there is a drawback that the voltage dependency becomes large and the possibility of causing the mismatch between the peripheral circuit and the memory array becomes large as described above.

[Outline of Invention]

Therefore, an object of the present invention is to provide a semiconductor integrated circuit capable of guaranteeing a circuit defect caused by a delay mismatch between a peripheral circuit and a memory array when a power supply voltage is changed.

In order to achieve such an object, the present invention provides an inverter circuit that receives a signal and outputs a signal for controlling a MOS transistor of an output circuit in series between a power supply potential node and a ground potential node. A resistance device is connected in series with two connected MOS transistors, and the charging time at the output node of the inverter circuit is reduced by reducing the power supply voltage dependence of the impedance at the desired point of this inverter circuit. Alternatively, the discharge time voltage dependency is reduced, which will be described in detail below with reference to examples.

Example of Invention

FIG. 6 is a circuit diagram showing an embodiment of a semiconductor integrated circuit according to the present invention, and more specifically, a circuit diagram showing an example of a signal generating circuit. In the figure, (13a) is the second MOS transistor described in between the power supply potential node and the first output node N ₁ when the φ ₁₁ signal which is the input signal is input to the gate electrode.
Transistor, (13b) is the input signal to the gate electrode A first MOS transistor to which a signal is input and which is connected between a ground potential node and the first output node N ₁ ;
A first inverter circuit is configured with the second MOS transistor (13a). (13c) is the gate electrode A signal is input, the power supply potential node and the second output node N
Fourth MOS transistor connected between a _2, (13d) has a gate electrode connected to the first output node N _1, connected between the output node N ₂ of the ground potential node and the second The third MOS transistor, (17), is a resistive device consisting of resistors connected in series with the third and fourth MOS transistors (13d) and (13c) between the power supply potential node and the ground potential node. In this embodiment, one end is connected to the output node N ₂ and the other end is connected to the drain electrode of the third MOS transistor, and the third and fourth MOS transistors (13a (13e) is a seventh MOS transistor in which the gate electrode is connected to the power supply potential, the source electrode is connected to the node N ₃ , and the drain electrode receives the φ ₁₁ signal. , (13g) has the gate electrode above The second is connected to the output node N ₂ of the inverter, a fifth MOS transistor connected between the signal line (15) connected to an output terminal ₄ and the ground potential node, and (13f) is a gate electrode A sixth MOS transistor connected to the node N ₃ and connected between the output terminal N ₄ and the power supply potential node, (16) is connected between the node N ₃ and the output terminal N ₄ . The fifth to seventh MOS transistors (13e) (13f), which are capacitors.
(13g) constitutes an output circuit which outputs a φ ₁₂ signal which is an output signal.

Next, the operation of the signal generating circuit having the above configuration will be described. FIG. 7 is a graph showing the gate voltage vs. β (source-drain impedance) of the MOS transistor (13d) in FIG. 6, and the voltage of the node N1 in FIG. 6 is Vg (this voltage is generally , The value obtained by subtracting the threshold voltage Vth from the power supply voltage Vcc), node N
It is a graph showing the impedance between 2 and the ground.

Here, for example, the node N at the power supply voltage Vcc = 5V
When the impedance between 2 and GND is set to about 1300Ω as an example (this impedance is the combined impedance of the resistor (17) and the MOS transistor (13d)), the Vcc dependence of the impedance is shown by the curve A in FIG. be able to. It can be seen from this curve A that the voltage dependence of the impedance is greatly reduced. In this case MO
When the size of the S transistor (13d) is L = 3 μm, W
= 40 μm, the size of the resistor (17) is l = 80 μm,
W = 4 μm and ρ _s = 50Ω. As shown by the curve B in FIG. 7, it can be seen that the impedance of the conventional signal generating circuit shown in FIG. 4 has a very large dependency on the power supply voltage Vcc, as shown by the curve B in FIG. In this case, the MOS transistor (13d) has a size corresponding to L = 3 μm and about W = 10 μm.

That is, by adjusting L and W in the conventional circuit, for example, the node N
It is shown that when the voltage of 1 changes, the source-drain resistance changes significantly. This is the same when the impurity concentration is adjusted and the resistance between the node N1 and GND is set to 1300Ω. However, it is shown that when the resistor (17) is inserted and the combined impedance of this and the transistor when the gate voltage is 5 V is set to 1300Ω, the voltage dependence characteristic becomes small. As described above, in the signal generating circuit shown in FIG. 6, the voltage dependence of the impedance between the node N ₂ and the ground voltage can be reduced, that is, at the second output node N ₂ of the second inverter circuit. Since the voltage dependency of the discharge time can be reduced, the voltage dependency of the delay time from the generation of the φ ₁₁ signal to the φ ₁₂ signal can be reduced. Therefore, for example, the dynamic MO shown in FIG.
When the signal generation circuit shown in FIG. 6 is used for the φ ₄ signal generation circuit (6) of SRAM, the inversion phenomenon due to the voltage of the signal generation time of the φ ₄ signal and the φ ₆ signal as described in FIG. Can be resolved. Therefore, it is possible to prevent the mismatching of the delay time between the peripheral circuit and the memory cell array, and improve the operation margin of the dynamic MOS RAM.

Although the resistor (17) is inserted between the node N ₂ and the drain of the MOS transistor (13d) in the above-described embodiment, the present invention is not limited to this, and the resistor (17) is connected between the power supply potential node and the drain of the MOS transistor (13a). Even if it is inserted between them, the same effect can be exhibited. At this time, the power supply potential node and the node N
Increases the impedance between _1, it is possible to reduce the voltage dependence of the charging time of the node N _1, it is possible to reduce the voltage dependence of the delay time from phi ₁₁ signal until the generation of the phi ₁₂ signal. Of course, the resistor (17) may be inserted in another position.

FIG. 8 is a circuit diagram showing another embodiment of the signal generating circuit shown in FIG. In the figure, (18a) to (18f) are insertable resistance positions for reducing the voltage dependence of the rise time of the φ ₁₁ signal and the rise time of the φ ₁₂ signal, and in FIG. The case where a resistor (17) is inserted is shown.
Also, (19a) ~ (19d) This is a resistance position that can be inserted to reduce the voltage dependence of the fall time of the φ ₁₂ signal from the rise of the signal. Resistance positions (18c) and (18f) are This is a position where resistance can be inserted so that the voltage dependence of the fall time of the φ ₁₂ signal from the rise of the signal can be reduced.

That is, this resistor may be inserted in a portion where the output signal component of the inverter exists. Further, the resistance positions (18c) and (18f) can reduce the voltage dependency at both the rising and falling edges of the φ ₁₂ signal, but if only one of them is desired, for example, at the rising edge of the φ ₁₂ signal, the resistance positions (18a) ), (18b), (18d) and (18e), and resistors may be inserted at (19a) to (19d) when the φ ₁₂ signal falls. Also, when a resistor is inserted at the source end of the MOS transistor (for example, at the resistance position (18e)), the source position with respect to the MOS transistor (13d) becomes high, so it is necessary to be careful when adjusting the delay time. .
Further, in the above description, the resistance positions (18a) to (18f) and (19f).
Although a case where a resistor is inserted in a) to (19d) is shown, it goes without saying that a device such as a depletion MOS transistor as a resistive device (17) or a load MOS transistor having a constant gate voltage may be used. is there. Also,
The resistive device can be formed by polysilicon, a diffusion layer.

〔The invention's effect〕

As described in detail above, according to the present invention, an inverter circuit that receives a signal and outputs a signal for controlling a MOS transistor of an output circuit is connected in series between a power supply potential node and a ground potential node. Since the resistive device is connected in series with the two MOS transistors that are connected, it is possible to reduce the power supply voltage dependency of the impedance at the desired point of this inverter circuit, and to reduce the charging time or discharge at the output node of the inverter circuit. Since the power supply voltage dependency of time can be reduced, there is an effect that the power supply voltage dependency of rising or falling in the output signal from the output circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a conventional dynamic MOS RAM,
2 (a) to 2 (f) are diagrams showing waveforms of respective portions of FIG. 1,
FIG. 3 is a diagram for explaining the operation of FIG. 1, FIG. 4 is a circuit diagram showing a signal generating circuit in FIG. 1, and FIG.
FIG. 5 (c) is a diagram showing the waveform of each part of FIG. 4, FIG. 6 is a circuit diagram showing one embodiment of the semiconductor integrated circuit according to the present invention,
FIG. 7 is a diagram showing the voltage dependence of impedance in the circuits of FIGS. 4 and 6, and FIG. 8 is a circuit diagram showing another embodiment of the semiconductor integrated circuit according to the present invention. (1) …… Clock input terminal, (2a) to (2n) …… First to nth
Φ ₁ clock generator, (3) …… φ ₁ signal generator,
(4) …… φ ₂ signal generation circuit, (5) …… φ ₃ signal generation circuit,
(6) ...... φ ₄ signal generating circuit, (7) ...... φ ₅ signal generating circuit,
(8) …… Memory array, (9a) to (9f) …… Resistance, (10a) to (1
0g) …… Capacitor, (11) …… Sense amplifier circuit, (12a)
And (12b) …… transistor, (13a) to (13g) …… MOS transistor, (14a), (14b) and (15) …… signal line, (16)
...... Capacitor, (17) ...... Resistance, (18a) to (18f) and (1
9a) to (19d) …… Resistance position. The same reference numerals indicate the same or corresponding parts.

Claims (3)

[Claims] 1. A first MOS transistor connected between a first output node and a ground potential node and having an input signal input to a gate electrode, and between the first output node and a power supply potential node. A first inverter circuit having a second MOS transistor connected to the first output circuit, a gate electrode connected to a first output node of the first inverter circuit, and a gate electrode connected between the second output node and the ground potential node. A third MOS transistor connected between the power supply potential node and the ground potential node, and a fourth MOS transistor connected between the second output node and the power supply potential node, and the third MOS transistor connected between the power supply potential node and the ground potential node. And a second device having a resistive device connected in series with the fourth MOS transistor
An inverter circuit having a gate electrode connected to a second output node of the second inverter circuit, and a semiconductor having an output circuit having a fifth MOS transistor connected between an output end and a ground potential node. Integrated circuit. 2. A first MOS transistor connected between a first output node and a ground potential node and having an input signal input to a gate electrode, and between the first output node and a power supply potential node. A first inverter circuit having a second MOS transistor connected to the node and a resistive device connected in series with the first and second MOS transistors between the power supply potential node and the ground potential node A gate electrode is connected to a first output node of the first inverter circuit, a third MOS transistor connected between a second output node and a ground potential node, and the second output node A second inverter circuit having a fourth MOS transistor connected between the power supply potential node and a second output node of the second inverter circuit, and a gate electrode connected to the second output node The semiconductor integrated circuit having an output circuit having a fifth MOS transistor connected between the output terminal and the ground potential node. 3. The second inverter circuit has a resistive device connected in series with third and fourth MOS transistors between a power supply potential node and a ground potential node. The semiconductor integrated circuit according to claim 2.