JP2667061B2 - Tone supply device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tone supply device for an ATM exchange.

[0002]

2. Description of the Related Art ATM exchanges, like other exchanges,
A tone signal (voice signal) such as a busy tone, a ringback tone, or a PB signal tone is supplied to the telephone terminal as needed. FIG. 2 shows a configuration of a conventional tone supply device, and further shows a configuration until tone information output from the tone supply device reaches a telephone terminal.

FIG. 2 shows a conventional tone supply device 10.
Is a tone generator 11, a time switch (TSW) 12,
It comprises a plurality of cell assembling circuits 13 and a cell multiplexing circuit 14.

[0004] A tone generator 11 generates data (tone data) of various tone signals converted into PCM, and is connected to a time switch 12 via a time division highway HWa. The tone generator 11 supplies various tone data to each time slot of the time division highway HWa.

[0005] In addition, including a time-division highway described later,
The time division highway in FIG. 2 has a frame format as shown in FIG. That is, 1
One frame is 25 μs, and this one frame is divided into 32 time slots, and one byte data is inserted in each time slot.

The time switch 12 is a time division highway H
This is a time switch capable of outputting an arbitrary time slot of Wa to a time slot at an arbitrary position of n time-division highways HWb1 to HWbn. That is, it has a time slot copy function. The switching by the time switch 12 is executed based on information stored in a built-in control memory, such as a telephone terminal to which a tone signal is to be supplied and a tone type.

[0007] The n cell assembling circuits 13 are connected to the corresponding time-division highways HWb1 to HWbn, accumulate tone data in units of time slots, and have a uniqueness on an output path Rd from the tone supply device 10. An ATM cell having the following header is assembled and output to the routes Rc1 to Rcn.

FIG. 4 shows the format of an ATM cell. The ATM cell is composed of a total of 53 bytes, including a 5-byte header used for identifying the ATM cell, a 47-byte information field payload, and an unused area of 1 byte. The stored tone data described above is inserted into the payload.

The cell multiplexing circuit (cell MUX circuit) 14
ATM cells input from routes Rc1 to Rcn
These are multiplexed and output to the ATM switch 20 via the path Rd.

The tone supply device 10 having the above configuration
Operates as follows when one tone signal is supplied to x telephone terminals. The time slot on the time-division highway HWa having the designated tone data output from the tone generator 11 is subjected to position conversion (time slot replacement) by the time switch 12,
Multiple copies are made to time slots on the time-division highways HWb1 to HWbn. The number of copies is the number of telephone terminals that are to supply the same tone signal. Time division highway HWb1 to HW to which tone data is copied
The time slot on bn is input to the cell assembly circuit 13. In the cell assembling circuit 13, 47 bytes (payload) of tone data are accumulated in time slot units, a header unique on the path Rd is added thereto, an ATM cell is completed, and the ATM cell is output to the cell multiplexing circuit. . At this time, ATM cells having the same tone data but different headers are output to the cell multiplexing circuit 14 by the number of telephone terminals to which tone signals are to be supplied. Paths Rc1 to Rc1 including such tone data in the payload
The ATM cell from Rcn is multiplexed by the cell multiplexing circuit 14 and output to the ATM switch 20 via the path Rd.

In the ATM switch 20 and thereafter,
The ATM cell having the tone data is also supplied to the telephone terminal 21 in the same manner as the ATM cell having general communication information.

That is, the ATM cell is the ATM switch 2
0, and is output to the subscriber line terminal 30 via the paths Re1 to Rem. In the subscriber line termination device 30, the ATM cells are separated by a cell separation circuit (cell DMX circuit) 31 and the paths Rf1-R
fk, is further decomposed by the cell disassembly circuit 32 and output to one time slot of the time-division highway HWg1 to HWgk, and the subscriber line interface circuit (SLIC) 32 corresponding to the time slot receives tone data. This is converted into a tone signal (analog signal) by the subscriber line interface circuit 32 and output to the telephone terminal 21. The time slot for supplying tone data at this time and the route R
AT having tone data output from c1 to Rcn
There is a one-to-one correspondence with M cells.

[0013]

As described above, the tone signal may need to be supplied to a plurality of telephone terminals at the same time. However, it is impractical and wasteful to prepare the same number of telephone terminals that may simultaneously supply the same tone data. Therefore, it is required to copy the tone data.
0 itself does not have a copy function (ATM cell broadcast function). Therefore, as described above, the conventional tone supply device 10 includes the time switch 12 having a copy function in units of time slots.
Has a plurality of output highways HEb1 to HWbn and thus has a plurality of cell assembling circuits 13 and a cell multiplexing circuit 14.

However, the types of tones have increased,
Moreover, assuming that the signal is supplied to a plurality of telephone terminals, a time-division highway HWa having many types of tone data is provided.
The upper time slot needs to be copied to the time division highways HWb1 to HWbn by the time switch 12, and the number of cell assembly circuits 13 provided corresponding to the time division highways HWb1 to HWbn also increases. As a result, the size and complexity of the tone supply device 10 cannot be avoided.

As described above, such a problem arises from the fact that the time switch 12 is provided for realizing the broadcasting function.

The present invention has been made in view of the above points, and it is possible to appropriately tone even when there are many telephone terminals to be supplied simultaneously without using a time switch and using a small number of cell assembly circuits. It is an object of the present invention to provide a simple and small tone supply device capable of supplying a signal.

[0017]

In order to solve the above problems, a tone supply device in an ATM exchange according to the present invention comprises:
The following means are provided.

That is, tone data storage means storing a plurality of types of tone data, control of the assembly status of the tone data to be inserted into the payload of the ATM cell, the header given to the ATM cell, and the type of tone to be transmitted. Control information storage means for managing a plurality of pieces of information which can be transmitted within a cycle of transmitting an ATM cell having the same header; a header read from the control information storage means; and a tone read from the tone data storage means. Cell assembling means for assembling an ATM cell from data and outputting it to the ATM switch. A tone data read address forming means for forming a read address for the tone data storage means based on an assembling state of the tone data read from the control information storage means and a tone type; and the control information storage means for every ATM cell time. Timing control means for outputting one piece of control information and controlling operation timing of the cell assembling means and the tone data read address forming means is provided.

[0019]

According to the present invention, a plurality of types of tone data are stored in the tone data storage means in advance. The control information storage means manages and stores a plurality of pieces of control information on the telephone terminals that need to supply a tone signal at that time. That is, control information including the assembling status of tone data to be inserted into the payload of the ATM cell, the header given to the ATM cell, and the type of tone to be transmitted, can be transmitted within a period for transmitting the ATM cell having the same header. Managing.

The timing control means causes the control information storage means to output one piece of control information every one ATM cell time. The header read out from the control information storage means is supplied to the cell assembling means, and the read tone is read out. The data assembly status and the tone type are given to the read address forming means. The read address forming means forms a read address for the tone data storage means from the assembling status of the tone data read from the control information storage means and the tone type while receiving the timing control by the timing control means. Give to. Thus, the tone data read from the tone data storage means is also supplied to the cell assembling means. Then, the cell assembling means receives the timing control by the timing control means,
ATM data is read from the header read from the control information storage means and the tone data read from the tone data storage means.
The cell is assembled and output to the ATM switch.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the tone supply apparatus according to the present invention will be described below. First, the concept of adopting this embodiment will be described.

As shown in FIG. 3, since the normal time division highway has a frame of 125 μs, one time slot transmits and receives one byte of data once every 125 μs. On the other hand, since the ATM cell has a payload of 47 bytes as shown in FIG. 4, the ATM cell to one destination is 125 μs × 47 = 5.88 ms.
The transmission may be performed at a rate of one ATM cell every time. Here, the bit stream speed on the path of the ATM cell is 15
Assuming that 5.52 Mbps, the ATM cell time including the header is 2.73 μs.
During a cell transmission period of 5.88 ms, about 2150 (=
(5.88 ms ÷ 2.73 μs) can be transmitted.

As described above, approximately 2150 types of ATM cells can be transmitted during the transmission period of 5.88 ms for ATM cells to the same destination. By providing an ATM cell containing data, the same kind of tone signal can be simultaneously supplied to a plurality of telephone terminals. Further, in the tone supply device, it is sufficient if one ATM cell can be assembled within one ATM cell time (2.73 μs).
It is not always necessary to perform processing in units of time slots. If an ATM cell can be assembled except for processing in units of time slots, a conventional time switch can be omitted. Therefore, in the embodiment, the tone data is stored in the memory, and the tone data is taken out from the memory to directly assemble the ATM cell.

FIG. 5 is a time chart showing an outline of processing according to the embodiment for transmitting an ATM cell containing tone data in accordance with the above concept. As the synchronization signal, 1
5.88 ms which is the transmission cycle of ATM cells to one destination
The synchronization signal shown in FIG. 5A (hereinafter referred to as the same cell transmission cycle signal) and 2.73, which is one ATM cell time, are shown.
It is assumed that a synchronization signal (hereinafter referred to as a cell synchronization signal) shown in FIG. Then, as shown in FIG. 5C, after detecting the valid edge of the same cell transmission period signal, one tone data is transferred from the tone data memory to the payload of the ATM cell in synchronization with the valid edge of the cell synchronization signal. The ATM cell is assembled by reading the minute (47 bytes) and adding a header, and this assembly is completed by the next valid edge of the cell synchronization signal. As shown in FIG. 5D, the assembled ATM cell is sent to the ATM switch with the next valid edge of the cell synchronization signal as a trigger. At this time, an ATM cell having tone data to be transmitted next is assembled in parallel. By repeating such assembling and sending operations 2048 times, an ATM cell having 2048 kinds of headers (destinations) can be assembled and supplied. After the completion of the assembling process and the sending process of the 2048 types of ATM cells, the assembling and sending are stopped until the next valid edge of the same cell sending period signal is detected.

The idle state is provided in order to absorb a timing gap generated because the cycle of the cell synchronization signal is not an integral multiple of the cycle of the same cell transmission cycle signal. The reason is to absorb the margin time naturally caused by selecting the number of types of ATM cells within the signal cycle, instead of the maximum possible 2150 types, but the 2048 type which is a multiplier of 2 suitable for digital processing.

FIG. 1 is a block diagram showing a specific circuit of the embodiment. Hereinafter, a specific configuration will be described with reference to FIG.

The tone supply device 40 of this embodiment comprises a tone data memory 41, a control memory 42, a cell assembling circuit 43, an address timing generator 44, an offset counter circuit 45, two latch circuits 46 and 47
An adder circuit 48 and a block end code detection circuit 49
It is composed of

The tone data memory 40 is constituted by, for example, a read-only memory (ROM) having an 8-bit width (1 byte width), and stores a plurality of types of tone data. Each type of tone data is stored as a block having consecutive addresses. In addition,
Since the total data amount differs depending on the type of tone, a block end code is stored at the last address of the tone data block to indicate a break between blocks. As the block end code, for example, “FF” can be used. In this case, if "FF" exists in the tone data to be stored, the tone data is changed to "FE" and stored. Since the error of the level of the tone signal (analog signal) is 1/256 even in this case,
It doesn't really matter. As will be described later, the address S1 for the tone data memory 41 is supplied from the adder circuit 48, and the 1-byte tone data S2 of the address is supplied to the cell assembling circuit 43 and the block end code detecting circuit 49. I have.

The control memory 42 is composed of a random access memory (RAM) of, for example, a dual-port configuration, and is provided within one cycle of the same cell transmission cycle signal (represented by the symbol S3 in FIG. 1). It has an address space of 2048 words, which is the maximum number of ATM cells that can be included. One word of the control memory 42 is composed of three fields: a header field, a load offset field, and a tone type field.

The header field stores the header of the ATM cell such as the destination of the ATM cell and data indicating that the ATM cell is a cell for supplying a tone. In the tone type field, the start address of any tone data block in the tone data memory 41 is stored. The load offset field contains the start address of the tone data block and the latest transmitted A
The shift amount (offset) from the address of the tone data memory 41 corresponding to one byte of the last tone data in the TM cell is stored. That is, at the end of the assembling of the ATM cell for a certain destination, the address of the first tone data necessary for assembling the ATM cell in the next cycle of the same cell transmission cycle signal is stored. In practice, the total amount of each type of tone data is not equal to the length of the payload of the ATM cell.
When the total amount of data is short, tone data of one cycle or more is inserted into one ATM cell and sent. In both cases, the ATM cell at the end of assembling the ATM cell is transmitted. Since tone data is often in the middle of a tone, it is necessary to store and manage the offset described above.

Writing and erasing to and from the control memory 42 is performed by a system CPU (not shown) that controls the entire ATM switch having the tone supply device 40 by a telephone terminal that is required to supply a tone signal at that time. It is based on information. The load offset at the time of writing by the CPU has an initial value of 0. The load offset used to define the first 1-byte tone data of the second and subsequent ATM cells for the same destination is written in the offset field based on the offset write signal S9 output from the address timing generator 44. It is.

On the other hand, the control memory 42 performs a read operation based on a control memory read address S4 supplied from an address timing generator 44. The read header S5 is supplied to the latch circuit 46, and is latched based on the latch timing signal S6 output from the address timing generator 44. The read tone type S7 is supplied to the latch circuit 47, and the latch timing signal S6
Latched based on. The read load offset S8 is supplied to the offset counter circuit 45, and is loaded based on the latch timing signal S6.

The cell assembling circuit 43 includes, for example, two ATMs.
It is composed of a random access memory (RAM) having a two-sided structure capable of simultaneously storing the information amount of cells, and can assemble an ATM cell and send out the ATM cell assembled immediately before it in parallel. . Cell assembly circuit 43
Converts the already assembled ATM cell S11 when detecting the valid edge of the cell synchronization signal S10 into an ATM.
Output to the switch (see FIG. 2). Cell assembly circuit 43
Fetches the header S5 latched by the latch circuit 46, then sequentially fetches byte-by-byte tone data S2 provided from the tone data memory 41 to assemble an ATM cell. In addition, tone data S2 of 1 byte at a time
Is taken in based on the tone data latch signal S12 output from the address timing generator 44. When the load offset write signal S9 is given, the fetch operation ends.

The address timing generator 44 is provided with, for example, the same cell transmission period signal S3 and the cell synchronization signal S1 provided by dividing the frequency of the original oscillation clock signal and supplied from the outside.
On the basis of 0, various addresses and timing signals described above and described later used in the tone supply device 40 are formed and output.

The offset counter circuit 45 is, for example, a binary counter. The offset counter circuit 45 generates an offset S13 of the tone data to be read from the tone data memory 41 from the head address of the block to which the tone data belongs, and adds It is provided to the control memory 42. As described above, the offset counter circuit 45 updates the offset S13 by incrementing by one each time the clock S14 is supplied from the address timing generator 11 after the loading offset S8 is loaded, as described above. The operation is performed only while the enable signal S15 output from the address timing generator 44 is active. During the period in which the enable signal S15 is active, 48 clocks S14, one more than 47, which is the byte number of the payload of the ATM cell, are generated. Further, the phase of the clock S14 is set to be ahead of the phase of the tone data latch signal S12. Further, the reset is performed when the reset signal S16 is supplied from the block end code detection circuit 49, that is, the offset S13
Is set to an initial value 0.

The adder circuit 48 adds the tone type (head address of the tone data block) S7 latched by the latch circuit 47 and the offset S13 given from the offset counter circuit 45, and adds the read address S7.
1 is provided to the tone data memory 41.

The block end code detecting circuit 49 monitors the byte-by-byte tone data S2 output from the tone data memory 41, and if it is a block end code,
The reset signal S16 is supplied to the offset counter circuit 45.

FIG. 6 is a time chart of each part of the tone supply device 40 having the above configuration. Hereinafter, the operation of the tone supply device 40 will be described with reference to FIGS. FIG. 6 does not show all the signals shown in FIG. FIGS. 6 (D) to 6 (J) show FIGS.
3C is an enlarged view of the time axis.

The address timing generator 44 is shown in FIG.
When the first valid edge of the cell synchronization signal S10 shown in FIG. 6B is detected after detecting the valid edge of the same cell transmission period signal S3 shown in FIG. 6A, the control memory 42 shown in FIG. The read address S4 is set to an initial value # 0, and thereafter, every time a valid edge of the cell synchronization signal S10 is detected, the value of the read address S4 is incremented, and the read address S4 becomes the 2048th value # 20.
After reaching 47, the read address S4 is held at the value # 2047 until the next valid edge of the same cell transmission periodic signal S3 is detected.

Hereinafter, the read address S of the control memory 42
The operation when 4 is fixed to a certain value # 0 as shown in FIG.

The address timing generator 44 makes the latch timing signal S6 shown in FIG. 6E significant after a slight delay after changing the value of the read address S4 to # 0. As a result, the address S4 of the control memory 42 becomes # 0.
Is latched by the latch circuit 46, and the tone type S7 (hereinafter, its value is referred to as Y) is latched by the latch circuit 47 (see FIG. 6F). At the same time, the load offset S8 (indicated by X in FIG. 6) is loaded into the offset counter circuit 45.

Further, the address timing generator 44 is
When the latch timing signal S6 becomes significant, the enable signal S15 shown in FIG. 6G for the offset counter circuit 45 is activated, and the clock S14 of the predetermined period T1 (see FIG. 6H) is offset from this time. It is given to the counter circuit 45. Therefore, from the offset counter circuit 45, the loaded offset X
6 is incremented at every clock S14, that is, X + 1, X + 2,.
Is output to the control memory 42 and the adder circuit 48. The address timing generator 44 is
When the output of the 47 offsets S13 is completed, the enable signal S15 is made negative at the timing of changing to the 48th offset S13 (X + 47), and the offset is maintained until the latch timing signal S6 becomes significant next.

In the adder circuit 48, the tone type S7
(Value Y) and the offset S13 are added, and this becomes the read address S1 of the tone data memory 41.
The read address S1 is X + Y, X + Y + 1, X + Y +
2,..., X + Y + 47. This allows
The address of the tone data block starting from address Y is X + Y, X + Y + 1, X + Y + 2,.
One byte of tone data S2 from the area of X + Y + 47
Are sequentially read in the cycle T1.

The address timing generator 44 activates the tone data latch signal S12 shown in FIG. 6 (I) supplied to the cell assembling circuit 43 47 times at such a timing that the changing tone data S2 is stable. . Therefore, when 1-byte tone data from the address X + Y + 47 is output from the tone data memory 41, it does not become active.

In the cell assembling circuit 43, when the tone data latch signal S12 is first activated, the latch circuit 4 is activated.
6, the first byte of the tone data S2 and the first byte of the tone data S2 are fetched. Thereafter, each time the tone data latch signal S12 becomes active, one byte of the tone data S2 at that time is fetched and the ATM cell S11 I will assemble. The address timing generator 44 activates the load offset write signal S9 shown in FIG. 6 (J) only for a predetermined period from a point slightly after the point when the enable signal S15 is made negative.
As a result, the cell assembling circuit 43 ends the fetch of the 1-byte data of the tone data S2, and ends the assembling of the ATM cell S11. The ATM cell S11 including the 47-byte tone data thus assembled is output to the ATM switch within one cycle of the cell synchronization signal S10, triggered by the next valid edge of the cell synchronization signal S10.

As described above, the offset S13, which changes as X + 1, X + 2,... Output from the offset counter circuit 45, is given to the control memory 42. Since the period offset S8 is written in the load offset field, the value of the written offset is X
+47. Therefore, after the next valid edge of the same cell transmission cycle signal S3, when the read address S4 for the control memory 42 becomes the value # 0 again (when the supply of the next ATM cell of the same destination is instructed), This value X
+47 is loaded into the offset counter circuit 45. Thereby, continuity of the tone signal given to the telephone terminal is ensured.

FIGS. 6D to 6J show that the total data amount of the target tone data block is more than 47 bytes, and that the tone data of the last byte of the block is assembled in the present ATM cell assembly. The case where output is not required is shown. However, a block end code may be output during assembly. In this case, the block end code detection circuit 49 detects this and resets the offset counter circuit 45. Therefore, at this time, the tone data is output continuously from the first tone data byte of the tone data block.
It should be noted that the period until the offset counter circuit 45 is reset after the change to the offset S13 related to the block end code is very short. That is, after changing to the offset S13 related to the block end code, the above-described reset processing is performed before the tone data latch signal S12 becomes active for the first time. This ensures that even if the offset counter circuit 45 is reset halfway, the ATM cell S11 contains valid 47-byte tone data.

The operation when the read address S4 of the control memory 42 is fixed at a certain value # 0 as described above is as follows.
Each time the read address S4 changes within one cycle of the same cell transmission cycle signal S3, that is, 2048 times, the operation is repeated each time a valid edge of the same cell transmission cycle signal S3 occurs.

In this way, ATM cells having a maximum of 2,048 different headers can be supplied to the ATM switch. That is, a tone signal can be simultaneously supplied to a maximum of 2048 telephone terminals. Note that the same tone data may be included in the 2048 types of ATM cells, which means that the same tone signal is simultaneously supplied to a plurality of telephone terminals.

According to the above-described embodiment, the tone data is stored in the memory 41, and the reading of the tone data from the memory 41, which is to be inserted into the ATM cell, is performed as follows.
Using the control memory 42 within one ATM cell time, one cell assembling circuit 43 assembles ATM cells directly, and assembles a plurality of (2048) ATM cells within the same type of ATM cell transmission cycle. Since transmission is performed, a time switch is not required, and a large number of cell assembling circuits are not required, so that the tone supply device 40 can be made simple and small.

Since the same tone data can be included in a plurality of types of ATM cells, the same tone signal can be simultaneously supplied to a plurality of telephone terminals.

Furthermore, since the broadcast function (copy function) is not used, even a long tone signal such as a message tone signal can be promptly started to be supplied when required by the telephone terminal.

The memory does not need to be constituted by one chip. Further, the tone data memory 41 may be constituted by a RAM so that addition and change of tone types can be performed.

[0054]

As described above, according to the present invention, the tone data stored in the tone data memory and inserted into the ATM cell can be read out of the 1 ATM cell using the control memory. Perform in time, assemble ATM cells directly with a small number of cell assembly circuits,
Multiple types of ATM within the same type of ATM cell transmission cycle
Since the cells are assembled and transmitted, a simple and small tone supply device capable of simultaneously supplying the same tone signal to a plurality of telephone terminals can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment.

FIG. 2 is a block diagram showing a conventional configuration.

FIG. 3 is an explanatory diagram of a frame format of a time division highway of an ATM exchange.

FIG. 4 is an explanatory diagram of a format of an ATM cell.

FIG. 5 is a time chart showing an outline process of the embodiment.

FIG. 6 is a time chart of each part in FIG. 1;

[Explanation of symbols]

40: tone supply device, 41: tone data memory, 4
2 ... control memory, 43 ... cell assembly circuit, 44 ... address timing generator, 45 ... offset counter circuit, 4
6, 47 ... Latch circuit, 48 ... Addition circuit, 49 ... Block end code detection circuit.

Claims (1)

(57) [Claims] 1. A tone supply device in an ATM exchange, wherein tone data storage means for storing a plurality of types of tone data, an assembling state of tone data to be inserted into a payload of the ATM cell, and a header to be transmitted to the ATM cell. Control information storage means for managing a plurality of pieces of control information, which are tones to be output, within a cycle of transmitting an ATM cell having the same header, a header read from the control information storage means, and tone data; Assembling the ATM cell from the tone data read from the storage means
Cell assembling means for outputting to the TM switch; tone data read address forming means for forming a read address for the tone data storage means from the assembling state and tone type of the tone data read from the control information storage means; A tone control means for outputting one piece of control information from the control information storage means for each cell time, and timing control means for controlling the operation timing of the cell assembling means and the tone data read address forming means. Feeding device.