JP2663996B2 - ニューラル・ネットワーク用の仮想ニューロコンピュータ・アーキテクチュア - Google Patents

ニューラル・ネットワーク用の仮想ニューロコンピュータ・アーキテクチュア

Info

Publication number
JP2663996B2
JP2663996B2 JP3517778A JP51777891A JP2663996B2 JP 2663996 B2 JP2663996 B2 JP 2663996B2 JP 3517778 A JP3517778 A JP 3517778A JP 51777891 A JP51777891 A JP 51777891A JP 2663996 B2 JP2663996 B2 JP 2663996B2
Authority
JP
Japan
Prior art keywords
neuron
adder
communication
weight
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP3517778A
Other languages
English (en)
Japanese (ja)
Other versions
JPH04505824A (ja
Inventor
ピチャネック、ジェラルド、ジョージ
ヴァシリデイス、スタマテイス
デルガドーフライアズ、ホセ、グアダルーペ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/526,866 external-priority patent/US5065339A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH04505824A publication Critical patent/JPH04505824A/ja
Application granted granted Critical
Publication of JP2663996B2 publication Critical patent/JP2663996B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00Computing arrangements based on biological models
    • G06N3/02Neural networks
    • G06N3/10Interfaces, programming languages or software development kits, e.g. for simulating neural networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • General Health & Medical Sciences (AREA)
  • Mathematical Physics (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Molecular Biology (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Mining & Analysis (AREA)
  • Artificial Intelligence (AREA)
  • Neurology (AREA)
  • Devices For Executing Special Programs (AREA)
  • Multi Processors (AREA)
  • Feedback Control In General (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
JP3517778A 1990-05-22 1991-05-17 ニューラル・ネットワーク用の仮想ニューロコンピュータ・アーキテクチュア Expired - Fee Related JP2663996B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US526,866 1990-05-22
US07/526,866 US5065339A (en) 1990-05-22 1990-05-22 Orthogonal row-column neural processor
US68278691A 1991-04-08 1991-04-08
US682,786 1991-04-08

Publications (2)

Publication Number Publication Date
JPH04505824A JPH04505824A (ja) 1992-10-08
JP2663996B2 true JP2663996B2 (ja) 1997-10-15

Family

ID=27062243

Family Applications (4)

Application Number Title Priority Date Filing Date
JP3517778A Expired - Fee Related JP2663996B2 (ja) 1990-05-22 1991-05-17 ニューラル・ネットワーク用の仮想ニューロコンピュータ・アーキテクチュア
JP3510421A Expired - Fee Related JP2746350B2 (ja) 1990-05-22 1991-05-17 学習機械シナプス・プロセッサ・システム装置
JP3510818A Expired - Lifetime JP2502867B2 (ja) 1990-05-22 1991-05-17 Plan―ピラミッド型学習ア―キテクチャ・ニュ―ロコンピュ―タ
JP3509437A Expired - Fee Related JP2663995B2 (ja) 1990-05-22 1991-05-17 スケーラブル・フロー仮想学習ニューロコンピュータ

Family Applications After (3)

Application Number Title Priority Date Filing Date
JP3510421A Expired - Fee Related JP2746350B2 (ja) 1990-05-22 1991-05-17 学習機械シナプス・プロセッサ・システム装置
JP3510818A Expired - Lifetime JP2502867B2 (ja) 1990-05-22 1991-05-17 Plan―ピラミッド型学習ア―キテクチャ・ニュ―ロコンピュ―タ
JP3509437A Expired - Fee Related JP2663995B2 (ja) 1990-05-22 1991-05-17 スケーラブル・フロー仮想学習ニューロコンピュータ

Country Status (4)

Country Link
US (3) US5509106A (en:Method)
EP (4) EP0484506A1 (en:Method)
JP (4) JP2663996B2 (en:Method)
WO (4) WO1991018349A1 (en:Method)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2647327B2 (ja) * 1992-04-06 1997-08-27 インターナショナル・ビジネス・マシーンズ・コーポレイション 大規模並列コンピューティング・システム装置
JP2572522B2 (ja) * 1992-05-12 1997-01-16 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピューティング装置
US5517667A (en) * 1993-06-14 1996-05-14 Motorola, Inc. Neural network that does not require repetitive training
AU684214B2 (en) * 1994-09-07 1997-12-04 Motorola, Inc. System for recognizing spoken sounds from continuous speech and method of using same
US6128720A (en) * 1994-12-29 2000-10-03 International Business Machines Corporation Distributed processing array with component processors performing customized interpretation of instructions
US5659785A (en) * 1995-02-10 1997-08-19 International Business Machines Corporation Array processor communication architecture with broadcast processor instructions
US5799134A (en) * 1995-03-13 1998-08-25 Industrial Technology Research Institute One dimensional systolic array architecture for neural network
US6023753A (en) * 1997-06-30 2000-02-08 Billion Of Operations Per Second, Inc. Manifold array processor
US6167502A (en) * 1997-10-10 2000-12-26 Billions Of Operations Per Second, Inc. Method and apparatus for manifold array processing
WO1999033184A2 (en) * 1997-12-19 1999-07-01 Bae Systems Plc Binary code converters and comparators
US7254565B2 (en) * 2001-07-26 2007-08-07 International Business Machines Corporation Method and circuits to virtually increase the number of prototypes in artificial neural networks
JP3987782B2 (ja) * 2002-10-11 2007-10-10 Necエレクトロニクス株式会社 アレイ型プロセッサ
GB2400201A (en) * 2003-04-05 2004-10-06 Hewlett Packard Development Co Network modelling its own response to a requested action
US8443169B2 (en) * 2005-03-28 2013-05-14 Gerald George Pechanek Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processor
CN111291873A (zh) * 2014-07-21 2020-06-16 徐志强 预制性突触的模拟方法及装置
US9747546B2 (en) 2015-05-21 2017-08-29 Google Inc. Neural network processor
CN105512724B (zh) * 2015-12-01 2017-05-10 中国科学院计算技术研究所 加法器装置、数据累加方法及数据处理装置
WO2017200883A1 (en) 2016-05-17 2017-11-23 Silicon Storage Technology, Inc. Deep learning neural network classifier using non-volatile memory array
KR102459854B1 (ko) * 2016-05-26 2022-10-27 삼성전자주식회사 심층 신경망용 가속기
CN111310893B (zh) * 2016-08-05 2023-11-21 中科寒武纪科技股份有限公司 一种用于执行神经网络运算的装置及方法
US9946539B1 (en) 2017-05-23 2018-04-17 Google Llc Accessing data in multi-dimensional tensors using adders
US10534607B2 (en) 2017-05-23 2020-01-14 Google Llc Accessing data in multi-dimensional tensors using adders
US11461579B2 (en) 2018-02-08 2022-10-04 Western Digital Technologies, Inc. Configurable neural network engine for convolutional filter sizes
US11494620B2 (en) * 2018-02-08 2022-11-08 Western Digital Technologies, Inc. Systolic neural network engine capable of backpropagation
US10853034B2 (en) 2018-03-30 2020-12-01 Intel Corporation Common factor mass multiplication circuitry
JP6902000B2 (ja) * 2018-07-10 2021-07-14 株式会社東芝 演算装置
EP4009184A1 (en) * 2018-10-18 2022-06-08 Shanghai Cambricon Information Technology Co., Ltd Network-on-chip data processing method and device
CN109614876B (zh) * 2018-11-16 2021-07-27 北京市商汤科技开发有限公司 关键点检测方法及装置、电子设备和存储介质
CN109657788A (zh) * 2018-12-18 2019-04-19 北京中科寒武纪科技有限公司 数据处理方法、装置及相关产品
US11500442B2 (en) 2019-01-18 2022-11-15 Silicon Storage Technology, Inc. System for converting neuron current into neuron current-based time pulses in an analog neural memory in a deep learning artificial neural network
US11270763B2 (en) 2019-01-18 2022-03-08 Silicon Storage Technology, Inc. Neural network classifier using array of three-gate non-volatile memory cells
US11023559B2 (en) 2019-01-25 2021-06-01 Microsemi Soc Corp. Apparatus and method for combining analog neural net with FPGA routing in a monolithic integrated circuit
US11270771B2 (en) 2019-01-29 2022-03-08 Silicon Storage Technology, Inc. Neural network classifier using array of stacked gate non-volatile memory cells
US10929058B2 (en) 2019-03-25 2021-02-23 Western Digital Technologies, Inc. Enhanced memory device architecture for machine learning
US11783176B2 (en) 2019-03-25 2023-10-10 Western Digital Technologies, Inc. Enhanced storage device memory architecture for machine learning
US11423979B2 (en) 2019-04-29 2022-08-23 Silicon Storage Technology, Inc. Decoding system and physical layout for analog neural memory in deep learning artificial neural network
CN115943377A (zh) * 2020-06-12 2023-04-07 高通股份有限公司 利用联邦学习来训练用户认证模型
US12400108B2 (en) 2021-06-17 2025-08-26 Samsung Electronics Co., Ltd. Mixed-precision neural network accelerator tile with lattice fusion

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4796199A (en) * 1987-02-24 1989-01-03 Oregon Graduate Center Neural-model, information-handling architecture and method
US4858147A (en) * 1987-06-15 1989-08-15 Unisys Corporation Special purpose neurocomputer system for solving optimization problems
US5014235A (en) * 1987-12-15 1991-05-07 Steven G. Morton Convolution memory
FR2625347B1 (fr) * 1987-12-23 1990-05-04 Labo Electronique Physique Structure de reseau de neurones et circuit et arrangement de reseaux de neurones
US4953099A (en) * 1988-06-07 1990-08-28 Massachusetts Institute Of Technology Information discrimination cell
DE58906476D1 (de) * 1988-07-05 1994-02-03 Siemens Ag In integrierter Schaltungstechnik ausgeführtes digitales neuronales Netz.
GB2224139A (en) * 1988-10-24 1990-04-25 Philips Electronic Associated Digital data processing apparatus
FR2639461A1 (fr) * 1988-11-18 1990-05-25 Labo Electronique Physique Arrangement bidimensionnel de points memoire et structure de reseaux de neurones utilisant un tel arrangement
DE68927474T2 (de) * 1988-12-29 1997-05-22 Sharp Kk Neuro-Rechner
JPH02287670A (ja) * 1989-04-27 1990-11-27 Mitsubishi Electric Corp 半導体神経回路網
US5148514A (en) * 1989-05-15 1992-09-15 Mitsubishi Denki Kabushiki Kaisha Neural network integrated circuit device having self-organizing function
JP2517410B2 (ja) * 1989-05-15 1996-07-24 三菱電機株式会社 学習機能付集積回路装置
US5148515A (en) * 1990-05-22 1992-09-15 International Business Machines Corp. Scalable neural array processor and method
US5243688A (en) * 1990-05-22 1993-09-07 International Business Machines Corporation Virtual neurocomputer architectures for neural networks

Also Published As

Publication number Publication date
WO1991018349A1 (en) 1991-11-28
EP0484506A4 (en:Method) 1994-03-23
US5542026A (en) 1996-07-30
JP2746350B2 (ja) 1998-05-06
EP0486684A1 (en) 1992-05-27
EP0486635A4 (en:Method) 1994-03-23
JP2663995B2 (ja) 1997-10-15
JPH04507027A (ja) 1992-12-03
JPH04507026A (ja) 1992-12-03
EP0484506A1 (en) 1992-05-13
JPH05500429A (ja) 1993-01-28
EP0486684A4 (en:Method) 1994-03-23
JP2502867B2 (ja) 1996-05-29
EP0484522A1 (en) 1992-05-13
WO1992001257A1 (en) 1992-01-23
EP0484522A4 (en:Method) 1994-03-23
WO1991018350A1 (en) 1991-11-28
EP0486635A1 (en) 1992-05-27
JPH04505824A (ja) 1992-10-08
US5617512A (en) 1997-04-01
WO1991018351A1 (en) 1991-11-28
US5509106A (en) 1996-04-16

Similar Documents

Publication Publication Date Title
JP2663996B2 (ja) ニューラル・ネットワーク用の仮想ニューロコンピュータ・アーキテクチュア
US5146543A (en) Scalable neural array processor
US5065339A (en) Orthogonal row-column neural processor
US5148515A (en) Scalable neural array processor and method
US5517596A (en) Learning machine synapse processor system apparatus
KR20160111795A (ko) 인공 신경망의 뉴로모픽 하드웨어 구현 방법
Lehmann et al. A generic systolic array building block for neural networks with on-chip learning
US5243688A (en) Virtual neurocomputer architectures for neural networks
US5640586A (en) Scalable parallel group partitioned diagonal-fold switching tree computing apparatus
US5146420A (en) Communicating adder tree system for neural array processor
JPH07210534A (ja) ニューラルネットワーク
Lehmann et al. A VLSI implementation of a generic systolic synaptic building block for neural networks
US20220027712A1 (en) Neural mosaic logic unit
US20210142153A1 (en) Resistive processing unit scalable execution
Myers et al. HANNIBAL: A VLSI building block for neural networks with on-chip backpropagation learning
Misra et al. Implementation of Sparse Neural Networks on Fixed Size Arrays
Delgado-Frias et al. A VLSI pipelined neuroemulator
Nagrani et al. Neural Network Architectures for Integrated Circuits
JPH02287862A (ja) ニューラルネットワーク演算装置
Solheim et al. RENNS-a reconfigurable computer system for artificial neural networks
Faure et al. A cellular architecture dedicated to neural net emulation
Krikelis et al. Implementing neural networks with the associative string processor
Malhotra et al. Evaluation of electronic artificial neural network implementations
Myers et al. A VLSI ARCHITECTURE FOR IMPLEMENTING NEURAL NETWORKS WITH ON-CHIP BACKPROPAGATION
Kechriotis et al. Training fully recurrent neural networks on a ring transputer array

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees