CN105512724B - 加法器装置、数据累加方法及数据处理装置 - Google Patents
加法器装置、数据累加方法及数据处理装置 Download PDFInfo
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- CN105512724B CN105512724B CN201510863726.2A CN201510863726A CN105512724B CN 105512724 B CN105512724 B CN 105512724B CN 201510863726 A CN201510863726 A CN 201510863726A CN 105512724 B CN105512724 B CN 105512724B
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- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
- G06F7/509—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination for multiple operands, e.g. digital integrators
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- G06N3/00—Computing arrangements based on biological models
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- G06N5/01—Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
- G06F2207/4802—Special implementations
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
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Abstract
Description
Claims (10)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510863726.2A CN105512724B (zh) | 2015-12-01 | 2015-12-01 | 加法器装置、数据累加方法及数据处理装置 |
PCT/CN2016/086110 WO2017092284A1 (zh) | 2015-12-01 | 2016-06-17 | 加法器装置、数据累加方法及数据处理装置 |
US15/773,974 US10416964B2 (en) | 2015-12-01 | 2016-06-17 | Adder device, data accumulation method and data processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN201510863726.2A CN105512724B (zh) | 2015-12-01 | 2015-12-01 | 加法器装置、数据累加方法及数据处理装置 |
Publications (2)
Publication Number | Publication Date |
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CN105512724A CN105512724A (zh) | 2016-04-20 |
CN105512724B true CN105512724B (zh) | 2017-05-10 |
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CN201510863726.2A Active CN105512724B (zh) | 2015-12-01 | 2015-12-01 | 加法器装置、数据累加方法及数据处理装置 |
Country Status (3)
Country | Link |
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US (1) | US10416964B2 (zh) |
CN (1) | CN105512724B (zh) |
WO (1) | WO2017092284A1 (zh) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105512724B (zh) * | 2015-12-01 | 2017-05-10 | 中国科学院计算技术研究所 | 加法器装置、数据累加方法及数据处理装置 |
CN105630733B (zh) * | 2015-12-24 | 2017-05-03 | 中国科学院计算技术研究所 | 分形树中向量数据回传处理单元的装置、方法、控制装置及智能芯片 |
CN106873940B (zh) * | 2016-12-30 | 2019-05-17 | 青岛专用集成电路设计工程技术研究中心 | 一种定点加法结果位宽限制的处理方法和装置 |
WO2018192500A1 (zh) * | 2017-04-19 | 2018-10-25 | 上海寒武纪信息科技有限公司 | 处理装置和处理方法 |
CN110275693B (zh) * | 2018-03-15 | 2023-08-22 | 华为技术有限公司 | 用于随机计算的多加数加法电路 |
CN108549933A (zh) * | 2018-04-23 | 2018-09-18 | 北京旷视科技有限公司 | 一种数据处理方法、装置、电子设备和计算机可读介质 |
CN109146059A (zh) * | 2018-08-03 | 2019-01-04 | 济南浪潮高新科技投资发展有限公司 | 一种卷积数据处理电路及数据处理方法 |
KR20200026455A (ko) * | 2018-09-03 | 2020-03-11 | 삼성전자주식회사 | 인공 신경망 시스템 및 인공 신경망의 고정 소수점 제어 방법 |
CN110427171B (zh) * | 2019-08-09 | 2022-10-18 | 复旦大学 | 可扩展的定点数矩阵乘加运算的存内计算设备和方法 |
CN111753962B (zh) * | 2020-06-24 | 2023-07-11 | 国汽(北京)智能网联汽车研究院有限公司 | 一种加法器、乘法器、卷积层结构、处理器及加速器 |
US20220253282A1 (en) * | 2021-02-11 | 2022-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | New low power adder tree structure |
CN113283251B (zh) * | 2021-06-11 | 2023-05-30 | 西安微电子技术研究所 | 一种基于二维流水线的n邻域累加/或的运算装置 |
CN114200822A (zh) * | 2021-12-09 | 2022-03-18 | 常州同惠电子股份有限公司 | 全精度数字积分控制器的fpga实现方法 |
CN114937470B (zh) * | 2022-05-20 | 2023-04-07 | 电子科技大学 | 基于多比特sram单元的定点全精度存内计算电路 |
Citations (2)
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CN1801082A (zh) * | 1995-08-31 | 2006-07-12 | 英特尔公司 | 在分组数据上执行乘-加运算的装置 |
CN103279322A (zh) * | 2013-06-13 | 2013-09-04 | 福州大学 | Set/mos混合电路构成的阈值逻辑型超前进位加法器 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3515344A (en) * | 1966-08-31 | 1970-06-02 | Ibm | Apparatus for accumulating the sum of a plurality of operands |
DE58906476D1 (de) * | 1988-07-05 | 1994-02-03 | Siemens Ag | In integrierter Schaltungstechnik ausgeführtes digitales neuronales Netz. |
JP2746350B2 (ja) * | 1990-05-22 | 1998-05-06 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 学習機械シナプス・プロセッサ・システム装置 |
US8442927B2 (en) * | 2009-07-30 | 2013-05-14 | Nec Laboratories America, Inc. | Dynamically configurable, multi-ported co-processor for convolutional neural networks |
KR102072543B1 (ko) * | 2013-01-28 | 2020-02-03 | 삼성전자 주식회사 | 복수 데이터 형식을 지원하는 가산기 및 그 가산기를 이용한 복수 데이터 형식의 가감 연산 지원 방법 |
CN104090737B (zh) * | 2014-07-04 | 2017-04-05 | 东南大学 | 一种改进型部分并行架构乘法器及其处理方法 |
CN105512724B (zh) * | 2015-12-01 | 2017-05-10 | 中国科学院计算技术研究所 | 加法器装置、数据累加方法及数据处理装置 |
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2015
- 2015-12-01 CN CN201510863726.2A patent/CN105512724B/zh active Active
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2016
- 2016-06-17 WO PCT/CN2016/086110 patent/WO2017092284A1/zh active Application Filing
- 2016-06-17 US US15/773,974 patent/US10416964B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1801082A (zh) * | 1995-08-31 | 2006-07-12 | 英特尔公司 | 在分组数据上执行乘-加运算的装置 |
CN103279322A (zh) * | 2013-06-13 | 2013-09-04 | 福州大学 | Set/mos混合电路构成的阈值逻辑型超前进位加法器 |
Also Published As
Publication number | Publication date |
---|---|
US20180321911A1 (en) | 2018-11-08 |
US10416964B2 (en) | 2019-09-17 |
WO2017092284A1 (zh) | 2017-06-08 |
CN105512724A (zh) | 2016-04-20 |
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Inventor after: Zhou Longyuan Inventor after: Li Zhen Inventor after: Liu Shaoli Inventor after: Zhang Shijin Inventor after: Luo Tao Inventor after: Qian Cheng Inventor after: Chen Yunji Inventor after: Chen Tianshi Inventor before: Li Zhen Inventor before: Liu Shaoli Inventor before: Zhang Shijin Inventor before: Luo Tao Inventor before: Qian Cheng Inventor before: Chen Yunji Inventor before: Chen Tianshi |