JP2663135B2 - Integrated circuit test equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electron beam test apparatus for performing a failure diagnosis of an integrated circuit at high speed and in detail.

[Conventional technology]

One of the testing methods for an integrated circuit using an electron beam test apparatus is a method using a failure image. The failure image is an image obtained as a result of a difference between image data obtained from the integrated circuit sample to be tested by the electron beam test apparatus and image data which is separately prepared in advance and is normal. Since the state of the failure can be observed at a glance on this image, the failure location can be easily and easily specified by tracking the temporal change of the state.

Such testing methods are broadly divided into dynamic fault images (DFI: see, eg, TCMay et al., “Dynam
ic Fault Imaging of VLSI Random Logic Decices ", 198
4 A method using IEEE / IRPS pp.95-108) and a method using a fault contrast image (FCI such as Alan R. Stivers at al.,
“Fault Contrast: A New Voltage Contrast VLSI Diagn
osis Technique ", 1986 IEEE / IRPS pp.109-114), and the outline is shown in Figs. 5 (a) and 5 (b).
Shown in FIG. 5 (a) shows the generation of a dynamic fault image, and FIG. 5 (b) shows the generation of a fault contrast image. In the former, the integrated circuit under test as the device under test
51 and a non-defective integrated circuit 52 as a non-defective device are prepared, and image data is fetched from both under the same operating condition, and a difference image is obtained to obtain a failure image. 53 is the same test parameter, 54 and 55 are observation images, 56 is a difference circuit, 57 is a dynamic fault image, and 58 is a fault cube.

On the other hand, the latter is applied to a device that has been confirmed to operate normally under specific test parameter conditions, and one of the integrated circuits under test 511 of the same device is, for example, 512 under the normal operation condition. Observed images 514 and 515 are obtained with test parameter 1 and another with test parameter 2 of 513 under a condition in which normal operation is not performed, a difference is obtained by a difference circuit 516, and a fault contrast image is obtained as a failure image.
Get 517. This method has a failure mode limited to only marginal ones, but has the advantage that alignment and distortion correction between images are not required in image difference processing.

As a method of failure tracking using DFI, there is a method using a fault cube 58 as shown in FIG. 5 (a).
The fault cube is a three-dimensional image of fault images arranged in the time direction and visually observing how the fault pattern expands with time, and by finding the starting point, the fault location is specified. .

FIGS. 6A and 6B show a failure tracking method in the case of FCI. Reference numeral 60 denotes an integrated circuit chip. When a fault is detected through the output pad 61, the fault pattern 63 on the integrated circuit sample is traced while moving in the fault image observation zone 62 at the timing (t = n) ( FIG. 6 (a)). When the starting point of the fault pattern propagation is reached, the test pattern is stopped at the immediately preceding test pattern timing (t = n-1), and the sample is manually traced again to search for the starting point of the fault propagation (FIG. 6). (B)). Thus, when the timing at which the failure pattern no longer occurs is reached, the starting point of the finally reached failure is determined to be a true failure portion. Even in the case of DFI, this method is often used eventually. This is because there is no guarantee that the failure pattern will spread out clearly from one point so that it can be intuitively understood, and it depends on the timing of taking image data. Because it is a target.

[Problems to be solved by the invention]

In the tracking method shown in FIG. 6, since it is necessary to capture an image with an accuracy capable of recognizing a wiring pattern, it is difficult to increase the observation zone so as to cover the entire integrated circuit sample due to the limitation of the number of pixels. Therefore, for example, by capturing a failure image in a local zone of 1 mm × 1 mm and tracking the failure pattern, every time a failure image is captured, the signal propagation direction on the failure wiring pattern and the signal between the failure wiring patterns are It is necessary to check the propagation order. However, the conventional method merely provides a means for observing a fault image, and all the work required for tracking these has to be performed manually. Specific tasks include the correspondence between a faulty wiring pattern and a design wiring pattern, the correspondence between a wiring pattern and a circuit diagram, and the tracking of the structure of a circuit diagram. A lot of time and labor-intensive work such as tracking the mask pattern diagram and comparing it with the observed image was required, and these were major factors that made it difficult to apply this method to large-scale integrated circuits.

It has been pointed out that it is necessary to use design data in some form in order to solve such a problem. However, with normal design data, there is no link between the wiring pattern and the circuit diagram to refer to each other, so a map for tracking cannot be created, making tracking easier. It was impossible.

SUMMARY OF THE INVENTION An object of the present invention is to solve the problem that a conventional test apparatus does not have a means for giving a guide regarding a fault tracking direction, and an object of the present invention is to increase the speed and efficiency of fault tracking.

[Means for explaining the task]

In order to achieve the above object, the integrated circuit test apparatus of the present invention scans a fixed area on an integrated circuit sample placed in an operating state with an electron beam, and performs secondary electron imaging at one or more timings. Take out the secondary electron image taken out, and obtain a difference image between the non-defective sample or the same sample under normal operating conditions or an image obtained from the design data, and detect a difference failure pattern from the difference image. Reading a design wiring pattern corresponding to a failure pattern that becomes a difference that appears in the difference image from design wiring pattern data, reading a logical depth of the design wiring pattern read from the design wiring pattern data from design circuit data, A collection of read end points (signal starting points) on the wiring directly connected to the output terminals of the logic cells of the design wiring pattern read from the design wiring pattern data from the design wiring pattern data In the circuit testing apparatus, and characterized in that it comprises means for displaying impart direction of the logical depth and signal propagation on the design wiring pattern.

(Operation)

The device according to the present invention is different from the conventional device in which the failure image (DFI or FCI) is simply observed and displayed, and information which is a clue for determining a direction to be tracked can be displayed corresponding to the failure image. Therefore, the apparatus according to the present invention can determine the most efficient fault tracking procedure while always referring to the search map in the form of the logical depth and the signal propagation direction. Hereinafter, embodiments will be described with reference to the drawings.

〔Example〕

FIG. 1 shows an embodiment of the present invention. An integrated circuit under test 3 is mounted on an XY stage 2 of the electron beam test apparatus 1. An electron beam 4 is irradiated thereon, and a secondary electron signal generated from the surface is extracted in the form of an image. The movement of the observation zone is performed by moving the XY stage 2 indicating the stage position information 2XY. The failure image generation circuit 6 calculates the difference between the observation image of the sample of the integrated circuit under test 3 obtained from the electron beam test apparatus 1 and the normal operation state image for reference stored in the reference image memory circuit 5 in advance. The processing is performed, and a failure image is generated and displayed on the failure image display unit 7.

On the other hand, a corresponding failure search map is generated and displayed in the following procedure.

1) The failure pattern identification circuit 70 identifies the length, the coordinates of the end point, etc. of the failure pattern on the observed failure image as shape parameters.

2) Circuit data 81 as design data, data 82 as a design wiring pattern, and a cross reference 83 indicating the correspondence between the two are stored in the memory circuit 8. The cross-reference 83 can be easily generated by using a design database having a mechanism such that a link exists between the circuit diagram and the wiring pattern so that the link can be referred to each other. Kuji et al., “FINDER: A CAD Syste
m-based Electron Beam Teester for Fault Diagnosis
of VLSI Circuits ", IEEE Trans.CAD, April 1986, Vol C
AD-5, Number 2, pp-313-319).

3) Based on the shape parameter of the fault pattern obtained in 1), the wiring data of the corresponding design wiring pattern is selectively read out of the eight memory circuits 1 and the recognition result by the design wiring recognition unit 80 is stored in the memory of nine. Accumulate in circuit 2.

4) The circuit net corresponding to this wiring is obtained by referring to the cross reference 83.

5) The logical depth reading circuit 10 reads the "logical depth" of the circuit net obtained in 4) and the position of the output terminal of the logic cell with respect to this net, and accumulates them at the logical depth output terminal coordinates of the memory circuit 11. "Logical depth" is the number of circuit nets that pass through the circuit when it reaches the circuit net from the primary input terminal of the entire circuit or circuit block, assuming a predetermined path on the circuit diagram.

6) The logical depth, wiring data, and output terminal coordinates are read out from the nine memory circuits 2 and 11 and the signal direction on the wiring pattern is obtained from these data, and the wiring pattern, signal output starting point, A search map including the signal propagation direction is displayed on a search map display unit.

FIGS. 2A to 2C show an embodiment in which the design wiring corresponding to the failure pattern is recognized. FIG. 2A shows an example of a failure image 200, and reference numeral 20 denotes an observed failure wiring pattern.
The faulty wiring pattern 20 is binarized with an appropriate threshold, and the position and line length of the end point 21 of the pattern are obtained as feature parameters. The position of one point on the wiring on the corresponding design coordinates is obtained by reading the coordinates of the XY stage,
The search range is determined centering on that point, and the wiring pattern included therein is found. If this search range is larger than the positioning accuracy of the XY stage, it should be included in the corresponding wiring pattern. FIG. 2B shows the corresponding design wiring pattern 201 obtained in the wiring pattern search range 22 in this manner. Which of the design wiring patterns 201 corresponds to the failure pattern can be determined based on the characteristic parameter of the failure pattern. As a result, the corresponding design wiring 202 selected as shown in FIG. 2C is selected.

FIGS. 3A and 3B show an embodiment of a search map. FIG. 3 (a) shows an example of a logical depth 300 obtained on a circuit diagram. The logical depth is obtained in accordance with the number of stages of the circuit net counted from the primary input. , 32,33,34. On the other hand, FIG. 3B shows a display example 301 of a search map, in which arrows 311 of each wiring are signal propagation directions of a wiring pattern 312, and numerals 31, 32, 33, and 34 are numbers of circuit nets corresponding to the wiring. Represents the logical depth, with smaller numbers indicating closer to the true failure point. 313 indicates a logic cell, and 314 indicates a signal output starting point.

FIGS. 4 (a) and 4 (b) show an embodiment of a test procedure performed using the apparatus according to the present invention based on the above search map display. FIG. 4 (a) shows a circuit diagram of the circuit under test, and numerals 41, 42, 43, 44 and 45 are logical depths. FIG. 4 (b) shows the failure tracking processes I, II, III, and IV. A search map 400 is shown on the left, and a failure image 401 on the integrated circuit sample is shown on the right. 402 is a failure image observation zone, 403 is a failure pattern, 411 is a signal output terminal, 412 is a design wiring pattern, 413
Is an observation zone. The search direction of the right failure image is determined with reference to the left search map 400, and the tracking is advanced to the true failure point. Usually, observation starts from the pad connected to the external terminal, and proceeds to the internal circuit. It is assumed that the timing of the test pattern at which observation has started is t = n (process I). The design wiring pattern corresponding to the failure pattern on the first failure image is
It is automatically identified by the method shown in FIG. The information necessary for such identification may be determined by a human and input interactively, or may be automatically extracted by image processing technology. For the corresponding wiring identified on the search map, a number indicating a signal propagation direction indicated by an arrow on the wiring and a logical depth between the wirings is displayed. From these, the one with the smallest logical depth is selected, the search direction is determined so as to trace the signal propagation direction, and the observation zone 413 may be moved. The tracking of such a planar failure pattern ends when the one with a smaller logical depth no longer appears (Process I).
I). Such tracking can be performed easily if the field size of the observation zone is 1 mm x 1 mm. Next, the timing of the test pattern is set back to a predetermined number of patterns, the timing t = n-1 (process III), and a failure pattern is searched for in the same manner. Tracking is performed by finding a failure pattern with the smallest logical depth, and a starting point of the failure at this timing t = n-1 is searched (process IV). Further, the same process is repeated with the timing of the test pattern traced back, and when the failure pattern no longer appears on the failure image, the search in the timing direction is terminated, and the failure origin obtained immediately before is the true failure occurrence point. Is required.

As described above, the device according to the present invention has a logical depth and a lower depth than the conventional device that performs fault tracking by groping.
A significant improvement has been made in that the most efficient fault tracking procedure can be determined while always referring to a search map in the form of signal propagation directions.

〔The invention's effect〕

As described above, the present invention has the following effects when tracing a failure image by providing means for specifying a search procedure based on design data.

1) There is no need to manually refer to the mask pattern, the circuit diagram, and the relationship between the two, and the labor involved in tracking is greatly reduced.

2) Since the tracking procedure is optimized, the number of times of processing the image data is minimized, and the time required for the test is greatly reduced.

3) Since the tracking procedure is specified, the test procedure is routineized, and even a person who does not have the design knowledge of the integrated circuit under test can perform the test in a short time.

[Brief description of the drawings]

FIG. 1 is a view for explaining the apparatus of the present invention, FIGS. 2 (a) to 2 (c) are views for explaining an embodiment of recognition of a design wiring pattern corresponding to a failure pattern, and FIGS. 3 (a) and 3 (b). FIGS. 4 (a) and 4 (b) are diagrams illustrating an example of a test procedure in the apparatus of the present invention, and FIGS.
6 (a) and 6 (b) are diagrams for explaining a conventional technique, and FIGS. 6 (a) and 6 (b) are diagrams for explaining a fault tracking method using a fault contrast image. 1 ... Electron beam test equipment, 2 ... XY stage, 3 ...
Integrated circuit under test, 4 ... Electron beam, 5 ... Reference image memory circuit, 6 ... Fault image generation circuit, 7 ... Fault image display section, 70 ... Fault pattern identification circuit, 8 ... Memory circuit 1 ,
81 …… Design circuit data, 82 …… Design wiring pattern data,
83 ... Cross reference, 80 ... Design wiring recognition part, 9
…… Memory circuit 2, 10 …… Logic depth reading circuit, 11…
... memory circuits 3, 12 ... search map display unit, 200 ... failure image, 201 ... design wiring pattern, 202 ... selected corresponding design wiring, 20 ... failure wiring pattern, 21 ... end point, 22 ... ... Search range of wiring pattern, 300 ... Example of logical depth, 301 ... Display example of search map, 31-34, 41-45 ... Logic depth, 311 ...
Signal propagation direction, 312 ... wiring pattern, 313 ... logic cell,
314: Signal output start point, 400: Search diagram, 401: Failure image on integrated circuit sample, 402: Failure image observation zone, 403 ...
Failure pattern, 411: Signal output terminal, 412: Design wiring pattern, 413: Observation zone, 51, 511: Integrated circuit under test, 52: Non-defective integrated circuit, 53: Same test parameter, 54, 55 ... Observation image, 56,516… Difference circuit, 57… Dynamic fault image, 58… Fault cube,
512: Test parameter 1, 513: Test parameter 2, 514, 515: Observed image, 517: Photo contrast image, 60: Integrated circuit chip, 61: Output pad, 62 ...
Failure image observation zone, 63 ... Failure pattern

Claims (1)

(57) [Claims] 1. A fixed area on an integrated circuit sample placed in an operating state is scanned by an electron beam, and a secondary electron image is taken out at one or more timings. Obtain a difference image between a good sample or an image obtained from the same sample or design data under normal operating conditions, detect a failure pattern that is a difference from the difference image, and obtain a difference that appears in the difference image. The design wiring pattern corresponding to the failure pattern is read from the design wiring pattern data, the logical depth of the design wiring pattern read from the design wiring pattern data is read from the design circuit data, and the design wiring pattern read from the design wiring pattern data is In an integrated circuit test apparatus for reading an end point (signal starting point) on a wiring directly connected to an output terminal of a cell from design wiring pattern data, An integrated circuit test apparatus comprising: means for giving a direction of signal propagation to the design wiring pattern and displaying the design wiring pattern.