JP2662458B2 - LCD segment drive circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a segment drive circuit for an LCD (Liquid Crystal Display).

[Prior Art] A plurality of segment driving LSIs (segment drivers) for driving a plurality of segment electrodes of an LCD, respectively
Is connected. In this case, the active control of the capture of the display data in each segment driver is performed by an enable signal input by cascade connection, or the active state is sequentially set by a built-in counter circuit.

In the former active control based on the enable signal, the enable signal is output when the cascade-connected segment driver of the preceding stage has completed the operation of fetching the display data, and the segment driver of the next stage operates by the enable signal from the previous stage. To start.

In the latter active control by the counter circuit, a select code number is set in advance using a plurality of input terminals for each segment driver, and each select code number is compared with the count value of the counter circuit. Then, control is performed so that the segment driver that matches the two starts the operation of fetching the display data.

[Problems to be Solved by the Invention] However, according to the above-described active control in which the fetch operation of the display data is controlled only by the enable signal from the preceding stage connected in cascade, the signal transmission delay time between the segment drivers is reduced. Since the clock pulse period is so large that it cannot be ignored, the upper limit of the operating speed of the segment driver is limited.

Further, according to the above-described active control by the counter circuit, there is a disadvantage that a plurality of extra input terminals are required to set the select code number of each segment driver.

Accordingly, the present invention provides a segment drive circuit which is not affected by the signal transmission delay time between the segment drive circuits and does not involve an increase in the number of input terminals.

[Means for Solving the Problems] According to the present invention, a segment driving circuit connected in multiple stages to drive a plurality of segment electrodes of an LCD respectively generates a carry signal every predetermined period. Means for generating a standby signal indicating a standby state when an enable signal is applied from a preceding stage; a display data fetch signal and an enable signal for a next stage in response to the generated standby signal and a carry signal from the counting means And means for generating

[Operation] The counting means generates a carry signal every time a predetermined number of clock pulses are counted. On the other hand, when the enable signal is applied from the preceding segment drive circuit, the standby signal is set. When the carry signal is generated while the standby signal is set, the generation of the display data capture signal is started. , An enable signal to be sent to the next segment drive circuit is generated.

Embodiment An embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a segment driving circuit according to an embodiment of the present invention, that is, a segment driving LSI (segment driver).
2 is a partial circuit diagram, and FIG. 2 is a partial time chart of the segment drive circuit shown in FIG. The circuit shown in FIG. 1 shows an active control circuit for generating a signal for fetching display data in a segment driver. The configuration of the other parts of the segment driver is well known, and therefore, the description is omitted. Actually, a plurality of such segment drivers are prepared for driving a plurality of segment electrodes of an LCD (not shown), respectively, and are connected in multiple stages.

As shown in FIG. 1, the active control circuit of the segment driver mainly includes an active control unit 10, an enable signal generation unit 20, and a counter unit 30.

The active control unit 10 includes four latches L1 to L4, three inverters INV1 to INV3, two NAND gates NAND1 and NAND2, and a NOR gate NOR1. Based on the enable signal EI, a signal CKSTART for instructing the start of capture of display data of the segment driver and a signal CKSTOP for instructing termination of capture of display data are generated.
Each of the latches L1 to L4 is configured by cross-connecting two negative logic NOR gates.

The enable signal E1 applied from the preceding segment driver is applied to one input terminal of the latch L1 via the inverter INV1.
CL1 is connected to one input terminal of NOR gate NOR1 and inverter INV
It is configured to be applied to two input terminals. The output terminal of the inverter INV2 is connected to one input terminal of the latches L2, L3, and L4. The standby signal ST obtained from the output terminal of the latch L1 is configured to be applied to one input terminal of the NAND gate NAND1, and the output terminal of the NAND gate NAND1 is connected to the other input terminal of the latch L2. The display data capture start signal CKSTART is output from the output terminal of the latch L2. The output terminal of the latch L3 is connected to one input terminal of the NAND gate NAND2, and the output terminal of the NAND gate NAND2 is connected to the other input terminal of the latch L4. The display data capture end signal CKSTOP is output from the output terminal of the latch L4. The above-described inverter INV1 and latch L1 correspond to the means for generating a standby signal in the present invention.

The enable signal generator 20 mainly includes a D flip-flop DFF and an AND gate AND1. The output terminal of the NAND gate NAND1 of the active control unit 10 is connected to the input terminal of the inverter INV4. Carry signal CA and standby signal are output from the output terminal of this inverter INV4.
The signal CA · ST of the logical product with ST is applied to the D input terminal of the D flip-flop DFF. The D flip-flop DFF is configured so that an enable signal EO to be sent to the next segment driver is output from its Q output terminal. This Q output terminal is connected to the other input terminal of the NOR gate NOR1 of the active control unit 10 and the input terminal of the inverter INV3. Inverter
The output terminal of INV3 is connected to the other input terminal of latch L3, and the output terminal of NOR gate NOR1 is connected to the other input terminal of latch L1. The output terminal of the inverter INV2 of the active control unit 10 is further provided with a D flip-flop.
It is connected to the input terminal of the reset signal R of DFF. A clock pulse CL2, a display data capture start signal CKSTART, and a display data capture end signal CKSTOP are applied to three input terminals of the AND gate AND1 of the enable signal generator 20. The signal ACK output from the output terminal of the AND gate AND1 is further applied to the clock pulse CK input terminal of the D flip-flop DFF. The above-mentioned NAND gate NA
The ND1 and NAND2, the latches L2 and L4, the inverter INV4, and the enable signal generator 20 correspond to the means for generating the display data fetch signal and the next-stage enable signal in the present invention.

The counter unit 30 has four T flip-flops TFF1 to TFF4
, Three AND gates AND2, AND3, and AND4, and a four-input NOR gate NOR2. Note that the counter section 30 corresponds to the counting means in the present invention.

The display data capture end signal CKSTOP is applied to one input terminal of the AND gate AND2, and the clock pulse CL2 is applied to the other input terminal. The output terminal of the AND gate AND2 is connected to the input terminal of the clock pulse CK of each of the T flip-flops TFF1 to TFF4. Each of the flip-flops TFF1 to TFF4 is configured such that a latch pulse CL1 is applied to an input terminal of the reset pulse R. The T input terminal of the T flip-flop TFF1 is pulled up by the power supply voltage. The Q output terminal of the T flip-flop TFF1 is connected to the T input terminal of the T flip-flop TFF2 and the NOR gate.
It is connected to a first input terminal of NOR2 and one input terminal of AND gate AND3. The Q output terminal of the T flip-flop TFF2 is connected to the second input terminal of the NOR gate NOR2 and the other input terminal of the AND gate AND3. The output terminal of the AND gate AND3 is connected to the T input terminal of the T flip-flop TFF3 and one input terminal of the AND gate AND4. The Q output terminal of the T flip-flop TFF3 is connected to the third input terminal of the NOR gate NOR2 and the other input terminal of the AND gate AND4. The output terminal of the AND gate AND4 is a T flip-flop TFF4
Of the T flip-flop TF
The Q output terminal of F4 is connected to the fourth input terminal of NOR gate NOR2. The carry signal CA is output from the output terminal of the NOR gate NOR2, and is applied to the other input terminals of the NAND gates NAND1 and NAND2 of the active control unit 10.

 Next, the operation of this embodiment will be described with reference to FIG.

First, in the counter unit 30, as described above, each T flip-flop T is generated by the latch pulse CL1 (see FIG.
FF1 to TFF4 are reset and the falling edge of the clock CL2 (see FIG. 8B) is counted, and 16 clock pulses are counted.
Carry signal CA every time CL2 is counted (see (D) in the figure)
Is output.

In the active control unit 10, the standby signal ST (see FIG. 9E) from the latch L1 is reset by the latch pulse CL1 and is reset by an enable signal EI (see FIG. 9C) sent next from the preceding segment driver. Set.

When the carry signal CA is applied in a state where the standby signal ST is set, the latch L2 is set, and the display data capture start signal CKSTART (see (G) in the figure) is output (high level). In this state, the latches L3 and L4 have been reset by the latch pulse CL1 but have not been set by the enable signal EO (see (H) in the same figure).
CKSTOP (see FIG. 1I) is not output (it remains at high level).

Therefore, the clock pulse CL2 is output to the enable signal generator 2
The signal passes through the AND gate AND1 of 0, and its output becomes the display data capture signal ACK (see FIG. 10 (J)). This signal ACK is also applied as a clock to the D flip-flop DFF, whereby the D flip-flop DFF
Is an AND signal of the standby signal ST and the carry signal CA
CA · ST (see FIG. 8F) is captured by the next clock pulse CL2, and an enable signal EO is generated and output to the next-stage segment driver. Also, the latches L1 to L4 of the active control unit 10 are reset by the enable signal EO, and the standby signal ST is reset.

In the active control unit 10, the latch L4 is set by the next carry signal CA, the display data capture end signal CKSTOP, which is the output of the latch L4, becomes low level, and the clock pulse CL2 is blocked by the AND gate AND2.

As described above, in the present embodiment, the enable signal EI applied to the active control unit 10 from the preceding segment driver is
However, since it is used only for the purpose of internally generating a standby state, the operation speed of the segment driver is not limited by the signal transmission delay time between the segment drivers. Further, in the present embodiment, the carry signal is generated every time the counter section 30 counts a predetermined number of clocks, and this is not configured to be compared with the select code number. There is no need to provide a plurality of input terminals for setting code numbers.

[Effects of the Invention] As described above in detail, according to the present invention, a segment driving circuit connected in multiple stages for driving a plurality of segment electrodes of an LCD is provided with a counting means for generating a carry signal every predetermined period. Means for generating a standby signal indicating a standby state when an enable signal is applied from a preceding stage; a display data fetch signal and an enable signal for a next stage in response to the generated standby signal and a carry signal from the counting means Is not affected by the signal transmission delay time between the segment drive circuits, and the number of input terminals is not increased at all.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a part of a segment drive circuit according to an embodiment of the present invention, and FIG. 2 is a time chart of a part of the segment drive circuit shown in FIG. 10 Active control unit, 20 Enable signal generation unit, 30 Counter unit, NAND1, NAND2 NAND gate, L1 to L4 Latch, INV1 to INV4 Inverter, NO
R1 to NOR2 ... NOR gate, AND1 to AND4 ... AND gate, TFF1 to TFF4 ... T flip-flop, DFF ... D flip-flop.

Claims (1)

(57) [Claims] 1. A segment drive circuit connected in multiple stages to drive a plurality of segment electrodes of an LCD, respectively, wherein a count means for generating a carry signal every predetermined period, and when an enable signal is applied from a preceding stage. Means for generating a standby signal indicating a standby state, and means for generating a display data capture signal and an enable signal for the next stage in accordance with the generated standby signal and a carry signal from the counting means. LCD segment drive circuit characterized by the following.