JP2662075B2 - Stacked three-dimensional semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a three-dimensional circuit, particularly
The present invention relates to a stacked three-dimensional semiconductor integrated circuit having a configuration in which the three-dimensional semiconductor integrated circuits are arranged in rows and n columns.

[Prior Art] FIG. 3 shows, for example, IEEJ Transactions on Electronics Vol. J72-C.
FIG. 2 is a perspective view showing an example of a conventional stacked three-dimensional semiconductor integrated circuit disclosed in No. 5 (May 1989), for example, an image sensor circuit having a three-layer structure. In the figure, 1 is 1
A light sensor block corresponding to a pixel, 2 is an A / D converter block for one layer connected to the lower layer of the light sensor block 1, and 3 is connected to the lower layer of the A / D converter block 2. Is a logic circuit (ALU) block for one pixel.

FIG. 4A is a perspective view of the image sensor circuit of FIG. 3 focusing on a power supply line and a ground line, and FIG. 4B is a top view. 11 is power line for optical sensor,
Reference numeral 12 denotes an optical sensor ground line, 21 denotes an A / D converter power line, 22 denotes an A / D converter ground line, 31 denotes a logic circuit power line, and 32 denotes a logic circuit ground line. Reference numeral 14 denotes a sensor area formed by arranging the optical sensor blocks 1 in m rows and n columns, and 24 denotes an A / D converter block 2 in m rows and n columns.
An A / D converter area 34 is formed by arranging the logic circuit blocks 3, and a logic circuit area 34 is formed by arranging the logic circuit blocks 3 in m rows and n columns.

Next, the operation of the thus configured image sensor circuit will be described.

When light strikes the sensor area 14, the photosensor blocks 1 arranged in m rows and n columns output a voltage corresponding to the light intensity for each pixel in accordance with the image (image). The lower-layer A / D converter block 2 converts each into a digital value. Further, the digital value is subjected to digital operation between adjacent pixels in the lower logic circuit block 3 to perform processing such as edge detection. Also, a logic circuit power supply line 31, a logic circuit ground line 32,
Power line 21 for A / D converter, Ground line for A / D converter
22 means that the circuit blocks 3 and 2 are formed in the lowermost layer of the laminated structure and the layer immediately above it, and in the process of making from the lowermost layer, these wirings that are not the uppermost layer usually use high melting point materials. It is formed with. That is, even if a heat treatment in a later process step is performed, the wiring formed before that must endure the heat.

[Problems to be Solved by the Invention] Since the conventional stacked three-dimensional semiconductor integrated circuit is configured as described above, a high melting point material is used as a wiring material in layers other than the uppermost layer of the stacked structure or a layer near the uppermost layer. ing. However, it is known that the high melting point material has a very high resistivity as represented by, for example, tungsten silicide, and can have a sheet value of several ohms (the melting point of an aluminum wiring is low, but the sheet resistance is several ohms). 10 milliohms). For this reason, when a high melting point metal wiring is used, the voltage drop is more remarkable in a path through which a current flows, and a power supply line, a ground line, and the like when arranging circuit blocks in m rows and n columns have a greater distance from a pad as the size thereof increases. There is a problem that a voltage is not applied to a distant circuit block and the ground potential rises. This voltage drop has a greater effect if the circuit block is an analog circuit such as an A / D converter. In the case of an A / D converter, this causes a malfunction of A / D conversion.

FIG. 5 is a graph showing the power supply voltage applied to the photosensor block 1 and the A / D converter block 2 as a function of the position as viewed from the pad in the column direction. In this case, the layer on which the optical sensor block 1 is made is aluminum wiring, A / D
One layer of the converter block 2 uses a tungsten silicide wiring. In both cases, it is assumed that the power supply voltage V _DD is applied to the leftmost block near the pad. Both the optical sensor block 1 and the A / D converter block 2 have a voltage drop of ΔV1 and ΔV2 at the right end of the row, respectively.
Does not drop, whereas ΔV2 reaches about 1 to 2 V with respect to the original power supply voltage of 5 V. That is, there is a problem that the sensor characteristics of the entire image sensor circuit differ depending on the case of the sensor region 14, and the overall performance is impaired.

The present invention has been made to solve such a problem, and even if the size of a circuit block of m rows and n columns, that is, the number of pixels is increased, the characteristics of each pixel are made uniform and the sensor performance is improved. It is an object of the present invention to obtain a laminated three-dimensional semiconductor integrated circuit.

[Means for Solving the Problems] A stacked three-dimensional semiconductor integrated circuit according to the present invention has a structure in which a power supply line and a ground line in a sensor region are moved from a ground line to a lower region.
A power supply line and a ground line are wired using through holes for each block arranged in a matrix of rows and n columns.

[Operation] In the present invention, even if the resistance of the through hole dropped from the optical sensor block to the A / D converter block is large, the A / D converter block hardly gives a difference in voltage drop. The D converter block is operated with almost the same power supply voltage.

Embodiment An embodiment of the present invention will be described below with reference to the perspective view of FIG. In the figure, 1, 2, and 3 denote an optical sensor block, an A / D converter block, respectively, as described above with reference to FIG.
Logic circuit blocks, and 14, 24, and 34 are a sensor area, an A / D converter area, and a logic circuit area, respectively, as described above with reference to FIG. 4, and the internal circuits thereof are not shown but are shown in FIG. Is the same as Reference numeral 410 denotes a power supply pad for the layer in which a low-resistance wiring material can be used, that is, the sensor area 14, and 41 denotes a power supply pad.
And a power supply wiring made of a low-resistance wiring material.
420 is also the sensor area 1 where low resistance wiring material can be used
Reference numeral 4 denotes a ground pad, and reference numeral 42 denotes a ground wiring made of a low-resistance wiring material and connected to the ground pad 420. Reference numerals 51 and 52 denote a power supply line and a ground line of the A / D converter region 24, which are formed by through holes connected to the power supply line 41 and the ground line 42 formed of a low-resistance wiring material for each pixel. Similarly, reference numerals 61 and 62 denote a power supply line 41 formed of a low-resistance wiring material for each pixel and a ground line, which is a power supply line and a ground line of the logic circuit area 34, which are formed by through holes connected to a line 42.

Next, the operation of the embodiment configured as described above will be described.

The basic operation is the same as that shown in FIG. 3. However, in the present invention, the power supply wiring 41 is provided in the sensor area 14 including the photosensor blocks 1 corresponding to the pixels in m rows and n columns.
And the ground wiring 42 using a low-resistance wiring material (in this case, the uppermost layer is aluminum wiring). In the lower layer, the power supply wiring 41 and the ground wiring 42 provide through-hole lines. I have. For this reason, the difference in the degree of voltage drop depending on the position of each pixel of the power supply wiring 41 and the ground wiring 42 made of a low-resistance wiring material is small as before, and it may be said that the same power is supplied to each pixel. A through hole extending from each pixel to each A / D converter block 2 has a similar voltage drop on each A / D converter block 2 even if its resistance is large.
Therefore, each A / D converter block 2 is operated at substantially the same power supply voltage, and exhibits the same A / D conversion characteristics. The same can be said for the reference voltage wiring of the A / D converter block 2. That is,
It can be said that the characteristics of the sensor are improved.

FIG. 2 is a graph showing the power supply voltage applied to the photosensor block 1 and the A / D converter block 2 as a function of the position as viewed from the pad in the column direction, similarly to FIG.
Although the voltage applied to the A / D converter block 2 slightly drops from the power supply voltage, a substantially uniform voltage is applied to each A / D converter block 2. As a result, each A / D converter block 2 exhibits uniform characteristics.

In the above embodiment, the power supply line 5 of the A / D converter block 2
1. Although the ground line 52 and the power line 61 and the ground line 62 of the logic circuit block 3 are provided by the same power line and ground line, they may be separated and provided similarly through through holes. good. Although the power supply line and the ground line have been described, the same can be said for the reference voltage line of the A / D converter block.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an embodiment of the present invention, FIG. 2 is a graph showing a relationship between a power supply voltage and a position in the present invention,
FIG. 3 is a perspective view showing a conventional stacked three-dimensional semiconductor integrated circuit, and FIGS. 4A and 4B are perspective views showing the conventional stacked three-dimensional semiconductor integrated circuit together with a power supply line and a ground line. FIG. 5 is a top view and FIG. 5 is a graph showing the relationship between the power supply voltage and the position in the conventional stacked three-dimensional semiconductor integrated circuit. In the figure, 1 is an optical sensor block, 2 is an A / D converter block, 3 is a logic circuit block, 14 is a sensor area, 24 is an A / D converter area, 34 is a logic circuit area, 4
1 is a power supply wiring, 42 is a ground wiring, 51 and 52 are a power supply line and a ground line of the A / D converter block, and 61 and 62 are a power supply line and a ground line of the logic circuit block, respectively.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H01L 25/18

Claims (1)

(57) [Claims] 1. A sensor region comprising photosensor blocks arranged in a matrix of m rows and n columns (m and n are integers) and provided with power supply wiring and ground wiring formed of a low resistance wire material; At least one region including an A / D converter region, which is a lower layer of the sensor region and includes A / D converter blocks arranged in a matrix of m rows and n columns, and having a matrix of m rows and n columns. In the stacked three-dimensional semiconductor integrated circuit in which each of the arranged blocks is formed in a stacked structure, a through hole is provided for each of the blocks arranged in a matrix of m rows and n columns from the power supply wiring and the ground wiring to a lower layer area. A stacked three-dimensional semiconductor integrated circuit, wherein a power line and a ground line are wired using holes.