KR960003002B1 - Semiconductor memory device - Google Patents
Semiconductor memory device Download PDFInfo
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- KR960003002B1 KR960003002B1 KR1019920016976A KR920016976A KR960003002B1 KR 960003002 B1 KR960003002 B1 KR 960003002B1 KR 1019920016976 A KR1019920016976 A KR 1019920016976A KR 920016976 A KR920016976 A KR 920016976A KR 960003002 B1 KR960003002 B1 KR 960003002B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
Abstract
Description
제1도는 종래의 반도체 메모리 셀 어레이의 접지선 배치 방법을 나타내고,1 illustrates a conventional method of arranging ground lines in a semiconductor memory cell array.
제2도는 본 발명의 방법에 의한 반도체 메모리 셀 어레이의 접지선 배치 방법을 도시하고 있다.2 shows a method of arranging ground lines in a semiconductor memory cell array according to the method of the present invention.
본 발명은 반도체 메모리 장치에 관한 것으로, 특히 반도체 메모리 셀 어레이의 접지선 배치 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a method of arranging ground lines in a semiconductor memory cell array.
반도체 메모리 장치에 있어서 메모리 셀의 접지선은 외부 접지선과 내부 접지선으로 이루어지는데, 통상 외부 접지선은 알루미늄등의 저 저항 금속, 내부 접지선은 다결정 실리콘이나 활성층(Active)등 일반적으로 금속보다 큰 저항값을 가지는 재료로 만들어진다.In the semiconductor memory device, the ground line of the memory cell is composed of an external ground line and an internal ground line. In general, the external ground line has a low resistance metal such as aluminum, and the internal ground line has a resistance value larger than that of a metal such as polycrystalline silicon or an active layer. Made of materials
따라서, 종래 저집적 반도체 메모리 장치에 있어서는 외부 접지선인 금속선의 저항은 무시할 수 있었으나, 반도체 장치의 고집적활 메모리 셀 어레이가 커지면서 금속선 자체의 저항값도 무시할 수 없을 정도가 되었다.Therefore, in the conventional low density semiconductor memory device, the resistance of the metal wire, which is an external ground wire, can be ignored. However, as the highly integrated memory cell array of the semiconductor device increases, the resistance value of the metal wire itself cannot be ignored.
종래의 일반적인 메모리 셀 어레이는 다수개의 셀과 하나의 금속 접지선 열(row) 열방향으로 교대로 배치되는 방법으로 구성되어 있고, 상기 금속 접지선과 각각의 셀 사이의 접지선은 통상 셀 사이즈(size)를 줄이기 위하여 금속보다는 저항성이 큰 다결정 실리콘등의 재료를 사용하여 연결된다.Conventional memory cell arrays are constructed in such a way that a plurality of cells and one metal ground line are arranged alternately in a row column direction, and the ground line between the metal ground line and each cell generally has a cell size. In order to reduce, the connection is made using materials such as polycrystalline silicon, which is more resistant than metal.
첨부도면 제1도에 종래의 반도체 메모리 셀 어레이의 접지선배치 방법이 도시되어 있으며, 이를 참조하여 상세히 살펴보면, 먼저, 도면에 도시되지는 않았지만 전원 패드(pad)로부터 셀 어레이 경계(100)까지는 보통 넓은 폭으로 접지선(11,13,17)을 배선한다. 그러나, 셀 어레이 내에는 접지선(41,43,47)과 여러개의 셀들이 있으므로 넓은 폭의 금속선을 배선할 경우에는 메모리 소자가 커지게 되어 집적도에 문제가 있으므로 가능한 좁은 금속 배선을 사용하고 있다.In FIG. 1, a conventional method of arranging a ground line of a semiconductor memory cell array is illustrated. Referring to this, in detail, first, although not shown in the drawings, a power pad from a power pad to a cell array boundary 100 is generally wide. The ground lines 11, 13, and 17 are wired in width. However, since there are ground wires 41, 43, and 47 and a plurality of cells in the cell array, when wiring a wide metal line, the memory element becomes large and there is a problem in the degree of integration.
또, 소정의 메모리 셀 어레이 내에 금속 접지선(41,43,47)을 많이 배선하게 되면 인접한 두 배선 사이에 어레이되는 셀들의 수가 작아지고 그에 따라 내부 접지선(21, 24)의 저항은 작아지나, 그 결과 칩(chip) 사이즈가 커지게 되므로 셀 어레이 내의 금속 접지선의 배열은 칩 사이즈와 내부 접지선의 저항을 모두 고려하여 결정하게 된다.In addition, if a large number of metal ground lines 41, 43, 47 are wired in a predetermined memory cell array, the number of cells arrayed between two adjacent lines decreases, and thus the resistance of the internal ground lines 21, 24 decreases. As the resulting chip size increases, the arrangement of the metal ground lines in the cell array is determined by considering both the chip size and the resistance of the internal ground lines.
금속접지선과 셀 접지선의 연결은 칩 사이즈나 셀 배치의 제약때문에 금속보다는 일반적으로 저항이 큰 다결정 실리콘이나 활성층(Active)등을 이용하여 금속 접속선 사이에 접속된 내부 접지선(21,24)에 접지되어 이루어진다.The connection between the metal ground wire and the cell ground wire is grounded to the internal ground wires 21 and 24 connected between the metal connection wires using polycrystalline silicon or active layer, which is generally higher in resistance than metal, due to the limitation of chip size or cell arrangement. It is done.
이와같이 종래의 반도체 메모리 장치에 있어서 셀 어레이가 작을때는 셀 접지선의 저항이 금속 접지선이 아닌 내부 접지선의 저항에 의해 주로 결정되므로 셀 어레이 내에 배선되는 금속 접지선의 배열 숫자를 늘려 내부접지선의 저항을 줄임으로써 저 저항의 접지선의 실현이 가능하였으나, 셀 어레이의 사이즈가 큰 고집적 반도체 메모리 장치에 있어서는 금속 접지선의 길이가 길어져서 자체의 저항이 커지게되므로 금속 접지선의 배열을 늘리는 것만으로는 문제의 해결이 되지 않을 뿐아니라 칩 사이즈가 커지는 문제가 야기되어진다.In the conventional semiconductor memory device, when the cell array is small, the resistance of the cell ground wire is mainly determined by the resistance of the internal ground wire, not the metal ground wire. Therefore, the resistance of the internal ground wire is increased by increasing the number of arrays of metal ground wires that are wired in the cell array. Although low resistance ground wires can be realized, in a highly integrated semiconductor memory device having a large cell array size, the length of the metal ground wires is increased so that the resistance of the ground wires is increased, so increasing the arrangement of the metal ground wires does not solve the problem. Not only that, but also the problem of larger chip size is caused.
따라서, 본 발명에서는 칩 사이즈를 늘리지 않으면서 셀접지선의 저항을 줄여 반도체 메모리 장치의 동작특성을 향상시키는데 그 목적이 있다.Accordingly, an object of the present invention is to improve the operating characteristics of a semiconductor memory device by reducing the resistance of the cell ground line without increasing the chip size.
상기한 목적을 달성하기 위한 본 발명의 바람직한 반도체 메모리 셀 어레이의 접지선 배치 방법은 다수개의 메모리 셀 어레이를 갖는 반도체 메모리 장치에 있어서, 외부 접지선을 이용하여 각각 메모리 셀 어레이 주변을 격자 모양의 행과 열 방향으로 배치하여 상기 행과 열이 교차되는 곳이 외부 접지선을 서로 접속하고, 열 방향의 외부 접지선에 각각 연결되어 있는 내부 접지선에 상기 어레이의 각 메모리 셀이 전기적으로 접지되어서 이루어지는 것을 특징으로 한다.In accordance with an aspect of the present invention, there is provided a method of arranging ground lines of a semiconductor memory cell array according to an embodiment of the present invention. The memory cell of the array may be electrically connected to an internal ground line connected to the external ground lines in the column direction, and the rows and the columns may cross each other.
첨부 도면 제2도에는 본 발명의 방법에 의한 일 실시예가 도시되어 있으며, 이를 참조하여 보면, 복수개의 셀 어레이의 열과 외부 접지선(41,43,47)이 교대로 배치되어 메모리 셀 어레이가 구성되어 있음을 알수 있다. 또한, 행(columm) 방향으로 셀어레이와 외부 접지선(31,34)이 교대로 배치되어 행과 열이 서로 교차되는 지점에서는 외부 접지선이 서로 연결되어 있다. 여기서 행과 열 방향의 외부접지선은 절연막으로 분리되어 동종 또는 이종의 금속 도체로 배선한 다음, 교차되는 부분에만 동종 또는 이종의 금속 도체로 배선한 다음, 교차되는 부분에만 콘택-홀(contact hole)을 형성하여 상하의 외부 접지선을 연결시키게 된다.In the accompanying drawings, an embodiment according to the method of the present invention is shown. Referring to this, a column of a plurality of cell arrays and external ground lines 41, 43, and 47 are alternately arranged to form a memory cell array. You can see that. In addition, the cell array and the external ground lines 31 and 34 are alternately arranged in the column direction so that the external ground lines are connected to each other at the point where the rows and the columns cross each other. Here, the outer ground lines in the row and column directions are separated by an insulating film and wired with the same or different metal conductors, and then wired with the same or different metal conductors only at the intersections, and then contact holes only at the intersections. Form a to connect the upper and lower external ground wire.
열 방향의 외부 접지선(41,43,47)은 각 셀의 접지가 연결되어 있는 행 방향의 내부 접지선(21,24)에 각각 연결되며, 통상 상기 내부 접지선은 금속보다는 저항이 큰 다결정 실리콘등의 재료를 사용하게 된다.The external ground wires 41, 43 and 47 in the column direction are connected to the internal ground wires 21 and 24 in the row direction to which the ground of each cell is connected, and the internal ground wires are generally made of polycrystalline silicon or the like having a larger resistance than metal. Material is used.
반도체 메모리 셀 어레이의 접지선의 저항은 외부의 전원 패드(도면에는 도시되어 있지 않음)로 부터 셀 어레이의 가장자리(100)까지의 외부 접지선(11,13,17)의 저항과 셀 어레이 내의 외부접지선(31,34,41,43,47)의 저항과 외부 접지선으로부터 셀 접지사이의 내부 접지선(21,24)의 저항의 합으로 구성되는데, 통상 전원 패드로부터 셀 어레이 가장자리까지의 외부 전원선(11,13,17)은 폭이 넓은 금속을 사용하기 때문에 이 부분의 저항은 무시할 수가 있다. 그러므로, 셀 어레이의 접지선의 저항은 셀 어레이 내의 외부 접지선(41,43,47,31,34)의 저항과 내부 접지선(21,24)의 저항에 의해 결정되며, 본 발명에서는 저 저항의 외부 접지선을 각 셀 어레이의 내부 접지선에 병렬로 연결하여 접지선의 저항을 크게 줄이고 있다.The resistance of the ground line of the semiconductor memory cell array includes the resistance of the external ground lines 11, 13, and 17 from the external power pad (not shown) to the edge 100 of the cell array and the external ground line in the cell array ( It is composed of the sum of the resistances of 31, 34, 41, 43, 47 and the resistance of the internal ground lines 21, 24 between the external ground line and the cell ground. 13 and 17 use wide metals, so the resistance of this part can be neglected. Therefore, the resistance of the ground wire of the cell array is determined by the resistance of the external ground wires 41, 43, 47, 31, 34 and the resistance of the internal ground wires 21, 24 in the cell array. Is connected in parallel to the internal ground wire of each cell array, greatly reducing the resistance of the ground wire.
또, 반도체 메모리 셀 어레이가 고집적화로 인해 커지게 되면, 외부 접지선의 저항이 차지하는 비중이 높아지게 되며, 이를 해결하는 방법으로 외부 접지선을 행과 열 방향의 격자 모양으로 배치하고, 교차 지점을 연결함으로써 외부 접지선의 저항을 줄이고 있다.In addition, when the semiconductor memory cell array is increased due to high integration, the resistance of the external ground wire becomes high. As a solution to this, the external ground wire is arranged in a grid shape in a row and column direction, and an external point is connected by connecting intersection points. The resistance of the ground wire is being reduced.
이와같이 열 방향으로만 배치되던 종래의 외부 접지선을 본 발명에서는 열과 행 방향의 격자 모양으로 배치함으로써 반도체 메모리 장치의 셀 어레이 접지선의 저항을 크게 줄여 메모리 셀의 동작 특성을 개선하여 반도체 메모리 장치의 성능 및 신뢰성을 크게 향상시킬 수 있다.Thus, in the present invention, the conventional external ground wires arranged only in the column direction are disposed in a lattice shape in the column and row directions so that the resistance of the cell array ground lines of the semiconductor memory device is greatly reduced, thereby improving the operation characteristics of the memory cells and improving the performance of the semiconductor memory device. The reliability can be greatly improved.
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KR1019920016976A KR960003002B1 (en) | 1992-09-18 | 1992-09-18 | Semiconductor memory device |
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