JP2661046B2 - Image recording device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image recording apparatus, and more particularly to an image recording apparatus that outputs a synchronization signal and obtains image data synchronized with the synchronization signal from a host device. [Prior Art] Conventionally, in such an apparatus, as shown in FIG. 6, the latch timing of image data from a higher-level apparatus is set to be constant with respect to a synchronous clock signal output via an amplifier 11. For example, as shown in FIG. 7, the image data which is output in synchronization with the rise of the synchronous clock signal via the amplifying element 12 is latched by the flip-flop 13 at the fall of the synchronous clock signal. There was something to do. The time t ₁ the synchronous clock is at a high level is always constant. [Problems to be Solved by the Invention] However, in such an apparatus, an extension of a cable connecting the higher-level apparatus and the image recording apparatus due to a maintenance check or a design change, a change in a circuit of the higher-level apparatus, or a replacement of the higher-level apparatus itself, etc. Is performed, the latch timing of the image data may be different. In such a case, it is necessary to change the latch timing of the image data. Therefore, in the conventional device, the control circuit for controlling the internal latch timing is modified or replaced with a completely different control circuit to change the latch timing of the image data.
Therefore, the work of changing the latch timing becomes complicated,
There was a problem that the change took time. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an image recording apparatus which can simplify the operation when changing the latch timing of image data and can easily cope with the change. [Means and Actions for Solving the Problems] The present invention transmits a synchronization signal to a host device such as a host computer or a controller, and synchronizes image data transmitted by the host device based on the synchronization signal with the synchronization signal. In an image recording device that latches and records at a timing corresponding to a signal, a synchronization signal generation unit that generates a synchronization signal indicating a transmission timing at which the higher-level device transmits image data,
Latch signal generating means for generating a latch signal indicating a latch timing of image data transmitted by the higher-level device in response to a synchronization signal; and a synchronization signal generated by the synchronization signal generating means in response to a predetermined timing switching instruction Control means for controlling a phase relationship with a latch signal generated by the touch signal generation means, a synchronization signal output means for outputting a synchronization signal phase-controlled by the control means to the host device, and the control means And latch means for latching the image data transmitted by the host device based on the phase-controlled latch signal. Therefore, according to the present invention, the phase between the synchronization signal and the latch signal is set to a desired interval, so that the time from when the host device transmits image data to when the image data is latched can be simplified according to the situation. Can be set to Further, according to the present invention, the latch signal generation means generates a latch signal having a predetermined frequency and a predetermined phase, and the synchronization signal generation means has the same frequency as the latch signal generated by the latch signal generation means. The control means generates a plurality of synchronization signals each having a different phase relationship, and in response to the predetermined timing switching instruction, the control means generates a synchronization signal corresponding to the timing switching instruction from the plurality of synchronization signals generated by the synchronization signal generation means. A signal is selected. Therefore, according to the present invention, it is possible to transmit a synchronization signal having a desired phase relationship with a predetermined latch signal to a host device. Also, in the present invention, the synchronization signal generation means generates a synchronization signal having a predetermined frequency and a predetermined phase, and the latch signal generation means has the same frequency as the synchronization signal generated by the synchronization signal generation means. The control means generates a plurality of latch signals each having a different phase relationship, and the control means responds to the predetermined timing switching instruction and outputs a plurality of latch signals corresponding to the timing switching instruction from the plurality of latch signals generated by the latch signal generation means. A signal is selected. Therefore, according to the present invention, image data can be latched based on a latch signal having a desired phase relationship with a predetermined synchronization signal. Further, the present invention is characterized in that the control means receives a command signal from the higher-level device as the predetermined timing switching instruction, and selects a synchronization signal or a latch signal based on the command signal from the higher-level device. I do. Also, in the present invention, the control means receives a switch switching or a jumper line connection change as the predetermined timing switching instruction, and selects a synchronization signal or a latch signal based on the switch switching or jumper line connection change. It is characterized by doing. Therefore, according to the present invention, image data can be taken into the image recording apparatus as latch data at an appropriate timing. Embodiment An embodiment of the present invention will be described in detail with reference to the drawings of FIGS. FIG. 1 is a schematic block diagram of an image recording apparatus according to the present invention. Next, the control signal interface unit 21
The latch timing control signal from the host device is analyzed, and a timing switching signal is output to the timing generator 22. When the timing switching signal is input, the timing generator 22 changes the latch timing of the image data by adjusting the phases of the synchronous clock and the latch clock to a predetermined phase according to the switching signal, and sends the synchronous clock to the host device. And outputs the latch clock to the image data input unit 23. The image data input unit 23 latches the image data output from the host device according to the latch clock, and outputs the latched data to the image data processing unit 24. The image data processing unit 24 is synchronized with an image recording unit 25 described later by the timing generation unit 22, processes the input latch data by predetermined data processing, and is also synchronized by the timing generation unit. Image recording section
Output to 25. Thereby, the image recording unit 25 can satisfactorily record the image data subjected to the data processing. FIG. 2 shows a control signal interface unit shown in FIG.
FIG. 3 is a block diagram showing a timing generator 22 and a timing generator 22 in further detail. In the figure, latch timing control from a higher-level device is performed by a serial 8-bit command signal, and the higher-level device transmits a control code as the command signal and gives various instructions to the image recording apparatus.
The command receiving circuit 26 converts the received command signal into a parallel code and outputs it to the main control circuit 27.The main control circuit 27 uses a microprocessor in the circuit to control the latch timing control information from the code information of the command. And a latch timing command based on the control information is given to the latch clock selection circuit 28. The latch clock selection circuit 28 outputs a latch timing switching signal according to the command to the switching circuit 29. The switching circuit 29 includes eight clocks CK1 to CK8 having different phases obtained by dividing a clock CK (see FIG. 3) oscillated by a crystal oscillator 30 by a frequency dividing circuit 31 including a ring counter or the like.
(See FIG. 3), the switching circuit 29 is controlled to be switched based on the latch timing switching signal, and one of the clocks CK1 to CK8 is used as a latch clock, and the image data shown in FIG. Output to the input unit 23. In this embodiment, the clock CK3 among the clocks divided by the frequency dividing circuit 31 is used as a synchronous clock. The number of clocks used in the present invention is not limited to the eight-phase clock and may be any number. FIG. 4 shows another embodiment of the timing generator, in which the synchronous clock switching unit 35 selects a control signal from n-phase clocks having the same frequency output from the clock generator 34 and different phases only. One clock is selected according to the timing switching signal from the interface unit, and the selected one clock is output to the host device as a synchronous clock. The latch clock generating unit 36 outputs the latch clock to the image at a predetermined phase. Output to the data input section. That is, in this embodiment, the latch timing is changed by changing the time from when the output of the synchronization signal changes to when the image data is latched. Note that the timing generators shown in FIGS. 2 and 4 are merely examples, and other methods can be used to change the phase relationship between the synchronous clock and the latch clock.
The latch timing command is not limited to the command signal from the higher-level device shown in FIG. 2, but the command data is latched by, for example, operating a dip switch 40 provided on the control board as shown in FIG. It is also possible to output to the selection circuit 28.The latch clock selection circuit 28 determines which clock of the clocks CK1 to CK8 of the frequency divider 31 is to be selected as the latch clock based on the data from the dip switch and determines the predetermined timing. The switching signal is output to the switching circuit 29. The switching circuit 29 can select and output one of the clocks CK1 to CK8 input according to the timing switching signal as a latch clock. Needless to say, this dip switch can be applied to the switching control of the synchronous clock shown in FIG. Further, in the present invention, it is possible to use a jumper wire instead of the dip switch and change the connection of the jumper wire to give a latch timing command to the image recording apparatus. Therefore, according to the present invention, the latch timing can be easily changed based on a command from a host device or the like. [Effects of the Invention] As described above, in the present invention, the synchronization signal indicating the transmission timing at which the host device transmits image data and the latch signal indicating the latch timing at which the image data is latched have a desired phase relationship. Since the configuration is such that the following effects can be obtained. 1) The time from when the host device transmits the image data to when the image data is latched can be easily changed according to the situation. 2) When the cable connecting the host device and the image recording device is extended, the circuit of the host device is changed, or the host device itself is replaced, the control circuit for controlling the latch timing needs to be modified or replaced. Can be eliminated. 3) The operation of changing the latch timing can be performed quickly and easily.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of an image recording apparatus according to the present invention,
FIG. 2 is a block diagram showing in detail the control signal interface unit and the timing generation unit shown in FIG. 1, and FIG.
4 and 5 are block diagrams showing another embodiment of the present invention, and FIGS. 6 and 7 are circuit diagrams and timing charts of a conventional example. It is. 21: Control signal interface unit, 22: Timing generation unit, 23: Image data input unit, 24: Image data processing unit, 25: Image recording unit, 26: Command receiving circuit, 27: Main control Circuit 28 Latch clock selection circuit 29 Switching circuit 30 Crystal oscillator 31 Frequency divider circuit

Claims (1)

(57) [Claims] An image recording apparatus that transmits a synchronization signal to a higher-level device, and latches and records image data transmitted by the higher-level device based on the synchronization signal at a timing corresponding to the synchronization signal. A synchronizing signal generating means for generating a synchronizing signal indicating a transmission timing for transmitting the image data; a latch signal generating means for generating a latch signal indicating a latch timing of image data transmitted by the host device in response to the synchronizing signal; Control means for controlling a phase relationship between a synchronization signal generated by the synchronization signal generation means and a latch signal generated by the touch signal generation means in response to a timing switching instruction; and synchronization controlled by the control means. A synchronization signal output unit that outputs a signal to the host device; and a latch signal that is phase-controlled by the control unit. The image recording apparatus characterized by host device comprises a latch means for latching the image data transmitted. 2. The latch signal generation unit generates a latch signal having a predetermined frequency and a predetermined phase, and the synchronization signal generation unit includes a plurality of latch signals having the same frequency as the latch signal generated by the latch signal generation unit and having different phase relationships. In response to the predetermined timing switching instruction, the control means selects a synchronization signal corresponding to the timing switching instruction from a plurality of synchronization signals generated by the synchronization signal generating means. The image recording apparatus according to claim 1, wherein the image recording apparatus is characterized in that: 3. The synchronizing signal generating means generates a synchronizing signal having a predetermined frequency and a predetermined phase, and the latch signal generating means includes a plurality of synchronizing signals generated by the synchronizing signal generating means having the same frequency and different phase relationships. The control means, in response to the predetermined timing switching instruction, selects a latch signal corresponding to the timing switching instruction from a plurality of latch signals generated by the latch signal generation means. The image recording apparatus according to claim 1, wherein the image recording apparatus is characterized in that: 4. The claim, wherein the control means receives a command signal from the higher-level device as the predetermined timing switching instruction, and selects a synchronization signal or a latch signal based on the command signal from the higher-level device. Item (2) or the image recording device according to Item 3. 5. The control means receives a switch switching or jumper line connection change as the predetermined timing switching instruction, and selects a synchronization signal or a latch signal based on the switch switching or jumper line connection change. The image recording apparatus according to claim 2 or 3, wherein: