JP2660488B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.
In particular, the main memory and cache memory are
Integrated on chips and transfer information between their memories
The semiconductor memory device having a characteristic in the transmission part.
You. [0002] 2. Description of the Related Art Conventionally, the cost of computer systems has been increasing.
Low speed, large capacity,
Therefore, main memory composed of low-cost DRAM
And a central processing unit (CPU).
It is common practice to provide a small-capacity high-speed memory
Have been done. This fast buffer uses cache memory
Data blocks that are likely to be needed by the CPU.
Lock is copied from main memory and stored
You. [0003] The DRAM of the CPU
The data stored at the address is stored in the cache memory.
When it exists, it is called a hit, and the CPU has a fast cache.
Access to memory. [0004] On the other hand, an ad
Data stored in cache memory exists in cache memory
If not, it is called a cache miss, and the CPU slows down.
Access to the main memory of the
Transfer the belonging block to the cache memory. However, such a cache memo
Re-system requires expensive high-speed memory, so
It can be used in small systems where stress is important.
Did not. Therefore, conventionally, general-purpose DRAMs have
Use page mode or static column mode
Thus, a simple cache system was configured. FIG. 5 shows a page mode or a static mode.
Basics of conventional DRAM device capable of executing column mode
FIG. 3 is a block diagram illustrating a configuration. In FIG. 5, a memory cell array 1 includes
Multiple word lines and multiple bit line pairs cross each other
Memory cells at each of their intersections
Is provided. The word line of the memory cell array 1
It is connected to the row decoder unit 3 via the driver 2.
The bit line pair of the memory cell array 1
Column decoder unit via the control unit 4 and the I / O switch unit 5
6 is connected. The row decoder 3 has a row address buffer.
7 is connected, and the column decoder section 6 has a column address buffer.
8 are connected. These row address buffers 7 and
And column address buffer 8 have row address signals RA and
And multiplexed column address signal CA.
A rex address signal MPXA is provided. Furthermore, I
The I / O switch unit 5 includes an output buffer 9 and an input buffer.
FA 10 is connected. FIG. 6A, FIG. 6B and FIG.
Normal read cycle of DRAM, page mode cycle
Waveform chart of the static column mode cycle
Is shown. In a normal read cycle shown in FIG.
First, the row address buffer 7 stores the row address
Multiplexed at falling edge of strobe signal / RAS
Address signal MPXA is taken in, and row address signal RA is taken.
To the row decoder unit 3. The row decoder unit 3 receives the row address signal R
According to A, one of the word lines is selected. This
As a result, the multiple word lines connected to the selected word line
The information in the memory cell is read out to each bit line, and the information
Is detected and amplified by the sense amplifier unit 4. at the time
Thus, the information of the memory cells for one row is stored in the sense amplifier unit 4.
Has been locked. Next, the column address buffer 8
Multiple on the falling edge of the dress strobe signal / CAS
Captures the column address signal MPXA
The signal CA is given to the column decoder unit 6. The column decoder 6 receives the column address signal C
One row latched in the sense amplifier unit 4 according to A
One of the minute information is selected. This selected information
Via the I / O switch unit 5 and the output buffer 9
Output data D_OUTAs outside. In this case, the access time (/ RAS type)
M) t_RACOf the row address strobe signal / RAS
Output data D from falling edge_OUTTime until becomes effective
Between. In this case, the cycle time t_CIs the prime
The child is in the active state and the / RAS pre
Charge time t_RPAnd the standard value is
t_RAC= 100 ns and t_C= 200 ns
I have. The page model shown in FIGS. 6B and 6C
Mode and static column mode are
A memory cell is accessed by changing the column address signal CA.
Things. In the page mode, the column address
Column address signal at falling edge of strobe signal / CAS
Latch CA. In static column mode
Is a column address like a static RAM (SRAM).
Access only by the change of the scan signal CA. Page mode and static column mode
/ CAS access time t_{CA C}And address
Access time t_AAIs the / RAS access time t_RACof
The value becomes almost 1/2, and t_RAC= 5 for 100 ns
It is about 0 ns. In this case, the cycle time becomes faster,
/ CAS precharge time t in page mode_CPof
50n similar to static column mode, depending on the value
A value of about s is obtained. FIG. 7 shows a page mode of the DRAM device of FIG.
Simple key using the
FIG. 2 is a block diagram illustrating a configuration of a cache system. Ma
FIG. 8 is an operation waveform of the simple cache system of FIG.
FIG. In FIG. 7, the main memory 20 has 1M
1M byte by 8 DRAM elements 21 of × 1 configuration
It is configured. In this case, the row address signal RA and the column
The address signal CA is a total of 20 bits (2²⁰= 1048
576 = 1M). The address multiplexer 22 has 10 bits.
Row address signal RA and 10-bit column address signal
To give to the main memory 20 in two times
It is. This address multiplexer 22 has 20 bits.
Address lines A receiving the address signals of₀~ A
₁₉And a multiplexed 10-bit address signal
(Multiplex address signal MPXA)
10 address lines A to be given to the child 21₀~ A₉And have
ing. The address generator 23 includes a CPU 24
Generates address signals corresponding to the data required by
You. Latch (TAG) 25 is selected in the previous cycle.
Holds the row address signal RA corresponding to the data
You. The comparator 26 has a 20-bit address.
10-bit row address signal RA and TA
Compare with row address signal RAL held in G25
I do. If they match, the same row as in the previous cycle is activated.
Was hit (hit), and comparator 2
6 is a high level cache hit (Cache Hi)
t) Generate the signal CH. The state machine 27 has a cache hit.
In response to signal CH, row address strobe signal / R
Column address strobe with AS low
Page mode control for toggling signal / CAS is performed.
In response, address multiplexer 22 outputs DR
A column address signal CA is applied to the AM element 21 (see FIG. 8).
See). In the case of such a hit, the DRAM
Access time t from element 21_CACOutput data at high speed
Is obtained. On the other hand, generated from address generator 23
Row address signal RA and TAG 25 hold
If the row address signal RAL does not match,
Row different from the cache was accessed (cache miss
). In this case, the comparator 26
No bell cache hit signal CH is generated. In this case, the state machine 27
Performs / RAS and / CAS control of the read cycle,
The address multiplexer 22 supplies the row address signals RA and
And column address signal CA to DRAM element 21 in order.
(See FIG. 8). In the case of such a cache miss,
Normal read cycle starting from / RAS precharge
And the slow access time t_RACOutput data
The state machine 27
Generates a write signal Wait and waits for the CPU 24
You. In the case of a cache miss, a new TAG 25
New row address signal RA is held. As described above, the simple cache system shown in FIG.
In the system, one row of the memory cell array of the DRAM element
Minute data (1024 bits in case of 1M bit element)
Is one block. Therefore, the simple cache shown in FIG.
The system has an unnecessarily large block size and TAG
Insufficient number of blocks (number of entries) held in 25
(One entry in the system of FIG. 7),
There was a problem that the hit rate of Shu was low. As another conventional example, US Pat.
Simple cache as disclosed in 4,577,293
There is also a system. This simple cache system has 1
A register for holding data for a row is outside the memory cell array
If a hit occurs, the data is directly sent from this register.
To speed up access by extracting
You. However, the technique disclosed in this patent gazette
In the simple cache system, the external register is a memory cell
This holds one row of data in the array. others
Therefore, this simple cache system also has a block size
Unnecessarily large, similar to the conventional example shown in FIGS. 5 and 7
Another problem is that the cache hit rate is low. Therefore, a proposal has been made for the cache shown in FIG.
This is a DRAM device with a built-in memory. This DRAM device is the same as the DRAM device of FIG.
The differences are as follows. That is, DRAM memory
The cell array 1 has a plurality of memory cells in its address space.
Is divided into a plurality of blocks. In FIG.
Is divided into four blocks B1 to B4. The sense amplifier unit 4 and the I / O switch
Transfer gate 11 and SR
An AM memory cell array 12 is provided.
A decoder 13 and a way decoder 14 are provided.
I have. In the block decoder 13, the number of blocks
Column address buffer 8 from column address buffer 8
Some will be supplied, but their activation will be
No. CH. The way decoder 14 has a way
The way address signal WA is output via the dress buffer 15.
Given. The way decoder 14 outputs a way address signal.
Word of the SRAM memory cell array 12 according to the signal WA
Selectively drive a line. FIG. 10 shows a part of the structure of the DRAM device shown in FIG.
FIG. In FIG.
Amplifier 4, transfer gate 11, SRAM memory
Cell array 12, I / O switch section and column decoder section
6 denotes a plurality of bit line pairs of the DRAM memory cell array 1.
A plurality of sense amplifiers respectively corresponding to BL and / BL
40, transfer gate 110, SRAM memory cell
120, from the I / O switch 50 and the column decoder 60
Become. Each block of the DRAM memory cell array 1
Block decoder 13 is arranged corresponding to the lock.
You. Each sense amplifier 40 is connected to each bit line pair BL, / BL
Connected between them. Then, each bit line pair BL, / B
L is a transistor composed of N-channel MOSFETs Q1 and Q2.
Through the transfer gate 110, the SRAM memory cell
Connected to the bit line pair SBL, / SBL
You. Bit line of SRAM memory cell array 12
The pair SBL and / SBL are N-channel MOSFETs Q3 and
To the I / O buses I / O and / I / O via Q4
It is connected. MOSFET of transfer gate 110
The gates of Q1 and Q2 are connected by the block decoder 13.
A common transfer signal is applied to each block. Also,
Gates of MOSFETs Q3 and Q4 of each I / O switch 50
Column select signal by the corresponding column decoder 60.
Is given. In this DRAM device, the block data
A coder 13 is a transfer gate corresponding to each block.
110 by providing a transfer signal to the DRAM memory
The data on the same row from the cell array 1 in blocks is S
The data is transferred to the RAM memory cell array 12. SRAM memory by way decoder 14
Word line W of cell array 12₁~ W _nSelect one of
The SRAM memory cell connected to the word line.
Is stored in each bit line pair SBL, //
Read on SBL. Read on bit line pair SBL, / SBL
Data from the column decoder 60 to the I / O switch 50
When the column select signal is applied, the I / O bus
Read to I / O, / I / O. According to this DRAM device, one row of a plurality of columns
Data on one line as a data block
A plurality of data blocks are divided into a plurality of SRAM memory cells 12
0 and data blocks on different rows of the same column.
Is simultaneously held on the SRAM memory cell array 12.
(Association). Therefore, this SRAM memory cell array
If the memory is used as a cache memory,
The number of birds can be increased, resulting in cache hits.
Rate can be improved. Further, the SRAM memory cell array 12
Word line W₁~ W_nIf you keep the inactive state, DR
Write operation to AM memory cell array 1 and DRAM
During a read operation from memory cell array 1,
A configuration that does not transfer data to memory becomes possible,
Advantages of increased flexibility in application to memory systems
Occurs. FIG. 11 shows a case where the DRAM device of FIG. 9 is used.
FIG. 2 is a block diagram illustrating a configuration of a simple cache system.
You. In FIG. 11, the main memory 30 has
1M bytes by 8 DRAM elements 31 of M × 1 configuration
Is configured. The memory system shown in FIG.
The difference from the stem is the block of the DRAM element 31.
And the word line of the SRAM memory cell array 12
TAG25 and Comparator corresponding to the number of
That the number of radiators 26 has increased and
And a cache hit signal CH output from the
And the way address signal WA is input to the DRAM element 31.
It is a point that has been. Here, the way address signal is 2
Is a bit. The operation of the simple cache system shown in FIG.
FIG. 6 used in the description of the conventional simple cache system
(A) to (C) and the operation waveform chart of FIG.
Will be described. The TAG 25 has the newest block by block.
Row address corresponding to the row selected in the new cycle
It is held as a set cache address set.
Here, two bits are considered as the way address signal.
Therefore, four sets of row addresses are held. Therefore, assuming that the number of blocks is 4, 1
6 address sets are stored in TAG25.
And Also, a set of frequently used addresses is fixed.
May be held in the TAG 25 first. First, for the data required by the CPU 24,
Address generator 23 generates a corresponding address signal.
I do. The comparator 26 has a 20-bit address signal.
10-bit row address signal RA and column address
Bits corresponding to the block division of the signal CA
(2 bits in the example shown in FIG. 9), and
With the specified address set. If they match, the cache
A hit has occurred, and the comparator 26
The cache hit signal CH and the hit block
A way address signal WA is generated. The state machine 27 uses the cache memory
Row address strobe signal in response to
Column address strobe while / RAS is kept at low level.
Toggle the CAS signal / CAS. And respond to it
In addition, the address multiplexer 22 includes the DRAM element 31
Is supplied with a 10-bit column address signal CA (see FIG. 12).
See). At this time, in the DRAM element 31,
As shown in FIG. 9, the cache hit signal CH
The column address signal CA is controlled by the block decoder 1
3 is not supplied. Therefore, DRAM memory cell array 1
And the SRAM memory cell array 12 are separated from each other.
Keep. Then, 1 corresponding to the way address signal WA
From each row of SRAM memory cells 120, each bit line pair SB
Data is read onto L, / SBL. The I / O corresponding to the column address signal CA
Switch 50 is turned on by column decoder 60.
It is. Thereby, the column address signal CA and the way
In the SRAM memory cell 120 corresponding to the dress signal WA
Of the I / O bus I / O, / I / O and the output bus
It is output via the buffer 9. If you hit like this
In this case, the page mode of the SRAM
Access time t_CACOutput data at high speed
Will be. On the other hand, generated from address generator 23
Address signal and the cache signal held in TAG 25.
Cache address set does not match
A miss has occurred and comparator 26
No cache hit signal CH is generated. In this case, the state machine 27
Performs / RAS and / CAS control of the read cycle,
The address multiplexer 22 supplies the row address signal RA and
And the column address signal CA are sequentially supplied to the DRAM element 31.
(See FIG. 12). When a cache miss occurs as described above,
Low access time t_RACOutput data
Therefore, the state machine 27 outputs the wait signal Wa
It generates an "it" and waits for the CPU 24. In the case of a cache miss, the
The data of the block containing the accessed memory cell is
Transfer made conductive by the decoder 13
Through the gate 110, the DRAM memory cell array 1
From the bit lines BL and / BL to the way address signal WA
To the selected block of SRAM memory cells 120
Batch transfer. Thus, the SRAM memo of this block is
The contents stored in the recell 120 are rewritten. Also,
TA related to way address signal WA corresponding to lock
G25 holds a new address set. As described above, the DRAM device shown in FIG.
In a simple cache system, the cache memory
In the SRAM memory cell array 12 as a
Is retained. For this reason, data to TAG25
The number of data entries can be increased,
The hit rate of Shu becomes higher. Here, the case where a cache miss occurs
At the same time as accessing the DRAM memory cell array
For cache memory consisting of SRAM memory cell array
An example of transferring data has been described. However, not limited to this,
Unselect all word lines in SRAM memory cell array
By setting the state, this transfer can be prohibited. Similarly, writing to the DRAM memory cell array is performed.
Transfer to the SRAM memory cell array
It is also possible to select whether or not. Note that FIG.
An example is the 4-way set associative cash
Corresponds to stem. However, in this simple cache system,
If there is a cache hit,
To access the SRAM memory cell array 12 as
Address signal WA among the address signals for
It is output after the comparison by the comparator 26. Therefore, D of the way address signal WA
Since the supply to the RAM element 31 is delayed, the SRAM memory
Driving of the word line of the cell array 12 is delayed. For this reason,
Cache memo for high-speed SRAM memory cell array 12
Although it is a device that can be used as a
There was a disadvantage that the set time could not be increased. [0071] SUMMARY OF THE INVENTION As described above,
In addition, conventional cache systems include a cache hit.
Low access rate and fast access time
And so on. An object of the present invention is to provide a cache hit ratio.
Can be increased, and access time is shortened.
It is to provide a semiconductor memory device that can be used. [0073] The present invention according to claim 1 is provided.
Is a main memory, a cache memory, a transfer means and
It has transfer control means. The main memory is arranged in a plurality of rows and a plurality of columns.
With a plurality of memory cells, each storing information
Then, it is divided into a plurality of blocks in units of a plurality of columns. Ki
The cache memory is arranged in multiple columns, each of which stores information.
It has multiple storage elements to store
Blocks in the same number of columns as multiple columns
And read from main memory in block units
The stored information is stored in block units. The transfer means includes a main memory and a cache memory.
Connected to memory and block units from main memory
Reads the information read out in the cache memory in block units.
It is for transferring. The transfer control means is a transfer means
Reads information read from the main memory in block units,
One of the blocks in the cache memory
To control the transfer means to selectively transfer to
Things. The transfer means consists of main memory and cache memory.
Internal I / O band inserted between memory and main memory
Between the main memory and the internal I / O band.
Transfers information read in lock units to internal I / O band
Transfer gate means for internal I / O band
And between the cache memory and the internal I / O band
The transferred block information is stored in cache memory.
Second transfer gate for transferring in lock units
Means, and the transfer control means comprises a block selection address.
One of the main memory blocks according to the
The output of the block decoder for selecting
To the gate circuit for selective drive and way selection
Multiple blocks of cache memory depending on the dress
The output of the way decoder for selecting one of
The data is supplied to the transfer gate means and is selectively driven. The present invention described in claim 2 is directed to claim 1.
In the invention described above, a plurality of storage elements of the cache memory
Are arranged in multiple rows. The third aspect of the present invention provides the first aspect.
The invention according to item 2, wherein each storage of the cache memory is
The element is a static memory cell. The present invention described in claim 4 has no claim 1
3. In the invention according to any one of (3) and (4),
Stored in cache memory and read in block units
Transfers information to main memory in block units and controls transfer
Means, transfer means block unit from cache memory
The information read at
Transfer means to selectively transfer to any block
Control. The present invention described in claim 5 has no claim 1
3. In the invention according to any one of Items 3 to 3,
A transfer line including a plurality of transfer lines;
Including the transfer gate section on the main memory side, the second gate
The transfer gate means is provided with a plurality of cache memory side
Including the transfer gate section. A transfer line is connected to each block of the main memory.
The same number as the plurality of rows. Multiple main memory
The transfer gate section is provided for each block in the main memory.
Corresponding to the main memory.
Corresponding transfer of multiple rows and corresponding columns of blocks
Has multiple transfer gates connected to the line
You. A plurality of transfer memories on the cache memory side
The port part is associated with each block of the cache memory.
Corresponding to the corresponding blocks of the cache memory.
The corresponding row of locks and the corresponding transfer lines of multiple transfer lines
Have a plurality of transfer gates connected between them. [0082] The present invention described in claim 6 has no claim 1
5. The invention according to any one of claims 5 to 5, wherein
Includes a row selection means and a first column selection means,
The memory includes second column selection means. The row selecting means included in the main memory
Of a plurality of memory cells arranged in a predetermined row.
This is for selecting a molycell. In main memory
The first column selection means included in the plurality of memory cells
Select multiple memory cells arranged in a given column
It is for Second column included in cache memory
The selection means is arranged in a predetermined column of the plurality of storage elements.
This is for selecting the storage element that has been set. The present invention described in claim 7 has no claim 1
5. The invention according to any one of claims 5 to 5, wherein
Includes first row selection means and first column selection means,
The cache memory includes a second row selection unit and a second column.
Including selection means. First row selecting means included in main memory
Is a plurality of memory cells arranged in a predetermined row.
This is for selecting a number of memory cells. Main menu
The first column selecting means included in the memory includes a plurality of memory cells.
Select multiple memory cells arranged in a given column
It is for doing. Selection of the second row included in the cache memory
The means are arranged in a predetermined row of the plurality of storage elements.
This is for selecting a plurality of storage elements. Cash
The second column selection means included in the menu memory includes a plurality of storage elements.
To select storage elements arranged in a predetermined column among the children.
It is for [0088] [0089] The present invention described in claim 8 has no claim 1
7. In the invention according to any one of Items 7 to 7,
Each of the blocks is physically placed on a semiconductor substrate.
It is formed as a solid and is adjacent to the semiconductor substrate.
A boundary area is provided between adjacent blocks. [0091] According to the first aspect of the present invention, the main memo
Memory and cache memory are the same
Has been split into locks. Single block from main memory
The information read in the order is transferred in block units by the transfer means.
Is transferred to the cache memory. The transfer means is controlled by the transfer control means.
You. By that control, block unit from main memory
Position information to any block in the cache memory
Will be transferred. Block-by-block information transferred as such
Are stored in the cache memory in block units. As described above, the block unit is stored in the main memory.
The information read out in the
Is stored in blocks for each block.
For example, blocks in different rows in the same column of main memory
Multiple sets of unit information at the same time, different cache memories
Can be stored in blocks. Therefore, the data
Can be increased. As a result,
The hit rate can be improved, and the cash
The access time of the memory can be shortened. According to the second aspect of the present invention, the cache
Multiple storage elements of flash memory are arranged in multiple rows
As a result, the cache memory is
Information read in multiple places on multiple lines in block units
Can be stored. According to the third aspect of the present invention, a cache is provided.
Each memory element of the flash memory is a static memory
Higher cache hit rate for cells
And access time is fast
It is possible to According to the fourth aspect of the present invention, the cache
The information read from the flash memory in block units is transferred.
Is transferred to the main memory in block units by means
You. At the time of the transfer, the transfer means
Is controlled. Depending on the control, cache memory
The information in block units is stored in one of the blocks in main memory.
Transferred to lock. As described above, the block from the cache memory is
The information read in units of blocks can be
It is possible to transfer data to a block in blocks. According to the fifth aspect of the present invention, the main
As many transfer lines as columns in each block of the memory;
Multiple main memory transfer gates and multiple
Includes cache memory transfer gate
You. Block unit read from main memory
When the information is transferred to the cache memory,
Information from the column corresponding to the block in main memory
The corresponding transfer of the memory side transfer gate
The data is transferred to the corresponding transfer line via the gate. And
From the transfer line, block the cache memory at the destination of the information.
In the column corresponding to the
Information is transferred via the corresponding transfer gate in the gate section.
Will be transferred. [0100] According to the sixth aspect of the present invention, the main
The memory cell of the memory is a row selecting means and a first column selecting means.
Stage, and the storage element of the cache memory is
2 is selected by the column selecting means. According to the seventh aspect of the present invention, the main
The memory cell of the memory comprises a first row selection means and a first row selection means.
Selected by the column selecting means and stored in the cache memory
The elements are controlled by the second row selecting means and the second column selecting means.
Selected. [0103] [0104] According to the eighth aspect of the present invention, the main
Multiple blocks of memory are each stored on a semiconductor substrate.
Are formed physically, and the boundary between adjacent blocks is
Separated by areas. [0106] An embodiment of the present invention will be described below with reference to the drawings.
I will tell. FIG. 1 shows a DRA according to an embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration of an M element. This embodiment is shown in FIG. 9 except for the following points.
Same as the DRAM device, and the corresponding parts have the same reference numbers.
Numbers are attached, and the description is omitted as appropriate. In FIG. 1, DRA which is a main memory
M memory cell array 1 has a plurality of
It is divided into blocks. In this example, four blocks
It is divided into locks BK1 to BK4. On the other hand, the SRAM memory as a cache memory
The memory cell array 12 includes a plurality of blocks in a plurality of columns.
It is divided into several ways. In this example,
It is divided into four ways A to D. However, DRA
Number of blocks in M memory cell array 1 and SRAM memory
The number of ways of the cell array 12 may be different. DRAM memory cell array 1 and SRAM
Transfer means is provided between the memory cell array 12 and the memory cell array 12.
, Sense amplifier section 4, block transfer gate section
11, internal I / O band 41, and way transferage
A port portion 42 is provided. The block transfer gate section 11
In the transfer gate section on the RAM memory cell array 1 side
Yes, any block in the DRAM memory cell array 1
The data of one row of data is transferred to the internal I / O band 41 which is a transfer line.
To transfer. Block decoder as block selecting means
13 is a part of the column address signal CA (this embodiment)
2 bits in the case of
Block which block of data in (1) to transfer
A command is given to the transfer gate unit 11. The way transfer gate section 42 has the SR
In the transfer gate section on the AM memory cell array 12 side
The data transferred to the internal I / O band 41 is
Transfer to any way of M memory cell array 12
Things. Way decoder 14 serving as transfer control means
Are provided through the way address buffer 15.
In response to the A-address signal WA, the internal I / O band 41
Data is transferred to any way in the SRAM memory cell array 12.
To the way transfer gate unit 42 to transfer to
Is what you do. The SRAM memory cell array 12 has
Cache row decoder 43, cache I / O switch unit 4
4 and a cache column decoder 45 are provided. The cache row decoder 43 has a cache
Cache line address provided from address buffer 46
Address of the SRAM memory cell array 12 in response to the
One row is selected. Cache column decoder 4
5 is given from the cache address buffer 46.
In response to the cache column address signal, one of each way
This is for selecting a column. The cache address buffer 46 has the DR
Column address signal C applied to AM memory cell array 1
A is input as a cache address signal CCA, and
Part of the cache row address is assigned to the cache row decoder 43.
And a cache column decoder 43
As a cache column address signal. The cache I / O switch section 44 has S
A plurality corresponding to each way of the RAM memory cell array 12
SRAM sense amplifiers 47 each have an I / O line pair I
/ O _A~ I / O_DConnected through. Cache line decoder 43 and cache
S selected for each way by the queue column decoder unit 45
The data in the RAM memory cell array 12 is
Detected and amplified by the corresponding SRAM sense amplifier 47
It is. The way selector 48 has a way address bar.
In response to the way address signal WA given from the buffer 15.
In response, it is provided by a plurality of SRAM sense amplifiers 47.
Select one of the received data and output buffer 9
b through the cache output data D_OUTGo out as
It is something to empower. Cache input data D_INInput buffer as
The data given to the memory 10b is stored in the SRAM memory cell
When writing to one memory cell of the ray 12, the above procedure is reversed.
It is performed in the route of. In FIG. 1, a DRAM memory
Data A of each row of block BK1 of cell array 1₁, B
₁, C₁And D₁Is the SRAM memory cell array 12
Transfer to the same row of each way A, B, C and D
The state shown is shown. FIG. 2 shows the configuration of a part of FIG. 1 in detail.
FIG. Each block B of the DRAM memory cell array 1
In K1 to BK4, the sense amplifier unit 4 and the block
Transfer gate unit 11 includes n pairs of bit lines BL
₁~ BL_nN sense amplifier units 4 corresponding to
From 0 and n block transfer gates 110
Become. Further, the internal I / O band 41 includes n sets of I / O line pairs I.
/ O₁~ I / O_nConsists of These blocks BK1
BK4 is such that adjacent blocks are separated by a boundary area.
Can be Bit line pair BL of each block₁~ BL
_nAre the sense amplifier 40 and the block transfer gate.
I / O line pair I / O via port 110₁~ I /
O_nConnected to each other. On the other hand, the SRAM memory cell array 12
It is divided into four ways. Each way has n columns of S
RAM memory cell 120, ie, n bit line pairs
SBL₁~ SBL_nConsists of In each way, the way transfer
The port section 42 includes n bit line pairs SBL₁~ SBL_nTo
Correspondingly each of the n way transfer gates 42
Consists of zero. N sets of bit line pairs SBL in each way
₁~ SBL_nMeans Way Transfer Gate 4
20, the corresponding I / O line pair I of the internal I / O band 41
/ O ₁~ I / O_nConnected to each other. The cache I / O switch unit 44
Each bit line pair SBL of the AM memory cell array 12₁~ S
BL_nCache I / O switches 44 corresponding to
0 and 4 sets of I / O lines I / O corresponding to each way_A~
I / O_DConsists of N sets of bit line pairs SBL belonging to each way
₁~ SBL_nIs the cache I / O switch 4
40 to the I / O line corresponding to the way.
Have been. For example, bit line pair SB belonging to way C
L₁~ SBL_nAre all I / O line pairs I / O_CConnected to
Have been. The cache row decoding is performed for each way.
A dam portion 45 is provided. Cache row data for each way
The coder unit 45 stores n cache column data corresponding to each column.
It consists of a coder 450. Each cache column decoder 450
Is the MOS of the corresponding cache I / O switch 440
It is connected to the gate of the transistor. FIG. 3 is a simplified diagram using the DRAM device of FIG.
It is a block diagram showing the composition of an easy cash system. Referring to FIG. 3, main memory 30 has 1M
1 Mbyte by 8 DRAM elements 31 of × 1 configuration
Is configured. The memory system shown in FIG.
The difference from the stem is the output from the comparator 26.
Instead of a certain cache hit signal CH, multiple
Column address signal before being multiplexed by
A 10-bit address signal corresponding to the
Input to the DRAM element 31 as the dress signal CCA
And in response to the cache hit signal CH
Data select signal DS generated by state machine 27
Is input to the data selector 51. The data selector 51 receives the data select signal.
Signal DS from DRAM element 31 in response to signal DS.
Select RAM data DD or cache data CD
Output. The operation of the simplified cache system shown in FIG. 3 is illustrated.
This will be described with reference to the operation waveform diagram shown in FIG. In the TAG 25, the newest block
Row address corresponding to the row selected in the new cycle
The set cache address is held as a set. Here, as the way address signal WA,
Since two bits are considered, four sets of row addresses are held.
Have been. Therefore, if the number of blocks is 4, 16 sets
Is stored in the TAG 25
Become. In addition, fixed addresses frequently used are fixed.
You may make it hold in TAG25. The reason is that
This is to increase the use efficiency of the cache memory. That
Is realized in the DRAM device of FIG.
SRAM memory cell array 1 divided into blocks
Data of some blocks (for example, one block) of 2
Data may be fixed data. First, for the data required by the CPU 24,
Address generator 23 generates a corresponding address signal.
I do. The comparator 26 has a 20-bit address signal.
10-bit row address signal RA and column address
Bits corresponding to the block division of the signal CA
(2 bits in the example shown in FIG. 3), and
With the specified address set. If the two match, the cache is invalid.
The comparator 26 outputs a high level signal.
The cache hit signal CH and the hit block
A way address signal WA is generated. The address signal from the comparator 26
Assumes a cache hit prior to comparison
The DRAM device 31 has a 10-bit cache address.
Address signal CCA is input to read the SRAM memory cell.
Operation is in progress. Here, since four ways are considered, four
A bit read operation is in progress. Therefore, the cache
When a hit occurs, the way address signal WA is input.
When the data is input, the desired data is quickly stored in the cache data C
D via the cache output buffer 9b.
Data generated in response to the cache hit signal CH.
The data selector 51 according to the data select signal DS.
Thus, data of the cache memory is obtained. Conversely, the address input to the comparator 26
Address signal is not compatible with the address set held in TAG25.
If they match, a cache miss has occurred and the
The lator 26 does not generate the cache hit signal CH.
As a result, the cache output from the SRAM memory cell is
The shred data CD will be ignored. In this case, the state machine 27
Performs the / RAS and / CAS control of the output cycle and
The dress multiplexer 22 receives the row address signal RA and
Column address signal CA is supplied to DRAM element 31 in order.
(See FIG. 4). When a cache miss occurs as described above,
Low access time t_RACOutput data
Therefore, the state machine 27 outputs the wait signal Wa
It generates an "it" and waits for the CPU 24. In the case of a cache miss, the
The data of the block containing the accessed memory cell is
Block decoder that is turned on by the
Via the transfer gate 110, the I / O band 41
/ O line pair I / O₁~ I / O_nIs forwarded to The data is a way address.
Way transfer gate 4 selected by signal WA
20 via the SRAM memory cell array 12.
A, and selected by the cache row decoder 43
The contents stored in the SRAM memory cell 120 on the written row are written.
Be replaced. Further, the corresponding block of the data block
The TAG 25 on rays is the new
Address set is retained. As described above, in the above embodiment, the key
SRAM memory cell array 12 as cache memory
0 holds data of a plurality of blocks. For this reason,
The number of data entries to the TAG 25 can be increased,
As a result, the probability of hits can be improved,
First, when the access time of the cache memory becomes faster
This has the effect. [0150] According to the first aspect of the present invention, the main
Memory and cache memory in the same row
Divided from the main memory.
Information read in cache units is one of the cache memories
Is transferred and stored in arbitrary blocks in arbitrary blocks
It was to so. Therefore, the block size is unnecessarily large.
Efficiently increase the number of data entries
Can be As a result, the cache hit rate is
Access time
Can be Therefore, the semiconductor memory device of the present invention
If used, the cache hit rate is high and high-speed simple
Configuring an associative cash system
Can be. According to the second aspect of the present invention, the cache
Multiple storage elements of flash memory are arranged in multiple rows
Therefore, in the cache memory,
Information read in lock units is blocked on multiple lines.
Can be stored in memory units. According to the third aspect of the present invention, a cache is provided.
Each memory element of the flash memory is a static memory
Higher cache hit rate for cells
Can further speed up access time
be able to. According to the present invention as set forth in claim 4, furthermore,
The information read from the cache memory in block units
Report to any block in main memory
Can be sent. According to the fifth aspect of the present invention, the main
Block information read from memory is cached
When transferred to memory, the information is stored in the main memory block.
From the row corresponding to the
Corresponding transfer via the corresponding transfer gate in the
Can be transferred to transmission line. And the transfer line
Correspond to the block of the cache memory at the destination of information.
The pair of transfer gates on the cache memory side
Transferring information via the corresponding transfer gate
Can be. [0157] According to the sixth aspect of the present invention, the main
A memory cell of a memory is selected by a row selecting means and a first column selecting means
Can be selected depending on the stage,
Storage elements can be selected by the second column selection means.
You. According to the present invention described in claim 7, furthermore,
Then, the memory cells of the main memory are stored in the first row selecting means and
And the second column selecting means.
A second row selection means and a second row selection means.
Can be selected by the column selecting means. [0160] [0161] According to the eighth aspect of the present invention, the main
Multiple blocks of memory, each on a semiconductor substrate
Are formed physically, and the boundary between adjacent blocks is
Claims 1 to 7 in a configuration separated by regions
The same effect as the effect of the invention described in (1) can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to one embodiment of the present invention. FIG. 2 is a block diagram showing in detail a configuration of a part of the semiconductor memory device of FIG. 1; FIG. 3 is a block diagram illustrating a configuration of a simple set associative cache system using the semiconductor memory device of FIG. 1; FIG. 4 is an operation waveform diagram of the simple cache system of FIG. 3; FIG. 5 is a block diagram showing a configuration of a conventional DRAM device. FIG. 6 is an operation waveform diagram of each of a normal read cycle, a page mode cycle, and a static column mode cycle in a conventional DRAM device. FIG. 7 is a block diagram showing a configuration of a simple cache system using the DRAM device of FIG. 5; FIG. 8 is an operation waveform diagram of the simplified cache system of FIG. 7; FIG. 9 is a block diagram showing a configuration of a DRAM device with a built-in cache memory. FIG. 10 is a block diagram showing in detail a configuration of a part of the DRAM device of FIG. 9; FIG. 11 is a block diagram showing a configuration of a simple cache system using the DRAM device of FIG. 9; FIG. 12 is an operation waveform diagram of the simplified cache system of FIG. 11; [Description of Signs] 1 DRAM memory cell array, 2 word driver,
3 row decoder section, 4 sense amplifier section, 5 I / O switch section, 6 column decoder section, 11 block transfer gate section, 12 SRAM memory cell array, 13
Block decoder, 14 way decoder, 15 way address buffer, 41 internal I / O band, 42 way transfer gate section, 43 cache row decoder, 44 cache I / O switch section, 45 cache column decoder section, 48 way selector.

   ────────────────────────────────────────────────── ─── Continuation of front page    (56) References JP-A-56-61082 (JP, A)                 JP-A-56-77968 (JP, A)                 JP-A-62-164296 (JP, A)                 JP-A-64-39691 (JP, A)                 JP-A-64-84495 (JP, A)                 JP-A-64-84492 (JP, A)

Claims (1)

(57) [Claims] A main memory arranged in a plurality of rows and a plurality of columns, each having a plurality of memory cells for storing information, and a main memory divided into a plurality of blocks in units of a plurality of columns; and arranged in a plurality of columns, each storing information. A cache memory having a plurality of storage elements, divided into a plurality of blocks of a plurality of columns in the same number as a plurality of columns in each block of the main memory, and storing information read in blocks from the main memory in blocks. A transfer unit connected between the main memory and the cache memory for transferring information read from the main memory in block units to the cache memory in block units; Information read in blocks from the cache memory is selectively stored in one of a plurality of blocks of the cache memory. Transfer control means for controlling the transfer means to transmit the data, the transfer means comprising: an internal I / O band inserted between the main memory and the cache memory; First transfer gate means provided between the internal I / O band and transferring information read from the main memory in block units to the internal I / O band; And a second transfer gate means provided between the cache memory and the cache memory for transferring the information in block units transferred to the internal I / O band to the cache memory in block units. The control means outputs the output of the block decoder for selecting one of the plurality of blocks of the main memory according to the block selection address to the first transformer. To the second transfer gate means for selective drive by giving the output to a transfer gate means for selecting one of a plurality of blocks of the cache memory according to a way select address.
Semiconductor storage device. 2. 2. The semiconductor memory device according to claim 1, wherein a plurality of storage elements of said cache memory are arranged in a plurality of rows. 3. 3. The semiconductor memory device according to claim 1, wherein each storage element of said cache memory is a static memory cell. 4. The transfer unit transfers the information stored in the cache memory and read in block units to the main memory in block units, and the transfer control unit reads the transfer unit in block units from the cache memory. 4. The semiconductor memory device according to claim 1, wherein said transfer means is controlled to selectively transfer information to any one of a plurality of blocks of a main memory. 5. The internal I / O band includes the same number of transfer lines as a plurality of columns in each block of the main memory, and the first transfer gate means is provided corresponding to each block of the main memory. A plurality of main memory-side transfer gate units each having a plurality of transfer gates connected between a corresponding column of a corresponding block of the main memory and a corresponding transfer line of the plurality of transfer lines, The transfer gate means is provided corresponding to each block of the cache memory, and each is connected between a corresponding column of the corresponding block of the cache memory and a corresponding transfer line of the plurality of transfer lines. 2. A method according to claim 1, further comprising a plurality of transfer gate units on a cache memory side having a plurality of transfer gates. The semiconductor memory device according to any one of claim 3. 6. The main memory includes: a row selection unit configured to select a plurality of memory cells arranged in a predetermined row of the plurality of memory cells; and a plurality of memory cells arranged in a predetermined column of the plurality of memory cells. A first column selecting means for selecting a memory cell of the plurality of memory cells, wherein the cache memory comprises: a second column selecting means for selecting a storage element arranged in a predetermined column among the plurality of storage means. 6. The semiconductor memory device according to claim 1, comprising means. 7. A first row selection unit for selecting a plurality of memory cells arranged in a predetermined row of the plurality of memory cells; and an array arranged in a predetermined column of the plurality of memory cells. First column selecting means for selecting a plurality of memory cells selected, wherein the cache memory is for selecting a plurality of storage elements arranged in a predetermined row among the plurality of storage elements. 6. The semiconductor device according to claim 1, further comprising: a second row selection unit; and a second column selection unit for selecting a storage element arranged in a predetermined column among the plurality of storage elements. 3. The semiconductor memory device according to claim 1. 8. Each of the plurality of blocks of the main memory includes:
While being physically solidified on a semiconductor substrate,
8. The semiconductor memory device according to claim 1, wherein a boundary region is provided between adjacent blocks on said semiconductor substrate.