JP2700886B2 - Semiconductor integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit device including latch means.
Is what you do. [Prior Art] Conventionally, semiconductor integrated circuit devices including a latch circuit have a variety of types.
There are various things. Here, as an example,
DRAM with built-in cache memory (dynamic run
(Dumb access memory) will be described. This DRAM
Using a simple cache with high cost performance
System can be configured. This cache
Before explaining the DRAM with built-in memory,
The moly system will be described. Traditionally, the cost performance of computer systems
Low speed, large capacity and therefore low to improve performance
Main memory consisting of cost DRAM and central processing unit
A small high-speed buffer as a high-speed buffer
It is common practice to provide a speed memory. This fast
Buffers are called cache memory and require CPU
Blocks of data that are likely to
Are copied and stored. CPU tries to access
The data stored at the DRAM address
When it is in memory, it is called a hit and the CPU
Access high-speed cache memory. on the other hand,
Stored at the address the CPU tried to access
Missing data when data does not exist in the cache memory
The CPU accesses the slow main memory.
At the same time, cache the block to which the data belongs.
Transfer to memory. However, such a cache memory system
Requires costly high-speed memory,
Can not be used with small systems to see
Was. Therefore, conventionally, the page mode that general-purpose DRAM has
Or simple column mode.
A flash system. FIG. 6 shows page mode or static column mode.
Block diagram showing the basic configuration of a conventional DRAM device capable of loading
It is. In the figure, a memory cell array 1 includes a plurality of words.
Line and multiple bit line pairs cross each other
And a memory cell is provided at each of those intersections.
I have. The word line of the memory cell array 1 is a word driver
2 and is connected to the row decoder unit 3 via the line 2. Also note
The bit line pairs of the recell array 1 are connected to the sense-up unit 4 and
Connected to the column decoder unit 6 via the I / O switch unit 5
I have. A row address buffer 7 is connected to the row decoder 3
And a column address buffer 8 is connected to the column decoder 6.
Have been. These row address buffer 7 and column address
The dress buffer 8 has a row address signal RA and a column address signal.
Multiplex address that multiplexes the address signal CA
Signal MPXA. In addition, I / O switch section 5
Output buffer 9 and input buffer 10 are connected
You. FIG. 7A, FIG. 7B and FIG.
Read cycle, page mode cycle and static
FIG. 4 shows an operation waveform diagram in a column mode cycle. In the normal read cycle shown in FIG. 7A, first,
The row address buffer 7 outputs a row address strobe signal
Multiplex address signal at falling edge of ▲ ▼
MPXA is taken in and row decoder section 3 is used as row address signal RA.
Give to. The row decoder 3 responds to the row address signal RA.
Then, one of the plurality of word lines is selected. This
Memory connected to this selected word line.
The information in the cell is read out to each bit line, and the information is
The signal is detected and amplified by the amplifier 4. At this point, 1
The information of the memory cells for the row is latched in the sense amplifier unit 4.
Have been. Next, the column address buffer 8 stores the column address.
Multiplex on falling edge of rest strobe signal ▲ ▼
Captures the rex address signal MPXA and the column address signal CA
And supplies it to the column decoder unit 6. The column decoder unit 6
Latch in sense amplifier unit 4 according to column address signal CA
One of the information for one line is selected. This selection
The selected information is stored in the I / O switch unit 5 and the output buffer 9
Output data D via _OUT As outside. this
Access time (▲ ▼ access time) t
_RAC Is the drop of row address strobe signal ▲ ▼
Output data D from edge _OUT Is the time until
You. Also, the cycle time t in this case _C Is the element
Active time and ▲ ▼ precharge
time And the standard value is t _RAC = 100 ns
In total _C = 200 ns. The page mode and status shown in FIGS. 7B and 7C
In the dynamic column mode, memory cells on the same row are
The access is performed by changing the address signal CA. Pe
In the mode, the column address strobe signal ▲
Latch the column address signal CA at the falling edge of ▼,
In static column mode, static RA
As in the case of M (SRAM), only the change in the column address signal CA
Access. Page mode and static column mode
▲ ▼ access time t _CAC And address access
Seth time t _AA Is ▲ ▼ access time t _RAC Almost one
/ 2 and t _RAC = 50 ns for 100 ns.
In this case, the cycle time is faster and the page mode
In case of ▲ ▼ precharge time 50ns, same as static column mode, depending on the value of
The value of the degree is obtained. FIG. 8 shows the page mode or the DRAM mode of FIG.
Simple cache using static column mode
FIG. 3 is a block diagram illustrating a configuration of a stem. FIG. 9 shows
FIG. 9 is an operation waveform diagram of the simple cache system of FIG. 8. In FIG. 8, there are eight main memories 20 in a 1M × 1 configuration.
1M bytes. This place
In this case, the row address signal RA and the column address signal CA
(2 ²⁰ = 1048576 = 1M) required. Address multi
Plexer 22 is composed of 10-bit row address signal RA and 1-bit
Column address signal CA and the main memory 20
20 that receives a 20-bit address signal
Book address line A ₀ ~ A ₁₉ 10 bits that were multiplexed with
Address signal (multiplex address signal MPXA)
Address lines A that apply ₀ ~ A ₉ Have
I have. The address generator 23 stores data required by the CPU 24.
And generates an address signal corresponding to the data. Latch circuit (TA
G) 25 corresponds to the data selected in the previous cycle
Holds the row address signal RA, and the comparator 26
10-bit row address signal out of 20 pit address signals
Signal RA and the row address signal RAL held in TAG25.
Compare. If they match, the same line as in the previous cycle
It is accessed (hit), and the comparison
26 is a high-level cache hit (CacheHit) signal.
Generate CH. State machine 27 hits cache
In response to the signal CH, the row address strobe signal ▲
Column address strobe while keeping ▼ at low level
Perform page mode control to toggle signal ▲ ▼
Address multiplexer 22 responds to the
The column address signal CA is applied to the child 21 (see FIG. 9). this
Is hit, the DRAM device 21 starts occupying
Im t _CAC Thus, output data can be obtained at high speed. On the other hand, the row address generated from the address generator 23 is
Signal RA and the row address signal RAL held by TAG25.
If there is a mismatch, a different row from the previous cycle is accessed.
(Mis-hit), and the comparator 26
Does not generate high-level cache hit signal CH. this
In this case, the state machine 27
▼ and ▲ ▼
Lexer 22 has a row address signal RAM and a column address signal CA
Are sequentially applied to the DRAM element 21 (see FIG. 9). in this way
In case of a miss hit, ▲ ▼ precharge
Performs a normal read cycle starting with
Time t _RAC Output data can be obtained with
Tate machine 27 generates wait signal WAIT and sends it to CPU 24.
Put a wait. In case of a miss hit, a new line at TAG25
The address signal RA is held. Thus, in the simple cash system of FIG.
For one row of a DRAM cell memory cell array (1 Mbit
(1024 bits in case of element) Data becomes one block
So the block size is unnecessarily large and kept at TAG25
The number of blocks (the number of entries) is insufficient (see FIG. 8).
1 entry in the system).
However, there was a problem that the power rate was low. Therefore, the cache memory shown in Fig. 10 was proposed.
It is a built-in DRAM element. This DRAM element is different from the DRAM element of FIG.
On the point. That is, the memory cell array 1 includes a plurality of columns.
It is divided into a plurality of blocks composed of memory cells.
In FIG. 10, the block is divided into four blocks B1 to B4.
You. The sense amplifier unit 4 and the I / O switch unit 5
Transfer gate unit 11 and data register unit 12
Is provided, and a block decoder 13 is further provided.
You. The block decoder 13 has a column address according to the number of blocks.
Part of the column address signal CA is supplied from the dress buffer 8.
Activation is controlled by the cash heat signal CH.
Is controlled. FIG. 11 shows in detail the configuration of a part of the DRAM device of FIG.
FIG. In FIG. 11, the sense amplifier unit 4
Port section 11, data register section 12, I / O switch section 5 and
And the column decoder unit 6 stores a plurality of bits of the memory cell array 1.
Multiple senses for each pair of lines BL and ▲ ▼
Amplifier 40, transfer gate 110, data register 12
0, an I / O switch 50 and a column decoder 60. Also,
Block data corresponding to each block of the memory cell array 1
A coder 13 is arranged. Each sense amplifier 40 is
It is connected between the pair of lines BL, ▲ ▼. And each bit
The line pair BL, ▲ ▼ is a line consisting of N-channel MOSFETs Q1, Q2.
The data in the data register 120 is transferred via the transfer gate 110.
Connected to the data line pair D. Data of data register 120
Data line pair D, through N-channel MOSFETs Q3 and Q4, respectively.
Connected to the I / O bus I / O, ▲ ▼. Trance
The gates of the MOSFETs Q1 and Q2
A common transfer signal is given to each block by the coder 13.
Can be Also, the gates of MOSFETs Q3 and Q4 of each I / O switch 50
Is supplied with a column selection signal by the corresponding column decoder 60.
available. In this DRAM device, the block decoder 13 controls each block.
Transfer signal to transfer gate 110 corresponding to lock
Thus, the block unit from the memory cell array 1 is
The data on the same row is transferred to the data register 120
You. The data held in the data register 120 is column-decoded.
The column selection signal is given from the
Read by the I / O bus I / O, ▲ ▼
You. According to this DRAM element, one row of data in a plurality of columns is stored in one.
Multiple data blocks on different rows
The lock is held in a plurality of data registers 120. did
As a result, the block size becomes
Key (block) can be increased.
System with improved cache memory hit rate
A simple cache system with high performance
Can be FIG. 12 is a simplified cache using the DRAM device of FIG.
FIG. 1 is a block diagram illustrating a configuration of a system. In FIG. 12, there are eight main memories 30 in a 1M × 1 configuration.
1M bytes. Fig. 12
Is different from the memory system of FIG.
TAG25 corresponds to the number of blocks divided into DRAM elements 31.
And the number of comparators 26
The cache hit signal CH output from the parator 26 is
The point is that it is also input to the DRAM element 31. The operation of the simple cache system shown in FIG.
Referring to FIG. 9 used in the description of the cache system,
Will be described. In TAG25, each block is selected in the previous cycle.
Row address or frequently used address
(Depending on how the system is created)
It is held as a less set. In this example, TAG25
Holds four address sets. First, the address corresponding to the data required by the CPU 24
The signal is generated by the address generator 23. Comparing
The data 26 is a 10-bit row signal of the 20-bit address signal.
Of the dress signal RA and column address signal CA
10 bits (two bits in the example shown in FIG. 10).
) And the address set held in TAG25
You. And if they match, you have hit the cache
And the comparator 26 outputs a high-level cache hit.
And generates a reset signal CH. The state machine 27
Row address strobe in response to shout signal CH
Column address while keeping signal ▲ ▼ low
Toggle the strobe signal ▲ ▼ and respond
The address multiplexer 22 stores a 10-bit string in the DRAM element 31.
An address signal CA is applied (see FIG. 9). At this time, DR
In the case of the AM element 31, as shown in FIG.
The column address signal CA is controlled by the hit signal CH.
It is not supplied to the lock decoder 13. Therefore, note
The recell array 1 and the data register section 12 are separated.
Keep state. The data register corresponding to the column address signal CA
Data in the I / O switch 50, I / O bus I / O, ▲
And output via the output buffer 9. this
The data register of the DRAM element 31
Access time t from page 120 as in page mode _CAC so
Output data can be obtained at high speed. On the other hand, the address generated by the address generator 23 is
Address signal and the cache address set held in TAG25.
If they do not match, it means a mishit and
The comparator 26 does not generate a high-level cache signal CH.
No. In this case, the state machine 27
▲ ▼ and ▲ ▼ control of
The multiplexer 22 receives the row address signal RA and the column address.
The signal CA is sequentially supplied to the DRAM element 31 (see FIG. 9). This
If there is a miss hit like
Mu t _RAC Output data will be obtained by
Machine 27 generates wait signal WAIT and waits for CPU 24
multiply. In case of a miss hit,
Data of the block containing the memory cell
Transfer gate 11 made conductive by coder 13
Data register 120 from bit line BL, ▲ ▼ through 0
Will be batch transferred. At this time, the new address is stored in TAG25.
Sset is retained. Thus, a simple cache using the DRAM device of FIG.
In the cache system, the cache
The number of birds can be increased,
Cut rate increases. [Problems to be Solved by the Invention] In the conventional DRAM device described above, the operation
From the data register 120 to the memory cell array 1
Data from the memory cell array 1 to the data register 120.
Data transfer. For example, a mishit
In the read operation, the memory cell array 1
At the same time, data is read from the memory cell array 1.
Is transferred to the data register 120. On the other hand, hit
In such a case, data is written into the data register 120 once.
At the same time or later, the data is stored in the memory cell array 1
Is written to the corresponding block of. That is, data
Data transfer from the register 120 to the memory cell array 1 is performed.
(See Figure 11). Transfer from memory cell array 1 to data register 120
First, the potential of the word line of the memory cell array 1 is raised.
After activating the sense amplifier 40,
Open the port 110 and connect to the data line pair D, of the data register 120.
Connect the bit line pair BL, ▲ ▼ to connect the bit line pair BL, ▲
Data transfer is performed by transmitting the potential of ▼.
You. In this case, the previous data is stored in the data register 120.
The data that has been latched and is about to be
If the data is inverted data of
Must invert the data held in data register 120
Must. Therefore, the data retention of the sense amplifier 40
Capability is at least the data holding capacity of data register 120
If it does not exceed the value, the data
Data cannot be transferred to the register 120. But sense
The data holding capacity of the amplifier 40 is
Data holding capacity,
The data held in the sense amplifier 40 is inverted by the
And the memory cell from the data register 120
Data transfer to array 1 becomes impossible. Thus, the DRAM device shown in FIGS. 10 and 11
In the case, the data register 120 and the sense amplifier 40
The problem is that bidirectional data transfer between
Was. Such problems are not limited to the above-mentioned DRAM elements, but
Data transfer between registers composed of
It can happen. Therefore, conventionally, when transferring data to a register,
It was as follows. That is, as shown in FIG.
Connect transistor Q between data line pair D of register R
Before transferring data to register R,
To turn on the transistor Q and connect the data lines D and
A short circuit occurs, and the potentials of the data lines D and D are set to the intermediate potential.
Thereafter, the transistor Q is turned off, and the data lines D and D are turned off.
And floating by
Data is transferred after killing the data holding capacity of the data R. However, in this case, the inverter holds the intermediate potential and
Therefore, a through current flows. Especially like the DRAM above
If a large amount of data is transferred at one time,
There is a problem that a current flows. The present invention has been made to solve the above problems.
Data transfer without increasing current consumption
To obtain a semiconductor integrated circuit device capable of
You. [Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention is a
, Cache memory and information
Means. Main memory has multiple memory cells and multiple words
Line, multiple bit line pairs and multiple sense amplifiers
You. Multiple memory cells are arranged in multiple rows and multiple columns.
Each one transistor element and one capacitor
And an element for storing information. Multiple words
Are placed on multiple lines, each on a corresponding line.
The plurality of placed memory cells are connected. Multiple bits
Line pairs are arranged in multiple columns, each in a corresponding column.
Memory cells are connected and arranged in parallel.
You. Multiple sense amplifiers are arranged in multiple rows and
Connected to the bit line pair of the corresponding column, and the bit line pair of the corresponding column.
Senses and amplifies the potential difference that appears in Cache memory
Has multiple storage elements and is read from main memory
The stored information is stored. Means for improving the ability to transmit information are
Read from in-memory memory cells,
Transmit amplified information to storage element of cache memory
When transmitting the information, the driving capability of the information is increased. Further, the semiconductor integrated circuit device according to the present invention
Memory, cache memory and information transmission drive capacity
Means to enhance. The main memory has multiple memory cells.
Multiple word lines, multiple bit line pairs and multiple cells.
It has a sense amplifier. Multiple memory cells are stored in multiple rows and
And multiple rows, each with one transistor element
It is composed of one capacitor element and stores information
I do. The multiple word lines are arranged in multiple rows, each of which
Are connected to multiple memory cells arranged in the corresponding row.
You. A plurality of bit line pairs are arranged in a plurality of columns, and
Are connected to multiple memory cells arranged in the corresponding column.
Are arranged in parallel. Multiple sense amplifiers, multiple columns
And connected to the bit line pair of the corresponding column,
Senses and amplifies the potential difference that appears on the bit line pairs in the
You. A cache memory has a plurality of storage elements,
Information read from the main memory and
The information to be written is stored in the memory. Information transmission drive
The means to increase the capacity is from the storage element of the cache memory
Transmits read information to memory cells in main memory
At that time, the information transmission driving ability is enhanced. [Operation] In the semiconductor integrated circuit device according to the present invention, the main
Read from the memory cells of the main memory
Information amplified by the sense amplifier
When the information is transmitted to the storage element of
Enhanced. Therefore, cache from main memory
Transmission of information to memory
It is possible to transfer information from memory to cache memory.
You. Further, in the semiconductor integrated circuit device according to the present invention,
Stores the information read from the storage element of the cache memory.
When transmitting the information to the memory cells of the main memory,
The transmission drive capability is enhanced. Therefore, the cache
When the drive capability for transmitting information from memory to main memory is low
Even if the information is transferred from the cache memory to the main memory.
Communication becomes possible. Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a configuration of a DRAM device according to an embodiment of the present invention.
FIG. This DRAM device is shown in FIG.
The difference from the DRAM element is that the transfer gate 11 and the data
Sub data register section 14 is provided between the
It is a point that is. In this DRAM element, the memory cell array 1
Constitute the main memory, and the data register section 12
Configure a flash memory. The sub data register unit 14 enhances the information transmission drive capability.
As shown in FIG.
Provided between the port 110 and the data register 120, respectively.
And a plurality of sub data registers 140. As described in the conventional example, the memory cell array
1 is decomposed into a plurality of blocks in units of a plurality of columns.
Then, the data register section 12 also corresponds to the memory cell array 1.
Accordingly, it can be said that it is divided into a plurality of blocks. FIG. 3 shows the sense amplifier 40 and the transfer gate 11
0, sub data register 140 and data register 120
FIG. 3 is a diagram illustrating a specific circuit configuration. The sense amplifier 40 includes P-channel MOS transistors Q5 and Q6.
And N-channel MOS transistors Q7 and Q8. Tiger
The transistor Q5 is connected between the bit line BL and the node N1,
Its gate is connected to the bit line ▲ ▼. Tiger
Transistor Q6 is connected between bit line ▲ ▼ and node N1
The gate is connected to the bit line BL. Ma
The transistor Q7 is connected between the bit line BL and the node N2.
Connected to the bit line ▲ ▼
You. Transistor Q8 is connected between bit line ▲ ▼ and node N2.
And its gate is connected to the bit line BL.
You. Node N1 is connected via P-channel MOS transistor Q9
Power supply potential V _CC And node N2 is an N-channel M
Connected to ground via OS transistor Q10
You. The sense amplifier drive signal is applied to the gate of transistor Q9.
▲ ▼ is given, and the gate of transistor Q10 is
An amplifier drive signal φs is provided. The data register 120 as a storage element is a P-channel M
OS transistors Q11 and Q12 and N-channel MOS transistors
Data Q13 and Q14. Transistor Q11 is connected to data line D
Source potential V _CC And its gate is connected to the data line
It is connected to the. Transistor Q12 is connected to data line
Source potential V _CC And its gate is connected to data line D
It is connected to the. Also, transistor Q13 is a data line
D and ground potential, the gate of which is connected to the data line
It is connected to the. Transistor Q14 is connected to the data line
And the gate is connected to data line D.
It is connected. The sub data register 140 is an NMOS flip-flop.
N-channel MOS transistors Q15, Q16, Q
Consists of 17 Transistor Q15 is connected to data line D and node N3.
And its gate is connected to the data line
ing. Transistor Q16 is connected between data line and node N3.
And its gate is connected to the data line D.
You. Transistor Q17 is connected between node N3 and ground potential.
Control signal φ is applied to the gate. control
Signal φ is normally low, and data register 120
Data is transferred to the memory cell through the sense amplifier 40.
When you rise to a high level. Transmission of information of data register 120 and sense amplifier 40
Drive capability (hereinafter referred to as data retention capability)
Is determined by the channel width of the transistor constituting the transistor. You
In other words, the larger the transistor channel width,
Need to pass large current to reverse the data
Therefore, the data holding ability is large. Here, the data holding capacity of the data register 120 is set.
It is assumed that it is smaller than the data holding capacity of the sense amplifier 40. This
In the case of, the data holding capacity of the sub-data register 140 and
The sum with the data holding capacity of the data register 120 is sensed.
The sub data is set to exceed the data holding capacity of the amplifier 40.
The data holding capacity of the data register 140 is set. Specifically
Is the transistor of the sub data register 140
Channel widths and corresponding transitions in data register 120
The sum of the channel width of the
Set to be larger than the corresponding transistor
Just do it. Data from memory cell array 1 to data register 120
Transfer the control signal φ at low level.
To deactivate sub data register 140
Open the fagate 110. In this case, the sense amplifier 40
Data holding capacity is higher than the data holding capacity of data register 120.
The data register 12 from the sense amplifier 40.
Data transfer to 0 is performed. On the other hand, from the data register 120 to the memory cell array 1
When transferring data, set control signal φ to high level.
After the sub data register 140 is activated by
Open the sphagate 110. In this case, the data register 120
Data holding capacity of the sub data register 140
The sum of the data holding capacity and the data holding capacity
Because it is higher than
Data can be inverted.
Data transfer from the data 120 to the memory cell array 1 is performed.
It is. As described above, in the DRAM device of the above embodiment, the data
The data holding capacity of the data register 120 is variable.
Between the data register 120 and the sense amplifier 40.
Data transfer in the
A rush system is obtained. In the above description, the sub data register 140 is controlled.
Control signal φ is normally low level and the data register
When data is transferred from the data 120 to the memory cell array 1,
To rise to a high level when
From the memory cell array 1 to the data register 12
It may be set to low level when transferring data to 0
No. Above, the data holding capacity of the data register 120 is sensitive.
Configuration example when the data holding capacity is smaller than that of SAMP40
It is. Conversely, the data holding capacity of the data register 120 is
If it is larger than the data holding capacity of the sense amplifier 40
Sets the sub data register 140 to the transfer gate 110
A memory cell array added to the memory cell array 1
Active when data is transferred from 1 to data register 120
From the data register 120 to the memory cell array 1
Is configured to be inactive at the time of data transfer.
Good. In this case, the data holding of the sub data register 140
The sum of the capacity and the data holding capacity of the sense amplifier 40 is
Data register 120's data holding capacity.
Must be set as follows. In the above embodiment, the sub data register 140 is set to N
It is composed of a channel latch circuit and a switch for controlling it.
Switch transistor Q17 is connected to transistors Q15 and Q16.
Although provided between the common source and the ground potential, as shown in FIG.
As shown, the latch constituted by the transistors Q15 and Q16
N channels between the circuit and the data lines D and
Connect MOS transistors Q18 and Q19 and connect their
Control signal φ to the gates of transistors Q18 and Q19.
You may do it. Also, as shown in FIG.
Are connected to P-channel MOS transistors Q21, Q22, Q23 and N-channel MOS transistors.
MOS type transistor consisting of channel MOS transistors Q24, Q25, Q26
It may be configured by a CMOS circuit that is a rip-flop means.
No. The configuration of the sub data register 140 in FIG. 5 is shown in FIG.
This is the same as the configuration of the sense amplifier 40 shown. Transis
A control signal is applied to the gate of the
Control signal φ is applied to the gate of data transistor Q26. In short, data transfer is controlled by appropriate control signals.
Switch to active or inactive state at
The data holding capacity of the
It is the present invention that the device
It is the gist of. Further, the present invention relates to the sense amplifier 40 and the data register.
Not limited to transferring data between
Also applies when you want to make the data retention capacity of the switch circuit variable
can do. [Effect of the Invention] As described above, according to the present invention, the key is stored in the main memory.
The ability to transmit information to the cache memory
Between the main memory and the cache memory.
Bi-directional transfer of information can be performed without increasing current consumption
It becomes possible easily. Also, the transfer of information from cache memory to main memory
The transmission drive capability is enhanced, so the main memory and cache
Transfer of information to and from
This is easily possible without increasing the flow.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a DRAM device according to an embodiment of the present invention; FIG. 2 is a block diagram showing a configuration of a part of the DRAM device of FIG. 1 in detail; FIG. 4 is a specific circuit diagram of a main part of FIG. 2, FIG. 4 is a circuit diagram showing another example of the sub data register shown in FIG. 2, and FIG. 5 is a sub data register shown in FIG. Circuit diagram showing still another example of
FIG. 6 is a block diagram showing the configuration of a conventional DRAM device, and FIG.
FIG. 7 is an operation waveform diagram of a conventional DRAM device in a normal read cycle, FIG. 7B is an operation waveform diagram of a conventional DRAM device in a page mode cycle, and FIG. 7C is an operation waveform diagram of a conventional DRAM device in a static column mode cycle. And FIG. 8 shows the DR of FIG.
FIG. 9 is a block diagram showing a configuration of a simple cache system using an AM device, FIG. 9 is an operation waveform diagram of the simple cache system of FIG. 8, FIG. 10 is a block diagram showing a configuration of a DRAM device with a built-in cache memory, and FIG. Is a block diagram showing in detail the configuration of a part of the DRAM device of FIG. 10, FIG. 12 is a block diagram showing a configuration of a simple cache system using the DRAM device of FIG. 10, and FIG. 13 is a data transfer to a register. FIG. 4 is a diagram for explaining a conventional method of performing the above. In the figure, 1 is a memory cell array, 2 is a word driver, 3 is a row decoder section, 4 is a sense amplifier section, and 5 is an I / O.
Switch section, 6 is a column decoder section, 7 is a row address buffer, 8 is a column address buffer, 9 is an output buffer, 10 is an input buffer, 11 is a transfer gate section, 12 is a data register section, 13 is a block decoder, 40 is Sense amplifier, 50 is an I / O switch, 60 is a column decoder, 110 is a transfer gate, 120 is a data register, 140 is a sub data register, BL, ▲ ▼ is a bit line pair, D, is a data line pair, φ is a control Signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A plurality of memory cells that are arranged in a plurality of rows and a plurality of columns, each constituted by one transistor element and one capacitor element, and store information; and arranged in a plurality of rows and each arranged in a corresponding row. A plurality of word lines to which a plurality of memory cells are connected; a plurality of bit line pairs to which a plurality of memory cells arranged in a corresponding column are connected; and a plurality of bit lines to which a plurality of memory cells arranged in a corresponding column are connected. Is connected to the bit line pair of the corresponding column and senses the potential difference appearing on the bit line pair of the corresponding column.
A main memory having a plurality of sense amplifiers for amplifying, a cache memory having a plurality of storage elements, storing information read from the main memory, and storing information to be written to the main memory, and the cache When the information read from the storage element of the memory is transmitted to the memory cell of the main memory, the information is deactivated, and the information read from the memory cell of the main memory and amplified by the sense amplifier is stored in the cache memory. A semiconductor integrated circuit that is activated when transmitting the data to the storage element and enhances the transmission drive capability of the information, wherein the drive capability of each sense amplifier of the main memory is lower than the drive capability of each storage device of the cache memory. apparatus. 2. 9. The main memory, wherein a plurality of memory cells are divided into a plurality of blocks in a unit of a plurality of columns, and the cache memory stores information read from the main memory in units of blocks in units of blocks. 2. The semiconductor integrated circuit device according to claim 1. 3. The cache memory has a plurality of storage blocks provided corresponding to each of the plurality of blocks of the main memory, and each of the storage blocks has information in block units from the corresponding block of the main memory. 3. The semiconductor integrated circuit device according to claim 2, which stores the following. 4. 3. The semiconductor integrated circuit device according to claim 2, wherein the plurality of storage elements of the cache memory are divided into a plurality of blocks in a unit of a plurality of columns in the same number as a plurality of columns in each block of the main memory. 5. The method according to claim 2, wherein the main memory and the cache memory are connected by a plurality of transfer gates for transferring information read from the main memory in block units to the cache memory in block units. 5. The semiconductor integrated circuit device according to claim 4. 6. 6. The semiconductor integrated circuit device according to claim 5, wherein the means for improving the information transmission driving capability is connected between the sense amplifier of the main memory and the transfer gate. 7. 7. The semiconductor integrated circuit device according to claim 1, wherein the means for improving the information transmission driving capability includes a plurality of NMOS flip-flops. 8. 7. The semiconductor integrated circuit device according to claim 1, wherein the means for enhancing the information transmission driving capability includes a plurality of CMOS flip-flops. 9. A plurality of memory cells that are arranged in a plurality of rows and a plurality of columns, each constituted by one transistor element and one capacitor element, and store information; and arranged in a plurality of rows and each arranged in a corresponding row. A plurality of word lines to which a plurality of memory cells are connected; a plurality of bit line pairs to which a plurality of memory cells arranged in a corresponding column are connected; and a plurality of bit lines to which a plurality of memory cells arranged in a corresponding column are connected. Is connected to the bit line pair of the corresponding column and senses the potential difference appearing on the bit line pair of the corresponding column.
A main memory having a plurality of sense amplifiers for amplifying, a cache memory having a plurality of storage elements, storing information read from the main memory, and storing information to be written to the main memory; and When the information read from the memory cell of the memory and amplified by the sense amplifier is transmitted to the storage element of the cache memory, the information is deactivated and the information read from the storage element of the cache memory is stored in the main memory. Means for enhancing the transmission driving capability of information by being activated when transmitting to the memory cell, wherein the driving capability of each storage element of the cache memory is lower than the driving capability of each sense amplifier of the main memory; Even while the means for increasing the transmission drive capability is inactivated, the storage element of the cache memory is It is activated to store the information which has been amplified by the sense amplifier, a semiconductor integrated circuit device. 10. 9. The main memory, wherein a plurality of memory cells are divided into a plurality of blocks in a unit of a plurality of columns, and the cache memory stores information read from the main memory in units of blocks in units of blocks. 10. The semiconductor integrated circuit device according to claim 9. 11. The cache memory has a plurality of storage blocks provided corresponding to each of the plurality of blocks of the main memory, and each of the storage blocks has information in block units from the corresponding block of the main memory. 11. The semiconductor integrated circuit device according to claim 10, which stores the following. 12. 11. The semiconductor integrated circuit device according to claim 10, wherein the plurality of storage elements of the cache memory are divided into a plurality of blocks in a unit of a plurality of columns in a number of columns in each block of the main memory. 13. The main memory and the cache memory,
13. The semiconductor according to claim 10, wherein the semiconductor memory device is connected by a plurality of transfer gates for transferring information read from the main memory in block units to the cache memory in block units. Integrated circuit device. 14． 14. The semiconductor integrated circuit device according to claim 13, wherein the means for improving the information transmission driving capability is connected between the cache memory and the transfer gate. 15. The means to increase the information transmission drive capability is to use multiple NMOS
15. The semiconductor integrated circuit device according to claim 9, further comprising a flip-flop of a type. 16. The means to increase the information transmission drive capability is multiple CMOS
15. The semiconductor integrated circuit device according to claim 9, further comprising a flip-flop of a type.