JP2660134B2 - Control device for floppy disk drive controller and floppy disk drive provided with the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a controller for a floppy disk drive controller, and more particularly, to the detection of an abnormality in the controller.

[0002]

2. Description of the Related Art A floppy disk drive controller (hereinafter referred to as FDDC) is an interface between a CPU and a floppy disk drive (hereinafter referred to as FDD), and controls the FDD itself for writing and reading data on a floppy disk. And control the data format on the floppy disk.

The configuration of the FDDC is roughly divided into a CPU interface, a controller / formatter unit, and an FDD interface. The CPU interface controls transmission and reception of commands, status, track addresses, sector addresses, and the like and data transfer. Further, the controller / formatter unit controls writing and reading of data according to the positioning control and format of the head.

By switching the setting of the FDDC, specifications such as the recording density required for the FDD can be satisfied. As a method of switching the setting of the FDDC, each bit address and FDDC are stored in a memory such as a PROM. A method has been proposed in which binary setting data in which the above settings are made to correspond one-to-one is stored in advance, and the setting data is supplied from the PROM to control the FDDC (see FIG. 4).

[0005]

As described above, the PROM
In the configuration in which the setting data is stored in the FDDC and the FDDC is set, the versatility is higher than in the case where the setting of the FDDC is performed mechanically (for example, switching by a changeover switch). Cannot be detected, so that the PROM itself or P
There has been a problem that a malfunction may occur if an abnormality occurs for some reason when supplying data from the ROM.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to control an FDDC capable of easily and surely detecting an abnormality in setting data and preventing a malfunction of the FDDC. Providing equipment , and
And an FDD having the same.

[0007]

According to a first aspect of the present invention, there is provided a floppy disk drive controller for controlling the operation of a floppy disk drive controller by supplying a control command stored in a memory in advance. A control circuit for calculating a parity of a control command supplied from the memory, and comparing the calculated parity with a value of a parity bit previously added to the control command, and the two do not match. A comparison circuit for outputting a signal for resetting the operation of the floppy disk drive controller. According to a second aspect of the present invention, there is provided a floppy disk drive, comprising: an arithmetic circuit for calculating a parity of a control command supplied from a memory; and an arithmetic circuit for calculating the calculated parity and a value of a parity bit previously added to the control command. comparison, characterized in that it comprises a control device of the floppy disk drive controller and a comparator circuit which both outputs a signal for resetting the operation of full lock <br/> floppy disk drive controller does not match.

[0008]

As described above, the control device of the FDDC according to the present invention performs a parity check of the setting data supplied from the memory to detect whether or not the setting data is abnormal, thereby preventing the FDDC from malfunctioning.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
A preferred embodiment of the control device of C will be described.

FIG. 1 shows a data format of setting data stored in a memory such as a PROM in this embodiment. As described above, the setting data is in a format such that each setting of the FDDC corresponds to each bit address on a one-to-one basis.
And a bit A ₀ to A ₆ (see FIG. 1 (A)). In the present embodiment, a 1-bit parity bit P ₀ is added to the 7-bit control command and stored as setting data in a memory such as the PROM 10. Various methods can be used to calculate the parity bit P ₀ , but in this embodiment, the setting data A ₀ to
The number of "1" of the A ₆ is a parity bit "0" when an odd number of "1" is set as the parity bit "1" when an even number. Therefore, in the case of the setting data shown in FIG. 1A, the number of “1” is three (odd number), and the parity bit P ₀ is set to “0”.

The setting data is stored in the PROM 10 in a format in which the 1-bit parity bit is added to the 7-bit setting data, and the setting data is supplied to the FDDC 12. The FDDC 12 controls the FDD based on the supplied setting data.
In the present embodiment, whether or not the supplied data is normal is detected by a parity check, and the operation of the FDDC 12 is stopped when the data is determined to be abnormal.

FIG. 2 shows a detection circuit for performing a parity check in this embodiment, and FIG. 3 shows a timing chart of each part of the detection circuit. The detection circuit in FIG. 2 includes an operation unit that performs a parity operation, and a comparison circuit that compares the calculated parity with the value of the parity bit. The arithmetic circuit includes a 3-bit binary counter 20, an AND gate 22 for calculating AND of each bit of the binary counter 20,
The delay circuit 24 generates a clock signal of a flip-flop, which will be described later, from the output of the D gate 22. The comparison circuit also includes a D-FF 30 for extracting a parity bit from the setting data and an EX-O 30 for comparing the calculated parity with the value of the extracted parity bit.
It comprises an R gate 32.

The detection circuit according to the present embodiment has such a configuration, and the operation of the detection circuit will be described below with reference to the timing chart of FIG.

FIG. 3 shows a 3-bit binary counter 20.
, A clock signal having a frequency f indicated by CLK is input, and the binary counter 20 is counted up one by one with this clock signal CLK. Binary counter 2
The output of each bit Qa, Qb, Qc of 0 is AN
The signal is input to the D gate 22, and AND is calculated. Since the binary counter 20 is sequentially incremented from (000) to (111), “1” is output from the AND gate 22 every eight cycles (8 bits) of the clock. FIG. 3B shows an output waveform from the AND gate 22.

Part of the output (b) from the AND gate 22 is input to one input terminal of the NAND gate 23.
An inverted output of CLK is input to the other input terminal of the NAND gate 23. Therefore, a waveform as shown in FIG. 3A is output from the NAND gate 23, and this output is inverted and input to the reset terminal of the T-FF 26.

On the other hand, the other of the outputs from the AND gate 22 is input to the delay unit 24. The delay unit 24 delays the input and output by ４ of the cycle of the clock CLK and outputs the delayed output. Accordingly, the output from the delay unit 24 has an output waveform (d) obtained by delaying the output of (b) in FIG. 3 by １ ／ of the clock cycle. And this output (d) is D-FF
28 and the clock terminal CK of the D-FF 30.

On the other hand, the setting data DA from the PROM 10
TA is the trigger terminal of the T-FF 26 and D of the D-FF 30
Input to the terminal. FIG. 3 shows the waveform of this setting data as D
ATA, and in this example, (1010
0100). here,
As described above, 7 bits (1010010) are a valid data portion, and the remaining 1 bit (0) is a parity bit. Then, such setting data DATA is TF
When input to F26, the inverted output terminal Qbar outputs a waveform as shown in FIG. 3 (c). That is, as is well known, the T-FF 26 is a flip-flop that changes its current state, that is, the output, at the rising edge of the pulse. Output, DATA
Output terminal Qbar at the rising edge (next 1) of the next pulse
Output 1 from Therefore, when there is an odd number of 1s of DATA, the inverted output terminal Qbar of this T-FF 26
Is 0, while 1 is output from the inverted output terminal Qbar of the T-FF 26 when there is an even number of 1s in the DATA. Therefore, D is calculated by the T-FF 26.
It is understood that the 7-bit parity of the ATA is calculated and output. As described above, the T-FF2
6, the inverted output of the output from the NAND gate 23, that is, a waveform in which a pulse is output after a half cycle of the eighth bit is also input. Therefore, as shown in FIG.
The output from 6 is reset after the eighth half-cycle. The output (c) from the T-FF 26 is D-
The signal is input to the D input terminal of the FF.

On the other hand, as described above, the setting data DATA
Is also input to the D input terminal of the D-FF 30. These D
As described above, a predetermined amount (1/4 of the clock signal CLK) is applied to the clock terminals CK of the FFs 28 and 30 by the delay unit 24 as described above.
The pulse signal (d) for every 8 bits, which is delayed, is input. Accordingly, an output corresponding to the number of 1s in the 7 bits of the setting data DATA (0 for an odd number, 1 for an even number) is output from the non-inverting output terminal Q of the D-FF 28, and D- From the non-inverting output terminal Q of the FF 30, the eighth bit of the setting data DATA, that is, the value of the parity bit is output. And D-FF28, 30
Are both input to the EX-OR gate 32. EX
The -OR gate 32 is a logic gate that outputs 0 when the input values are equal, and outputs 1 when the input values are different. Therefore, the output from the D-FF 28 (that is, the parity in the 7 bits of the setting data DATA) and D
Output from the FF 30 (that is, the setting data DATA
Is output, when the parity bit value of the 8th bit is equal, that is, when there is no abnormality in the parity, and 1 is output when both outputs do not match, that is, when there is an abnormality in the parity. . When 1 is output, this is supplied to the FDDC as a reset signal.

As described above, in this embodiment, it is possible to easily detect whether or not an abnormality has occurred in the setting data by checking the parity of the setting data. If an abnormality is detected, the reset signal is output. Is supplied to the FDDC to stop its operation, thereby preventing a malfunction.

[0020]

As described above, according to the present invention, the controller child floppy disk drive controller according to the present invention
According to the floppy disk drive equipped with the
The abnormality of the setting data supplied from the memory such as OM can be prevented reliably detected and erroneous operation.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a format of setting data according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a detection circuit in the embodiment.

FIG. 3 is a timing chart of a detection circuit in the embodiment.

FIG. 4 is a block diagram showing a control method of a conventional floppy disk drive controller.

[Explanation of symbols]

10 PROM 12 FDDC (Floppy Disk Drive Controller)

Claims (2)

(57) [Claims] 1. A control device for a floppy disk drive controller for controlling the operation of a floppy disk drive controller by supplying a control command stored in a memory in advance, wherein a parity of the control command supplied from the memory is calculated. And comparing the calculated parity with the value of the parity bit added beforehand to the control command, and if the two do not match.
Operation of the floppy disk drive controller
And a comparison circuit for outputting a signal for resetting the operation of the floppy disk drive controller. Wherein <br/> floppy disk drive, characterized in that it comprises a control device of the floppy disk drive controller of Claim 1, wherein.