JP2658578B2 - Programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller having a process step language (SFC) executing means as a user program.

[0002]

2. Description of the Related Art In recent years, programmable controllers (hereinafter, referred to as PCs) have become widespread, and are now being used in complicated and sophisticated control fields. Various forms of languages have come to be used as programming languages.

[0003] However, in the conventional PC, although various types of languages mainly used for logic control are used as programming languages, they are not sufficient for the recent increase in size and complexity of systems. And could not follow software engineering concepts such as quality control and reuse of PC programming languages.

Therefore, in recent years, International Electrotec
The hnical Commission (hereinafter referred to as IEC) has reviewed the PC programming language, and has been able to express the process step in the conventional ladder language description format, and to use a structured step programming language (Sequential Function Chart) SFC) and drafted the standard.

[0005] This involves putting the entire program into a number of "steps".
Is a graphic language that is programmed in such a way that each process is divided into one or more "processes".
It is based on process step-type control.

In the SFC, programming is performed by combining a "transition condition" inserted between each process and a process associated with each process.

[0007]

However, in the above-described PC using the conventional SFC, when it is necessary to stop a certain process step in the program and reset the load, there are the following problems. .

(1) First, in the processing method as described above, in order to stop the execution of a certain step, the step itself must be deactivated and the step must be transited to the next step. If an emergency stop or the like is required without being stopped, quick processing cannot be performed.

(2) The SFC is programmed by combining processes and transition conditions between processes.
Since the description method is simple, the redundancy of the program is required in order to express complicated control such as the stop of the process, which impairs the high visibility that is a feature of the process stepping type language, and also reduces the program capacity. This leads to an increase in capacity for programming the redundant part, and also requires extra work steps.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to program a stop and reset operation for a certain process portion in a program in a simple form for a user. An object of the present invention is to provide a programmable controller that enables the above.

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention divides the entire user program for each process, and executes an SFC in which step-by-step control is performed under transition conditions between processes. In a programmable controller having means, during a program process, a plurality of related processes are formed into one chart to form a subchart, and an upper process for stopping and resetting the entire subchart is provided. The stop and reset are executed by a stop and reset command for the upper process of the subchart.

[0012]

According to the present invention, when an execution stop and a reset are commanded to an upper process of a hierarchical process step type program, the entire subchart process included in the lower process of the upper process is also stopped and reset. Thus, the stop and reset commands need only be issued to the upper steps. Therefore, it is possible to reduce the capacity of the emergency stop program and to speed up the emergency stop process.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an entire configuration of an embodiment to which the present invention is applied.

First, the configuration will be described. The CPU 11 is composed of a microprocessor and controls the entire apparatus.

The input / output (I / 0) memory 12 is a memory for storing the state of the input / output circuit (I / 0) 17 input or output via the interface (i / f) 16.

The user program memory 1 is a memory that stores a process information table for the number of processes and a head address of each process.

The user program memory 2 is a memory that stores transition condition information tables for the number of transition conditions and the respective start addresses.

The user program memory 3 is a memory that stores a processing program representing a process in a process and a head address of each.

The user program memory 4 is a memory that stores a transition condition program representing a transition condition and the respective start addresses.

The system program memory 13 includes a CPU
11 is a memory that stores a system program for controlling the CPU 11.

The work memory 14 is a memory used as a work area for controlling the entire PC.

Although the user program memory is divided into four in this example, it may be integrated into one.

The above is the basic configuration of the present embodiment. Next, its operation will be described.

FIGS. 2 to 7 are charts showing an example of the process step type program by the SFC. FIG. 2 is an overall chart, and FIGS. 3 to 7 are partial detailed charts of FIG.

First, the outline of SFC, which is a process stepping language, will be described with reference to the overall chart shown in FIG. 2. The SFC divides the entire program into a number of "processes" (shown by A). A graphical language in which one process is divided into one or a plurality of "processes" (indicated by B), and is programmed based on process step-type control.

That is, programming is performed by combining a "transition condition" (denoted by C) inserted between the steps and a process B accompanying the step A.

As shown in the figure, in the SFC, each process A is represented by a box shape, and transition conditions C between the processes are represented by horizontal lines. Further, the process B accompanying each process A is also represented in a box shape.

Next, the characteristics of the “step”, “process”, and “transition condition” will be briefly described.

A "process" has an active (active) or inactive (inactive) logic state. When the process is in the active state, "processes" related to the "process" are sequentially executed. On the other hand, when in the inactive state, the processing in the “step” is not executed. 1 for “process”
If the “process” is not related at all, “wait” is set until the “transition condition” for the “process” is satisfied. A “process” always has a unique process number, and a plurality of “processes” having the same process number cannot be used. There is no “step” without a step number.

Next, “processing” is associated with 0 or more “processes”. A “step” to which no “processing” is related can be used as a “dummy” that does not operate even when it is activated. “Process” is turned ON and OFF according to the active or inactive state of the “process” to which the “process” belongs. A “process” always has a unique process number, and a plurality of “processes” having the same process number cannot be used. Further, there is no “process” without a process number.

There is only one "transition condition" between "step" and "step", and represents a connection condition between "step" and "step". Then, when the condition of the “transition condition” under the “process” in the active state is satisfied, the “process” in the currently active state becomes inactive, and the next “process” becomes active. As described above, the “transition condition” plays a role of controlling the flow of control from “process” to “process”. This “transition condition” always has a unique transition condition number. Then, a plurality of “transition conditions” having the same transition condition number cannot be used. There is no “transition condition” without a transition condition number.

Next, the SFC will be described with reference to FIGS.
Will be described.

First, FIG. 3 shows the step step operation. Step 1 is in an active state, and processing 1 and processing 2 are performed.
Is executed, when the transition condition 1 which is the execution transition condition of the process 1 and the process 2 is satisfied, the process 1 is in an inactive state, and the process 2 is in an active state. Accordingly, the execution of the processing 1 and the processing 2 as the processing of the step 1 is interrupted, and the execution of the processing 3 as the processing of the step 2 is started. Then, the execution of the process 3 is repeated until the process 2 becomes inactive.

Next, FIG. 4 shows a selective branch operation. When step 2 is in an active state and processing 3 is executed, transition condition 2 which is an execution transition condition between step 2 and step 3 is shown. Is satisfied, or when transition condition 3, which is an execution transition condition of step 2 and step 4, is satisfied, step 2 is in an inactive state, and the process proceeds to the next step. When the transition condition 2 is satisfied, the active state of the step 2 shifts to the step 3, the execution of the processing 3 is interrupted, and the execution of the processing 4 is started. This processing 4
Is repeated until transition condition 4 is satisfied.

Next, FIG. 5 shows a parallel branch operation. When step 4 is in an active state and step 5 is executed, the execution transition condition between step 4, step 5 and step 6 is set. When a certain transition condition 5 is satisfied, step 4 is in an inactive state, and steps 5 and 6 are simultaneously in an active state. Accordingly, the execution of the process 5 as the process 4 is interrupted, and the process 6 as the process 5 and the process 7 as the process 6 start to be executed. The execution of the processing 6 is repeated until the transition condition 6 is satisfied.
The execution of the process 7 is repeated until the transition condition 7 is satisfied.

Next, FIG. 6 shows the parallel merging operation. The transition from step 5 to step 7 and the transition from step 6 to step 8 are the same as those in FIG. However, the transition from step 7 to step 9 and step 8 to step 9 is as follows. That is, the transition to the step 9 is performed in the steps 7 and 8
Are active only when the transition condition 8 is satisfied. In this case, Step 7 and Step 8 are inactive simultaneously, and Step 9 is active. Thus, the process 8 as the process 7 and the process 9 as the process 8 are interrupted, and the process 10 as the process 9 starts to be executed. The execution of the process 10 is repeated until the transition condition 9 is satisfied.

Next, FIG. 7 shows the merging operation from the selective branch, in which the transition operation from step 3 to step 10 is performed.
The transition operation from step 9 to step 10 is the same as in FIG. 3, and operates separately.

The above is the basic operation of the SFC. By the way, the following user programs (1) to (4) are stored in the user program memories 1 to 4 in order to execute the above processing.

FIG. 8 shows the contents of the user program (1) stored in the user program memory 1. As shown in FIG. 8, the user program (1) is stored in the process information table vector 20. And a process information table storage area 230 in which (n + 1) process information tables 23 for the number of processes are stored.

FIG. 9 shows the details of the process information table 23. One process information table 23 is provided for each process, and each table has a process number 24, the number of processes in process 25, The processing number 26, the number of transition conditions 27 when moving to the next step, and their transition condition numbers 28 are written.

In the figure, reference numeral 29 denotes a binary display column, in which 1 is written in advance in the case of a step which becomes active at the start of the program operation.

In this example, each process information table 2
Although the binary display field 29 is provided for each of the three, a separate table may be provided which collects only the steps that become active at the start of the program operation.

When the program is executed, the process information table 23 is read and processed in units of one table as needed.

Next, FIG. 10 shows the details of the process information table vector 20. The process information table vector 20 stores the start address 21 of each table for the number of processes (n + 1). At the time of execution, the corresponding process information table 23 is read with reference to the head address 21 of each table stored in the process information table vector 20.

Next, FIG. 11 shows the user program memory 2
3 shows the contents of the user program (2) stored therein. As shown in FIG.
Are provided with a transition condition information table vector storage area 300 in which the transition condition information table vector 30 is stored, and a transition condition information table storage area 330 in which the transition condition information tables 33 for the number of transition conditions (m + 1) are stored. ing.

FIG. 12 shows the details of the transition condition information table 33.
Is provided for each transition condition, and in each transition condition information table 33, a transition condition number 34, the number of preceding steps 35 connected before each transition condition, the preceding step number 36, and connected after each transition condition. The number 37 of subsequent steps and the number 38 of subsequent steps are written.

The transition condition information table 33 is read and processed in units of one table as needed when executing a program.

FIG. 13 shows the details of the transition condition information table vector 30. The transition condition information table vector 30 stores the start address 31 of each table by the number of transition conditions (m + 1). At the time of program execution, the corresponding transition condition table 33 is read with reference to the start address 31 of each table specified in the transition condition table vector 30.

FIG. 14 shows the user program memory 3
3 shows the contents of the user program (3) stored in the processing program vector storage area 400 in which the processing program vector 40 is stored, as shown in FIG. A processing program storage area 430 in which processing programs 43 for (p + 1) are stored is provided.

FIG. 15 shows an example of the processing program 43, which is shown by a ladder chart or the like.

FIG. 16 shows the details of the processing program vector 40. The processing program vector 40 stores the start address 41 of each processing program 43 by the number of processing programs (p + 1). At the time of execution, the corresponding processing program 43 is read out in units of one program while referring to the start address 41 stored in the processing program vector 40.

FIG. 17 shows the user program memory 4
3 shows the contents of the user program (4) stored therein. As shown in FIG.
Is provided with a transition condition program vector storage area 500 in which the transition condition program vector 50 is stored, and a transition condition program storage area 530 in which the transition condition programs 53 for the number of transition conditions (m + 1) are stored.

FIG. 18 shows an example of the transition condition program 53, which is shown by a ladder chart or the like.

FIG. 19 shows the details of the transition condition program vector 50. In the transition condition program vector 50, the start addresses 51 of each transition condition program are stored by the number of transition conditions (m + 1). At the time of program execution, the corresponding transition condition program 53 is read out in units of one program with reference to the start address 51 stored in the transition condition program vector 50.

FIGS. 20 to 23 show user programs (1) to (4) when the SFC program shown in FIGS. 2 to 7 is stored as codes in four user program memories 1 to 4. It is the contents of.

FIG. 20 shows the contents of the user program (1), and FIG. 21 shows the contents of the user program (2).
FIG. 22 shows the contents of the user program (3), and FIG. 23 shows the contents of the user program (4). These contents are already described with reference to FIGS.
Since the contents are the same as those in FIG. 18, the duplicate description will be omitted.

The above is the basic operation of the SFC employed in this embodiment and the contents of each user program.

Incidentally, an emergency stop may be required during the execution of the program. In this case, as described above, a very complicated program is required to individually stop and reset an arbitrary process.

Therefore, in the present embodiment, a series of related steps in the program are collectively formed as a subchart, and the upper step is provided, and the upper step is stopped and reset to lower the lower step. The stop and reset can be applied to all the steps constituting the subchart.

It should be noted that the process numbers and process numbers used in the following description have no relation to the process numbers and process numbers used in the description so far, so they will be omitted in advance.

FIG. 24 is a main chart of the SFC used in this embodiment. In FIG. 24, steps 1 and 3 are steps having the same functions as those described above, and I do not have a chart. However, step 2 is a higher step having the subchart 10.

FIG. 25 is a detailed view of the above subchart 10. When the program is executed, step 1 shown in FIG.
At the stage when the active state of step 2 has transitioned to step 2, step 10 shown in the figure becomes active. Thereafter, step 2 does not transition to step 3 until step 17 becomes active.

Since the process step chart having the hierarchical structure as described above is a known technique in a process step type language such as GARAFCET, its description method and the like will not be described in detail here.

The above is the contents of the SFC having a hierarchical structure employed in this embodiment. Hereinafter, a method for resetting each step having such a configuration will be described in detail.

First, when resetting a specific step, a step designation command 5 is used as shown in FIG. The process designation command 5 is stored in the user program (1), and the process designation command is executed by writing a process number for resetting to the operand 6 of the command 5.

Therefore, as shown in FIG. 27, in the instruction program, when two process designation instructions 5 are provided, when 1 is written to the operand 6, the contact A is turned on and the reset operation for the process 1 is performed. As a result, the load associated with step 1 is reset.

On the other hand, when 2 is written to the operand 6, the contact B is turned on, and the reset operation is performed on the entire subchart 10, which is a lower process of the process 2. As a result, the load associated with the entire process of configuring the subchart 10 is reset.

Here, the procedure for resetting one step, such as the resetting operation for step 1, is well known in the art, and a description thereof will be omitted. Will be described.

First, a reset end storage table 7 as shown in FIG. 28 is provided in the work memory 14. When the MAX value of the process number is N, one row of 16 is stored in the step number corresponding to each process number. Bit by bit is reserved.

That is, FIG. 29 is a detailed view of FIG. 28, and one bit is secured for one process in the direction from DO to D15.

At the time of execution of the name instruction, each bit is cleared to 0, and the corresponding bit is turned on and set to 1 each time one step of reset is completed.

Here, the case where there is a reset command for the upper step 2 and the sub-chart 10 as shown in FIG. 25 which is the lower step is reset will be described. The steps are reset one by one in the connection order with reference to the process information table 23 and the transition condition information table 33.

When the reset is completed, the corresponding bit of the reset end storage table 7 is set to "1".

In this case, the work memory 14 is provided with a reset queue table 8 as shown in FIG. 30, and the queue table 8 is provided with a current processing pointer column 8a and a reset processing work area 8b. Have been.

When the reset for steps 10 and 11 is completed, as shown in (1) and (2) of FIG. 31, writing to the queue table 8 is performed. Nothing is written in the reset processing work area 8b, and thus 0 is written in the current processing pointer column 8a.

If there is a parallel branch or a selective branch on the chart, only the first step in the process information table is reset, and the remaining step numbers are written in the reset processing work area 8b. Is written in the pointer column 8a as the current processing pointer.

Therefore, there is a branch from the process 11 to the process 12, the process 14, and the process 16, but in this case, the process information table 23 stores the process 12, the process 14, and the process 16 in this order ( First, the process 12 is reset, and as shown in FIG. 31C, the process numbers of the processes 14 and 16 are written in the reset processing work area 8b, and the current process pointer is set to 2. .

Next, as shown in (4), the reset processing in step 13 is performed. In this case, the state of the queue table 8 does not change.

By the way, since the step 13 is a sub-chart end step, the step following the step 13 returns to the step 12, but since the step 12 has already been reset, the steps in the reset end storage table 7 12 is 1.

Accordingly, among the remaining processes written in the queue table 8, the reset process of the process 14 having the earlier storage order in the process information table 23 is performed.

In this case, as shown in FIG. 31 (5), since there is one remaining process on the queue table 8, the pointer value is incremented to 1.

Next, as shown in (6), the reset processing of step 15 is performed.
Since this is a subchart end process, the queue table 8
The reset processing is continued from step 16, which is the remaining step written in step (1).

When the reset process of step 16 is completed, there is no remaining process written in the reset work area 8b, so that the current process pointer is set to 0 and the process proceeds to the reset process of step 17 as shown in (8). .

Here, since the step 17 is a sub-chart end step like the steps 13 and 15, the reset processing is to be continued from the remaining steps written in the queue table 8, but the current execution pointer is 0. Since there is no remaining process, the reset process ends.

In the above description, the case in which the process is reset is described. However, the process in which the process is stopped can be performed in exactly the same manner. In this case, the reset completion storage table 7 is replaced with the execution of each process. Status (active / inactive)
May be provided in the work area 14.

Next, FIG. 32 is a flowchart showing the overall processing procedure of the programmable controller according to this embodiment. The overall processing procedure of this embodiment will be described with reference to FIG. Then, first, a common process (step 82) is performed following the power-on initial process (step 80). Then, the operation of the user program is possible (YES in step 84), and if the operation is the first time operation (YES in step 86), the user program operation processing (step 90) is performed following the user program operation initial processing (step 88). Output circuit (I /
O) The refresh of step 17 (step 92) is performed and the process returns to the common processing (step 82).

As described above, in the present embodiment, when execution stop and reset are instructed to the upper process of the hierarchical process step type program, the entire subchart process included in the lower process of the upper process is commanded. Also, stop and reset processing is performed, and a stop and reset command may be issued only to the upper steps.

As a result, it is possible to reduce the capacity of the emergency stop program, speed up the emergency stop processing, and the like.

[0090]

As described above, according to the present invention, during a program step, a plurality of related steps are formed into one chart to form a subchart, and the upper steps for stopping and resetting the entire subchart are described. Since the correction and reset for the process in the subchart can be executed by the stop and reset command for the upper process of the subchart, the stop and reset operation for a certain process part in the program can be easily programmed for the user. And the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment to which the present invention is applied.

FIG. 2 is an explanatory diagram of an overall chart of an SFC which is a process stepping type language.

FIG. 3 is an explanatory diagram of a step increment process in FIG. 2;

FIG. 4 is an explanatory diagram of a selective branching process in FIG. 2;

FIG. 5 is an explanatory diagram of a parallel branch process in FIG. 2;

FIG. 6 is an explanatory diagram of a parallel merging process in FIG. 2;

FIG. 7 is an explanatory diagram of a merging process from the selective branching process in FIG. 2;

FIG. 8 is an explanatory diagram of a user program (1).

FIG. 9 is an explanatory diagram of a process information table.

FIG. 10 is an explanatory diagram of a process information table vector.

FIG. 11 is an explanatory diagram of a user program (2).

FIG. 12 is an explanatory diagram of a transition condition information table.

FIG. 13 is an explanatory diagram of a transition condition information table vector.

FIG. 14 is an explanatory diagram of a user program (3).

FIG. 15 is an explanatory diagram of a processing program.

FIG. 16 is an explanatory diagram of a processing program vector.

FIG. 17 is an explanatory diagram of a user program (4).

FIG. 18 is an explanatory diagram of a transition condition program.

FIG. 19 is an explanatory diagram of a transition condition program vector.

FIG. 20 is an explanatory diagram in a case where a user program (1) is dropped as a code in a user program memory.

FIG. 21 is an explanatory diagram in a case where a user program (2) is dropped as a code in a user program memory.

FIG. 22 is an explanatory diagram of a case where a user program (3) is dropped as a code in a user program memory.

FIG. 23 is an explanatory diagram in a case where a user program (4) is dropped into a user program memory as a code.

FIG. 24 is an explanatory diagram of a main chart.

FIG. 25 is a detailed view of the subchart in FIG. 24.

FIG. 26 is an explanatory diagram of a process designation command stored in a user program.

FIG. 27 is an explanatory diagram of an instruction program stored in a user program.

FIG. 28 is an explanatory diagram of a reset end storage table.

FIG. 29 is a detailed explanatory diagram of the reset end storage table shown in FIG. 28;

FIG. 30 is an explanatory diagram of a reset queue table.

FIG. 31 is an explanatory diagram of a queue table for each process when executing a subchart.

FIG. 32 is a flowchart showing an overall processing procedure of the programmable controller.

[Explanation of symbols]

 1, 2, 3, 4 User program memory (1), (2), (3), (4) User program 5 Process designation instruction 6 Operand 7 Reset end storage table 8 Queue table 11 CPU 12 Input / output (I / 0) ) Memory 13 System program memory 14 Work memory 17 I / O circuit (I / 0)

Claims (1)

(57) [Claims] 1. An entire user program is divided for each process,
SFC with step-by-step control based on transition conditions between processes
In the programmable controller having the execution means of (1), during the program process, a plurality of related processes are formed into one chart to form a subchart, and an upper process for stopping and resetting the entire subchart is provided. A programmable controller characterized in that stop and reset for a process are executed by a stop and reset command for a higher-order process of the subchart.