JP2657129B2 - Insulated gate bipolar transistor and manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate bipolar transistor (IGBT) having a high breakdown voltage.

[0002]

2. Description of the Related Art An IGBT for supplying a base current of a bipolar transistor through a channel of a MOSFET.
Is attracting attention as an element having both the high-speed switching characteristics of a vertical MOSFET and the low impedance characteristics of a bipolar transistor. FIG. 7 shows the structure of a conventional IGBT.
^{A +} type buffer layer (2) and an N ⁻ type semiconductor layer (3) are formed, a P type diffusion region (4) is formed on the surface of the N type semiconductor layer (3), and an N ⁺ type source is formed on the surface. Area (5)
Are formed to form a PNPN four-layer structure. A gate electrode (6) made of polycrystalline silicon is provided on the P-type diffusion region (4) between the N-type semiconductor layer (3) and the N ⁺ -type source region (5) via a gate oxide film. Have been. Further, a P type diffusion region (4) and an N ⁺ type source region (5)
Is in ohmic contact with the source electrode.

In the conventional IGBT, an N ⁺ -type buffer layer (2) and an N-type semiconductor layer (3) are sequentially stacked on a P-type substrate (1) by an epitaxial growth method.
When the voltage becomes 0 V or more, the N-type semiconductor layer (3) is
Since it is necessary to perform the above-described lamination, the processing time becomes longer, which leads to a decrease in throughput and a disadvantage of higher cost.

Therefore, as described in Japanese Patent Application Laid-Open No. 01-253279, an N-type substrate is employed, and a region serving as an N ⁺ -type buffer layer (2) and a region serving as a P-type substrate (1) are formed by diffusion. Have been proposed. Also, a technique for bonding different kinds of wafers has been proposed.

[0005]

However, the N ⁺ -type buffer layer (2) is formed with a high impurity concentration and a narrow width so as to maintain the breakdown voltage, suppress the thyristor operation, and prevent the current capacity from being reduced. There is a need to. In the above diffusion method,
As shown in FIG. 8, the impurity concentration profile of the N ⁺ -type buffer layer (2) is sagged, and there is a disadvantage that it is difficult to form a narrow and high impurity concentration. Also, the method of bonding wafers complicates the process and is costly.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned disadvantages, and has an N ⁺ type buffer layer (12) formed on an N-type substrate (11) by an epitaxial growth method. ) On the surface of a P ⁺ type semiconductor layer (1).
3) is formed by diffusion, and N on the opposite side of the buffer layer (12) is formed.
By forming a P-type diffusion region (14), an N ⁺ -type source region (15), and a gate electrode (16) on the surface of a mold substrate (11), a buffer layer (1) having a narrow width and a high impurity concentration is formed.
2).

[0007]

According to the present invention, since the N ⁺ -type buffer layer (12) is formed by the epitaxial method, its concentration profile can be formed uniformly and uniformly in the thickness direction. Further, the thickness of the N ⁺ -type buffer layer (12) can be easily controlled by controlling the diffusion of the P ⁺ -type semiconductor layer (13). Therefore, the buffer layer (12) having a narrow width and a high impurity concentration
Can be formed. Further, by selectively diffusing the P ⁺ type semiconductor layer (13), a universal electrode structure in which a P layer and an N layer are mixed can be easily formed.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a sectional view showing the structure of an IGBT of the present invention. (11) is the specific resistance ρ = 100 to 200Ω · c
m, an N ⁻ -type silicon single crystal substrate having a thickness of 100 to 200 μm. (12) is a specific resistance ρ = 0.01 to − formed on one surface of the N ⁻ -type substrate (11) by an epitaxial growth method.
N ⁺ type buffer layer of several Ω · cm, thickness of several μ to several + μ,
(13) is a P ⁺ -type semiconductor layer diffused and formed on the entire surface of the N ⁺ -type buffer layer (12), (14) is a P-type diffusion region formed on the surface opposite to the substrate (11), and (15) is a P-type diffusion region. N ⁺ type source region formed on the surface of the type diffusion region (14), (1
6) is a gate electrode arranged on the surface of the substrate (11) via a gate oxide film. The P ⁺ type semiconductor layer (12) has a collector electrode, a source region (15) and a P type diffusion region (1).
Emitter electrodes (source electrodes) are in ohmic contact with both of 4). The channel of the MOSFET is
It is formed on the surface of a shallow portion of the P-type diffusion region (14) sandwiched between the source region (15) and the N ^- type substrate (11).
In this IGBT, current flows from the channel of an N-channel MOSFET to the base of a PNP transistor having a P ⁺ type semiconductor layer (13) as a collector, an N ⁻ type substrate (11) as a base, and a P type diffusion region (14) as an emitter. Is supplied and operated.

FIG. 2 shows an impurity concentration profile of the substrate (11) of the present IGBT. In the present invention, since the N ⁺ -type buffer layer (12) is formed by epitaxial growth, the buffer layer (12) can be formed with a sufficiently high impurity concentration and a constant impurity concentration in the thickness direction. ^- it can be an impurity concentration of the junction between the mold substrate (11) stepwise. Further, since the epitaxial growth method can easily control the film thickness, by controlling the diffusion of the P ⁺ -type semiconductor layer (13) from the surface thereof, a buffer layer (12) having an extremely narrow width can be obtained with high precision. Can be

The method of manufacturing the IGBT of the present invention will be described with reference to FIG.
Show. First, as shown in FIG.^-Based on mold substrate (11)
After cleaning the surface,_FourEpisode using
N by the tax growth method⁺Form buffer layer (12)
And then, as shown in FIG.
Thermal diffusion of P-type impurities such as boron (B) from the surface ⁺
A mold semiconductor layer (13) is formed. At this time, adjust the diffusion depth
A few μm of buffer layer (12)
Formed. Then, as shown in FIG.^-Mold substrate
On the opposite surface of (11), a P-type diffusion region (14) and a gate electrode
Pole (16), and N⁺Forming a mold source region (15)
You. The steps after FIG. 5 are the same as those in the conventional technique.

FIG. 6 shows a second embodiment of the present invention. Since the present invention was to form a diffusion P ⁺ -type semiconductor layer (13), by performing the diffusion selectively, P ⁺
The mold semiconductor layer (13) can be formed so as to be scattered on the surface of the buffer layer (12). Then, the junction diode (1) between the deep portion of the P-type diffusion region (14) and the N ⁻ -type substrate (11) is formed.
7) can be equivalently connected in parallel between the collector of the IGBT composed of the P ⁺ type semiconductor layer (13) and the emitter of the IGBT composed of the P type diffusion region (14), and the IGBT can be connected to an inverter device such as a motor or the like. When used as a horizontal deflection device of a CRT, it can be used as a commutation diode.

[0013]

As described above, according to the present invention,
By using the N ^- type substrate (11), a high breakdown voltage IG
There is an advantage that BT can be provided at low cost. Further, the buffer layer (12) has a high impurity concentration, a small thickness,
^Since the concentration profile of the junction with the mold substrate (11) can be formed in a step-like manner, there is an advantage that the breakdown voltage of the IGBT is increased, the latch-up withstand voltage is increased, and the current capacity is increased. Further, the epitaxial growth method and the P ⁺ type semiconductor layer (13)
Has an advantage that the buffer layer (12) can be easily controlled. And further, according to the second embodiment,
Another advantage is that a structure incorporating a rectifier diode can be easily obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a diagram showing an impurity concentration profile of the present invention.

FIG. 3 is a first cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 4 is a second cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 5 is a third sectional view for explaining the manufacturing method of the present invention.

FIG. 6 is a sectional view showing a second embodiment of the present invention.

FIG. 7 is a cross-sectional view for explaining a conventional example.

FIG. 8 is a diagram showing an impurity concentration profile of a conventional example.

Claims (5)

(57) [Claims] A semiconductor substrate having a high specific resistance of one conductivity type; a high-concentration buffer layer of one conductivity type epitaxially grown on one surface of the substrate; and a high-concentration buffer layer of a reverse conductivity type formed by diffusion from the surface of the buffer layer. A concentration layer, a gate electrode, a reverse conductivity type diffusion region serving as a base formed on the opposite surface of the substrate, and a one conductivity type source region formed on the surface of the reverse conductivity type diffusion region. Insulated gate bipolar transistor. 2. The insulated gate bipolar transistor according to claim 1, wherein said high-concentration layer of the opposite conductivity type is uniformly formed on a surface of said buffer layer. 3. The insulated gate bipolar transistor according to claim 1, wherein said reverse conductivity type high concentration layer is selectively formed in an island shape on a surface of said buffer layer. 4. The buffer layer according to claim 1, wherein the buffer layer has a constant impurity concentration profile in a thickness direction.
The insulated gate bipolar transistor according to the above. 5. A step of preparing a substrate of one conductivity type having a high specific resistance; a step of epitaxially growing a buffer layer of one conductivity type with a high concentration on one surface of the substrate; Forming a high-concentration layer by diffusing impurities of a type, forming a base of the opposite conductivity type on the opposite surface of the substrate, and forming a gate electrode on the opposite surface of the substrate via an insulating film Forming an emitter region of one conductivity type on the surface of the base region .