JP2655585B2 - Data bus control circuit for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
More specifically, the present invention relates to a semiconductor integrated circuit in which a plurality of functional blocks including a central processing unit are formed on one semiconductor chip.

[0002]

2. Description of the Related Art Conventionally, in a compound semiconductor integrated circuit (compound LSI) composed of a plurality of functional blocks including a central processing unit (CPU), a data bus of the CPU is a compound L.
It is directly connected to the input / output terminal of the SI or connected to the input / output terminal of the composite LSI via a resistor as a bus buffer. FIG. 8 shows the former example and FIG. 9 shows the latter example.

In the composite LSI of FIG. 8, a data bus 102 of a CPU 101 is directly connected to a data input / output terminal 104 of a composite LSI 103. Note that 105 is the CPU 1
01 is an output terminal for outputting the read signal RD of 01 via the buffer 107, and 106 is a functional block other than the CPU. On the other hand, in the composite LSI of FIG.
Each signal line of the data bus 102 of the CPU 101 is connected to an input / output terminal 104 via a resistor r.

[0004]

In the case of the LSI shown in FIG.
External noise is directly transmitted to the data bus 10 of the CPU 101.
2, there is a problem that sufficient electrical reliability cannot be obtained. Further, in the case of the LSI shown in FIG. 9, the amount of delay of a signal propagating on the data bus 102 becomes a problem. That is, it is difficult to set the value of the resistor r so as to be suitable in any case. Further, since the signal is attenuated by the resistor r, there is a problem that the driving capability of the data bus is reduced.

An object of the present invention is to provide a semiconductor integrated circuit which can solve such a problem and can prevent intrusion of external noise without causing problems such as signal propagation delay and reduction in drive capability. .

[0006]

An object of the present invention is to provide a semiconductor chip having a plurality of functional blocks including a central processing unit having input / output terminals for exchanging data with the outside. A data bus control circuit for a semiconductor integrated circuit formed and configured above, comprising: a bidirectional bus buffer for connecting a data bus connected to the central processing unit with the input / output terminal; When the read signal output from the device becomes valid, the bus buffer
Immediately switch the signal propagation direction to the input direction, and
When the output signal becomes invalid, the signal of the bus buffer
Switching the propagation direction to the output direction after delaying the propagation direction for a predetermined time
The present invention is achieved by a data bus control circuit for a semiconductor integrated circuit, comprising a switching means. The switching
The read means is configured to output the read signal when the read signal becomes invalid.
The signal propagation direction of the bus buffer is set next to the central processing unit.
Switch to output direction with delay until rising of clock
It may be configured so as to obtain.

[0007]

In a semiconductor integrated circuit having a data bus control circuit according to the present invention, for example, a read signal becomes effective.
The signal direction of the bus buffer immediately changes to the input direction.
And the signal propagation direction of the bus buffer becomes the direction from the input / output terminal to the central processing unit, and data can be read from an external device such as a storage device. Also, when the read signal becomes invalid, the signal
The direction is switched to the output direction with a delay of a predetermined time, and the signal propagation direction of the bus buffer becomes the direction from the central processing unit to the input / output terminal, and data can be output to the outside. This allows external noise to enter the data bus
And the electrical reliability of the semiconductor integrated circuit is greatly increased.
improves. Also, if a resistor is used as the bus buffer,
No problem of propagation delay that occurs in
There is no problem like below. In addition, no read signal
If it becomes effective, switch the signal propagation direction immediately.
Do not switch, switch after a predetermined time delay.
Until the external device stops outputting the signal completely.
Even if it takes some time, the signal output from the central processing unit
Avoid collisions with signals output from external devices.
Can be.

[0008]

Next, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment of a semiconductor integrated circuit having a data bus control circuit according to the present invention. The semiconductor integrated circuit, that is, the composite LSI 3 is constituted by the CPU 1 and other functional blocks 6, and the data bus control circuit is constituted by a bidirectional bus buffer 7, a two-input AND circuit 8, and a flip-flop circuit 9. I have.

The bus buffer 7 includes eight buffer circuits 7
1 and eight buffer circuits 72, and the inputs of the buffer circuits 71 are connected to the data bus 2 of the CPU 1 respectively.
And the outputs of the buffer circuit 71 are connected to the eight input / output terminals 4 of the composite LSI 3, respectively. The input of the buffer circuit 72 is 8
The output is connected to each of the signal lines D0 to D7 of the data bus 2. All control terminals of the buffer circuits 71 and 72 are connected to the output of the AND circuit 8. The buffer circuit 71 outputs a signal to the input / output terminal 4 when a high-level control signal is supplied, and does not output a signal when a low-level control signal is supplied. On the other hand, the buffer circuit 72 outputs a signal to the data bus 2 when a low-level control signal is supplied, and does not output a signal when a high-level control signal is supplied. The arrow A in the figure indicates the signal propagation direction in the buffer circuit 7 when the CPU 1 takes in a signal from the outside, and the arrow B indicates the signal propagation direction when the CPU 1 outputs a signal to the outside.

One input of the AND circuit 8 is connected to a read signal line 10 from the CPU 1, and the other input of the AND circuit 8 is a non-inverting output terminal 9c of the flip-flop circuit 9.
It is connected to the. The data input terminal 9a of the flip-flop circuit 9 is also connected to the signal line 10, and the clock input terminal 9b is connected to the clock input line 11.

A read signal line 10 from the CPU 1 is also connected to a read signal output terminal 5 via a buffer 12, and the CPU 1 receives signals from external devices such as an input / output device and a storage device connected to the terminals 4 and 5. When reading data, an active “LOW” read signal RD is output to the signal line 10. Also, the clock input terminal 1 of the CPU 1
a is connected to the clock input line 11.

Next, the operation will be described with reference to the timing chart shown in FIG. When the CPU 1 reads data from an external device and outputs a low-level read signal RD to the signal line 10 at the timing T1, this is supplied to one input of the AND circuit 8, so that the AND circuit 8 immediately outputs the low-level signal. The signal is output to the control terminals of the buffer circuits 71 and 72. As a result, the buffer circuit 72 outputs a signal (input signal) given from the external device to the input / output terminal 4 to the data bus 2. The CPU 1 reads this signal via the data bus 2.

On the other hand, when the CPU 1 outputs data to an external device, when the read signal RD goes high at the timing T2, the flip-flop circuit 9 causes the flip-flop circuit 9 to synchronize with the rising of the clock signal CK from the clock input line 11. And a high-level signal is supplied to one input of the AND circuit 8. At this time, since the other input of the AND circuit 8 is supplied with the high-level read signal RD, the AND circuit 8 outputs a high-level signal to the control terminals of the buffer circuits 71 and 72. As a result, the buffer circuit 71 outputs a signal (output signal) from the data bus 2 to an external device via the input / output terminal 4.

In the composite LSI 3 incorporating the data bus control circuit of the above embodiment, the data bus 2 of the CPU 1 is connected to the input / output terminal 4 via the buffer 7 and
The PU 1 transmits and receives signals via the buffer 7. Therefore, noise from the outside hardly enters the data bus 2, and the electrical reliability of the composite LSI 3 is greatly improved. Then, there is no problem of propagation delay as in the case of using a resistor as a bus buffer, and further, there is no problem such as a decrease in drive capability.

In the data bus control circuit, when the read signal RD goes high, the signal propagation direction of the buffer circuit 7 is not switched immediately but at the next rising edge of the clock signal CK. Has become. That is, the read signal RD becomes high level,
Thereafter, after the holding time t has elapsed, the buffer 71 outputs a signal. Therefore, even if it takes some time after the external device receives the high-level read signal RD to completely stop sending the signal, the signal output from the CPU 1 collides with the signal output from the external device. Can be prevented.

FIG. 3 shows a modification of the first embodiment.
In this example, Z80 is used as the CPU 1, the output of the AND circuit 8 is connected to one input of the AND circuit 13 and one of the inputs of the OR circuit 14, the output of the AND circuit 13 is connected to the control terminal of the buffer circuit 71, The output of the OR circuit 14 is connected to the control terminal of the buffer circuit 72. Also, the data bus release signal BUS output from the CPU 1
AK is supplied to the other input of the AND circuit 13 and also to the other input of the OR circuit 14 via the inverter 15.

The operation of the data bus control circuit when the data bus release signal BUSAK is at the high level is the same as that of the first embodiment. Data bus release signal BUSA
When K goes low, the data bus 2 is released (floating) as shown in the timing chart of FIG. 4, and the signal supplied to the control terminal of the buffer circuit 71 goes low, so that the control terminal of the buffer circuit 72 becomes low. Becomes high level. In this state,
The LSI 3 and the external device are electrically separated from each other, and data transfer between the LSI 3 and the external device is prohibited. Therefore, in this state, the L between external storage devices and input / output devices is low.
Data transfer can be performed ignoring SI3.

Next, a second embodiment of the present invention will be described with reference to FIGS. 5, members having the same functions as the members in FIG. 1 are denoted by the same reference numerals.

In the second embodiment, the flip-flop circuit 9 is used.
The second embodiment differs from the first embodiment in that a delay element 16 is used in place of the first embodiment. As shown in FIG. 5, the input of the delay element 16 is connected to the read signal line 10, and the output of the delay element 16 is connected to the input of the AND circuit 8. As shown in the timing chart of FIG. 6, the output of the AND circuit 8 falls from the high level to the low level at the same time when the read signal RD falls from the high level to the low level. It is ready to read data. When the read signal RD rises from the low level to the high level, the output of the AND circuit 8 rises to the high level after the elapse of the holding time t determined by the delay characteristic of the delay element 16, and the CPU 1 enters a state of outputting data to the outside. . The holding time t is set to prevent the data from colliding with each other and prevent the LSI 3 and the external device from deteriorating when both the LSI 3 and the external device output data as described above. Provided.

In the data bus control circuit of the second embodiment, the holding time t is determined by the delay amount of the delay element 16 without depending on the clock signal CK. It can be set arbitrarily according to the characteristics.

FIG. 7 is a circuit diagram of a modification of the second embodiment. In this example, as in the modification of the first embodiment described above, Z80 is used as the CPU 1 and the output of the AND circuit 8 is connected to one of the inputs of the AND circuit 13 and the OR circuit 14, respectively. Output buffer circuit 7
1, and the output of the OR circuit 14 is connected to the control terminal of the buffer circuit 72. Further, a data bus release signal BUSAK output from the CPU 1 is supplied to the other input of the AND circuit 13,
To the other input of the OR circuit 14.

With such a configuration, as described above, when the data bus release signal is at the low level,
The SI3 and the external device are electrically separated, and data transfer between the LSI3 and the external device is prohibited. Therefore, in this state, LS between external storage devices and input / output devices
Data transfer can be performed ignoring I3.

[0023]

As described above, in the semiconductor integrated circuit employing the data bus control circuit of the present invention, the data bus of the central processing unit is connected to an external device via a bidirectional bus buffer. Therefore, external noise is less likely to enter the data bus, and the electrical reliability of the semiconductor integrated circuit is greatly improved. In addition, there is no problem of propagation delay that occurs when a resistor is used as a bus buffer, and there is no problem such as a decrease in drive capability. In addition, read
If the signal becomes invalid, switch the signal propagation direction.
Do not switch immediately after switching for a predetermined time.
Until the external device completely stops signal output.
Even if it takes some time, the central processing unit outputs
Prevents signals from colliding with signals output by external devices
can do.

Further, the data bus control circuit of the present invention has a very simple structure and can be used in common for all composite semiconductor integrated circuits, so that it is not necessary to consider a method of handling the data bus for each system. It is very advantageous in terms of development efficiency.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an LSI according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the LSI in FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of a modification of the LSI of FIG. 1;

FIG. 4 is a timing chart for explaining the operation of the LSI in FIG. 3;

FIG. 5 is a circuit diagram showing a configuration of an LSI according to a second embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the LSI in FIG. 5;

FIG. 7 is a circuit diagram showing a configuration of a modification of the LSI of FIG. 5;

FIG. 8 is a circuit diagram showing a configuration of a conventional LSI.

FIG. 9 is a circuit diagram showing a configuration of another conventional LSI.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Central processing unit (CPU) 2 Data bus 3 Composite LSI 4 I / O terminal 5 Read signal output terminal 6 Other functional blocks 7 Bus buffer 8, 13 AND circuit 9 Flip-flop circuit 14 OR circuit 15 Inverter 16 Delay element 71, 72 Buffer circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Katsuhiro Masui 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (56) References JP-A-58-24925 (JP, A) Real-life Sho-63 −181198 (JP, U)

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit having input / output terminals for exchanging data with the outside and having a plurality of functional blocks including a central processing unit formed on one semiconductor chip. A data bus control circuit, wherein a bidirectional bus buffer for connecting a data bus connected to the central processing unit and the input / output terminal and a read signal output from the central processing unit are enabled. When
Immediately switch the signal propagation direction of the bus buffer to the input direction.
When the read signal becomes invalid, the
Output direction after delaying the signal propagation direction of the buffer
A data bus control circuit for a semiconductor integrated circuit, comprising: a switching unit for switching the data bus direction. 2. The method according to claim 1, wherein the switching unit is configured to output the read signal.
Is invalid, the signal propagation direction of the bus buffer
Until the next clock rise of the central processing unit.
To switch to the output direction.
2. The data of the semiconductor integrated circuit according to claim 1, wherein
Tabus control circuit.