JP2650256B2 - Serial data transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Field of the Invention The present invention relates to a serial data transmission method,
The present invention relates to a serial data transmission method for efficiently transmitting data between a data processing processor, a so-called CPU, and various devices.

B. Summary of the Invention The present invention relates to a method for serially transmitting data from a so-called CPU to a plurality of devices via a serial interface circuit, according to a write / read control signal from the CPU. By outputting a status bit indicating whether or not the write / read status bit is added to the data to be transmitted and serially transmitting it together with a start bit indicating the beginning of the serial data string,
Data transmission between U and a plurality of devices can be performed in the same manner as normal writing / reading to / from a memory, and realizes high-speed serial data transmission with a simple structure.

C. Prior Art In recent years, so-called microprocessors have been used for various applications, and there is a need to transmit data to and from various devices. Data transmission methods between the microprocessor and various devices are roughly classified into parallel (parallel) transmission and serial (serial) transmission. Among these, serial transmission has advantages such as requiring less wiring. For example, in serial control of various electronic devices, serial transmission is used for data transmission to a plurality of controlled devices. I have.

FIG. 3 is a block circuit diagram for explaining a conventional example in which serial data transmission is performed between a CPU and various devices. In FIG. 3, for example, an 8-bit microprocessor is used for the CPU 51, and the data bus DB and the address bus AB of the CPU 51 are used.
And the control bus CB include a so-called ROM (read only memory) 52 and a RAM (random access memory).
Memory) 53, PIO (parallel interface) circuit 5
4 and an SIO (serial interface) circuit 55 are connected. The data input / output terminals of this SIO circuit 55
Multiple serial controlled devices, such as AD / DA converters6
1, DSP (Digital Signal Processor) 62,... Are commonly connected. In order to alternatively designate these various devices 61, 62,..., For example, an address decoder 56 connected to an address bus AB and a control bus CB is used. This is a so-called memory-mapped IO configuration, in which each CPU can be specified from the CPU 51 in the same form as ordinary memory access, and commands can be unified or simplified, which is advantageous in terms of software. It is.

D. Problems to be Solved by the Invention However, it is necessary to provide wiring for device selection from the address decoder 56 to each of the devices 61, 62,. It is necessary to provide as many as the number of devices, which complicates wiring and complicates the configuration. In addition, as an operation procedure for actually performing serial transmission, not only a step for selecting a device and a step for transmitting data via the SIO circuit 55 are required at least, but also an ordinary peripheral IC Transmission of data via the SIO circuit 55 is generally slow because it involves so-called handshake processing and the like, and high-speed data transmission cannot be performed.

The present invention has been made in view of such circumstances, and has as its object to provide a serial data transmission method capable of high-speed serial data transmission with a simple configuration.

E. Means for Solving the Problems In order to solve the above problems, the serial data transmission method according to the present invention provides data from a data processing processor to a controlled device via a serial interface circuit. In the serial data transmission method for transmitting, when writing / reading data from the processor to / from a controlled device, the serial interface circuit includes a write state / read corresponding to a write / read control signal of the processor. A status bit indicating a state is generated, and the status bit and a start bit indicating the beginning of serial data are added to the data of the predetermined bit to be transmitted, and the start bit, the data bit, and the status bit are added. It is characterized by serial transmission of bits.

F. Function Since the serial data is provided with a write / read status bit which is automatically generated in response to a write / read control similar to the memory access by the processor, a command, etc. Therefore, a control step only for instructing writing / reading can be omitted, and the speed can be increased.

G. Embodiment FIG. 1 is a block circuit diagram schematically showing a configuration used in an embodiment of the serial data transmission method according to the present invention.

In FIG. 1, for example, a CPU 10 comprising a so-called 8-bit microprocessor is provided with a write control signal W.
R, read control signal RD, memory access request signal MREQ, 1
At least output terminals for 6-bit addresses A0 to A15 and input / output terminals for 8-bit data D0 to D7 are provided. The data (including address data) from the CPU 10 is serially transmitted to a plurality of devices 11, 12,... Via a serial interface circuit 20.

The serial interface circuit 20 is mainly
Shift register 21 for converting parallel input data from CPU 10 into serial data
And an address decoder 22 for detecting addresses assigned to the plurality of devices 11, 12,.
A three-state buffer 23 for controlling the direction of data transmission to the serial interface circuit 20; a serial transmission clock;
At least a serial control circuit 24 for controlling the operation of the state buffer 23 and the shift register 21 is provided. Such a serial interface circuit 20
16-bit addresses A0 to A15 and 8-bit data D0 to D7 from the CPU 10 are input in parallel to the shift register 21,
A read / write status bit R / W and a start bit ST for serial transmission are added, and serial transmission is performed in a format as shown in FIG.

That is, in the serial transmission data format shown in FIG. 2, a start bit ST, a read / write status bit R / W, and a 16-bit address A0 to A15 are arranged in order from the beginning of the serial data string. The 8-bit data D0 to D7 are arranged via a read / write operation switching margin bit MG. This serial data string is, according to the serial transmission clock,
Serial transmission is performed sequentially from the start bit ST.

Here, the read / write status bit R / W in the format of FIG.
The AND circuit 25 obtains the logical product of the data and the memory request signal MREQ. The start bit ST is constantly supplied from the terminal 26 to the shift register 21. The write control signal WR and the memory request signal MREQ from the CPU 10 are supplied to the address decoder 22.
In addition, the read control signal RD and the 16-bit address A0 to A1
5 are supplied. When an access request (memory request) is made to an address assigned to each of the devices 11, 12,... Based on these signals, a predetermined serial transmission start signal or A trigger signal is sent to the serial control circuit 24. In the serial control circuit 24,
For example, a master synchronized with the reference operation clock of CPU10, etc.
The clock is supplied via terminal 27. From the serial control circuit 24, this master clock is output as a serial transmission clock by a predetermined number of pulses in response to the input of the trigger signal, and is supplied to the shift and register 21, and if necessary, a clock supply line l _CK Are supplied to the clock input terminals of the devices 11, 12,. This serial transmission clock can be omitted. Serial transmission data from the shift register 21, 3 through the state buffer 23 is sent to the serial transmission line l _ST, each device 11 and 12 is sent to the serial data input pin of ‥‥. In the example of FIG. 1, a bidirectional serial transmission line l _ST is assumed,
The serial data from each of the devices 11, 12, and も is also transmitted via the transmission line l _ST to the serial interface circuit 20.
However, separate serial transmission lines may be provided for data transmission and data reception, respectively.

According to the transmission method as described above, the CPU 10 only performs an operation of writing or reading data by designating an address in the same manner as during normal memory access.
Serial data transmission with each device via the serial interface circuit 20 can be realized, so that software can be simplified and data transmission can be speeded up.

The present invention is not limited to the above-described embodiment. For example, the number of bits of the CPU is not limited to 8 bits, and for example, a 4-bit CPU, a 16-bit CPU, or the like may be used. In addition, various changes can be made without departing from the spirit of the present invention.

H. Effects of the Invention According to the serial data transmission method of the present invention, the CP
Since the read / write status bits based on the read control signal and the write control signal from the U (processor) are included in the serial transmission data string and transmitted, there is no need to individually send a read or write command. Data transmission efficiency can be improved. Also, by writing or reading data by specifying the same address as during normal memory access, serial data transmission with each device via the serial interface can be realized, greatly simplifying software. Can be

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a configuration used in an embodiment of a serial data transmission method according to the present invention;
FIG. 2 is a diagram showing a format of serial transmission data in the embodiment, and FIG. 3 is a block circuit diagram for explaining a conventional example. 10 CPU (processor) 11, 12 Device under control 20 Serial interface circuit 21 Shift register 22 Address decoder 24 Serial control circuit

Claims (1)

(57) [Claims] 1. A serial data transmission method for transmitting data from a data processing processor to a controlled device via a serial interface circuit, wherein the serial interface circuit transmits data from the processor to the controlled device. write/
When reading, a status bit indicating a write state / read state according to a write / read control signal of the processor is generated, and this status bit and a start bit indicating the head of serial data are transmitted as described above. A serial data transmission method, characterized in that the start bit, the data bit, and the status bit are serially transmitted in addition to predetermined bit data to be transmitted.