JP2649382B2 - Transaction trace method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a transaction tracing method in which a central control unit of an electronic exchange traces and records a transaction used in call processing. The purpose is to be able to track and record the usage state and storage contents of transactions without squeezing, and to be added to the bus connecting the central control unit and the main storage unit, and between the central control unit and the main storage unit. In a bus trace device that records information transferred via a bus without being controlled by a central control device, a transaction capture mechanism provided in the central control device is provided with an optional device provided in a main storage device. Transaction capture detection means for detecting that an empty transaction has been captured, and transaction capture detection means When the capture of a transaction is detected, transaction position information indicating the position of the captured transaction in the main storage device held by the central control unit is extracted, and the area for occupying the captured transaction in the main storage device is set. For the transaction area setting means and the transaction area set by the capture transaction area setting means,
And a tracing means for recording information transferred by the central controller.

[Industrial applications]

The present invention relates to a bus tracing device, and more particularly to a transaction tracing method in which a central control device of an electronic exchange traces and records transactions used in call processing.

2. Description of the Related Art In an electronic exchange, a bus trace device that records information transferred between a central control device and a main storage device is used as means for tracking the operation state of the central control device.

On the other hand, the central control unit that controls the call processing of the electronic exchange, in order to process a large number of calls simultaneously in parallel, stores an arbitrary free space in a plurality of storage areas called transactions in the main storage device. The transaction is captured at the start of the process, control information in each process of each call is stored and stored, and when the process is completed, the transaction is released again to return to an empty state.

Therefore, tracking the use state and stored contents of the transaction is effective for tracking the call processing status of the electronic exchange.

[Conventional technology]

A conventional bus trace device does not have a function of tracking the use state and storage contents of a transaction provided in a main storage device of an electronic exchange.

Therefore, in order to track the use state and storage contents of the transaction, a trace program for tracking and recording the use state and storage contents of the transaction is added to the call processing program executed by the central controller for call processing, Each time the central controller captures a transaction and stores / updates each control information, it records the transaction usage status and storage contents in the trace-dedicated area in the main memory, and stores it until the transaction is released. There was no control information other than recording.

[Problems to be solved by the invention]

As is apparent from the above description, since the conventional bus trace device does not have a transaction trace recording function, a transaction trace program is added to the call processing program executed by the central control unit, and the transaction usage state is changed. In addition to recording the stored contents in the course of the call processing, not only the call processing capability of the central control unit is reduced, but also the storage area of the main storage device may be squeezed.

SUMMARY OF THE INVENTION It is an object of the present invention to enable tracking and recording of a transaction use state and storage contents without squeezing a call processing capability of a central control unit and a storage area of a main storage device.

[Means for solving the problem]

 FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 1 is a central control unit, 2 is a main storage unit, 4 is a bus connecting the central control unit 1 and the main storage unit 2, 7 is a bus trace unit, and 11 is a transaction provided in the central control unit 1. The capture mechanism, 21 is a transaction provided in the main storage device 2, and _aTR is transaction position information indicating the position in the main storage device 2 of the transaction captured by the transaction capture mechanism 11.

Reference numeral 100 denotes a transaction capture detecting unit provided in the bus trace device 7 according to the present invention.

200 is a capture transaction area setting means provided in the bus trace device 7 according to the present invention.

Reference numeral 300 denotes a tracing means provided in the bus tracing device 7 according to the present invention.

[Action]

The bus trace device 7 is added to the bus 4 that connects the central control device 1 and the main storage device 2, and transmits information transferred between the central control device 1 and the main storage device 2 via the bus 4. Recording is performed without being controlled by the central control device 1.

The transaction capture detecting means 100 detects that the transaction capture mechanism 11 in the central control device 1 has captured any free transaction 21 in the main storage device 2.

The capture transaction area setting means 200 extracts the transaction position information _aTR held by the central controller 1 when the transaction capture detection means 100 detects the capture of the transaction 21, and extracts the transaction position information _aTR from the main storage device 2 of the captured transaction 21. Set the area occupied by.

The tracing means 300 records information transferred by the central control device 1 for the area of the transaction 21 set by the capture transaction area setting means 200.

Therefore, the bus trace device does not squeeze the processing capacity of the central control device and the storage area of the main storage device,
The transaction captured by the central control unit is detected, and the use state and the stored content of the transaction can be tracked and recorded.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Second
FIG. 3 is a diagram illustrating an electronic exchange to which the present invention is applied, FIG. 3 is a diagram illustrating a bus trace device in FIG. 2, and FIG. 4 is a diagram illustrating a condition determining circuit in FIG. FIG. 5 is a diagram showing a transaction trace process according to an embodiment of the present invention. The same reference numerals indicate the same objects throughout the drawings.

3 to 5, the transaction capture detecting means 100 in FIG. 1 is used as the condition determination circuit 72 in FIG. 3 and the steps S1 to S3 shown in FIG.
And a control unit 73 for executing S9 is provided. As the capture transaction area setting means 200 in FIG.
A condition determining circuit 72, a console control unit 75, and a control unit 73 for executing steps S4 to S6 shown in FIG. 5 are provided.
A control unit 73 and a trace control unit 74 for executing steps S7 and S8 shown in the figure are provided.

In FIG. 2, a central control unit (CC) 1 for controlling the call processing of the electronic exchange, a call processing program executed by the central control unit (CC) 1, a main storage device (MM) 2 for storing data, various input / output devices Data channel device (DCH) 3 for connecting
Are duplicated and connected via a bus 4, and the duplicated buses 4 are connected to each other via a bus coupling circuit (BC) 5 provided for each.

In addition, a common console (BC
NS) 6 is connected.

The main storage device 2 is provided with a number of transactions (TR) 21 each having a predetermined storage capacity _LTR and corresponding to the traffic volume.

On the other hand, a bus trace device 7 is provided to trace information transferred between the central control device 1 and the main storage device 2 via the bus 4, and is connected to the bus 4 and the basic console 6.

In FIG. 3, a bus tracing device 7 is connected to a bus 4 and extracts an address a, data d, status information s, and control information c (the above information is collectively referred to) transferred on the bus 4. A condition determining circuit 72 for determining whether or not the information extracted by the processor interface 71 matches a predetermined trace condition; a control unit 73 for setting the trace condition in the condition determining circuit 72; Is composed of a trace control unit 74 for storing information determined to meet the trace condition in the trace memory 76, and a console control unit 75 for transmitting and receiving various control information to and from the central control device 1 via the basic console 6. You.

The bus trace device 7 includes a plurality of condition determination circuits.
72 are provided.

In order to cause the bus trace device 7 to track the use state and the stored contents of the transaction 21, the operation panel (not shown) instructs the control unit 73 to start the address a _HP of the transaction capture program THP22 in the main storage device 2,
A command for transaction tracing including the storage capacity _LTR of the transaction 21 to be traced is input (step S1 in FIG. 5).

The control unit 73 stores the start address a _HP included in the command in a register 724-1 provided in one of the condition determination circuits 72 (hereinafter, a specific condition determination circuit is referred to as 72-1 and the like). Then, an all mask code is set in the registers 725 and 726 (step S2).

On the other hand, the address matching circuit 721-
1, the address a transferred via the bus 4 is transmitted from the processor interface 71, and the data d transferred via the bus 4 is transmitted from the processor interface 71 to the data matching circuit 722-1. Further, control information c transferred via the bus 4 is transmitted from the processor interface 71 to the function matching circuit 723-1.

The address collating circuit 721-1 stores the address a transmitted from the processor interface 71 in the register 724-1.
Set against the head address a _HP is, in the case address a head address a _HP inconsistent sets the match detection signal e _a-1 to be output to a logic "0", address a head address If it matches with _aHP , the output match detection signal ea _-1 is set to logic "1" (step S3).

Since all mask codes are set in the registers 725-1 and 726-1, the data collation circuit 722-1 and the function collation circuit 723-1 perform the data d and the control information c transmitted from the processor interface 71.
Regardless of this, the output coincidence detection signals _ed-1 and ec _-1 are set to logic "1".

In this state, in order for the central controller 1 to capture an arbitrary transaction 21, a transaction capturing mechanism (TR
H) When 11 executes the transaction capturing program 22 and succeeds in capturing the transaction 21, the transaction start address a of the captured transaction 21
_TR is stored in a built-in register (R) 12.

On the other hand, in the bus trace device 7, when the transaction capturing mechanism 11 executes the transaction capturing program 22, the processor interface 71 extracts the head address a _HP to be transmitted to the bus 4, and the condition determining circuit 72-1.
To communicate.

In the condition determining circuit 72-1, the address collating circuit 72
1-1 is the start address a from the processor interface 71
_{When TH} is transmitted, the coincidence detection signal ea _-1 is set to logic "1".

A match detection signal e _a-1 output from the address matching circuit 721-1, a match detection signal e _d-1 output from the data matching circuit 722-1, and a match detection signal output from the function matching circuit 723-1. e _c-1 is input to the gate 727-1.

The gate 727-1 receives the input coincidence detection signals e _a-1 and e _a-1 .
_{When d-1} and e _c-1 are all set to logic "1", the output condition satisfaction signal e-1 is set to logic "1" and transmitted to the trace control unit 74.

When the condition satisfaction signal e transmitted from the condition determination circuit 72-1 is set to logic "1", the trace control unit 74 sends a transaction start address a to the console control unit 75.
Request _TR extraction.

Upon receiving the request, the console control unit 75 extracts the transaction start address _aTR stored in the register 12 in the central control device 1 via the basic console 6 and transmits it to the control unit 73 (step S4). .

Control unit 73 calculates the transaction start address a _TR transmitted from the console control unit 75, based on the storage capacity L _TR included in the command, the region A _TR transaction 21 the central control unit 1 has been captured (step S5), a register 724 provided in another condition determination circuit 72-2
-2, and an all-mask code is set in the registers 725-2 and 726-2 (step S6).

The address collating circuit 721-2 stores the address a transmitted from the processor interface 71 in the register 724-2.
_Is compared with the transaction area _ATR set in
If the address a is outside the transaction area _ATR , the output match detection signal e _a-2 is set to logic “0”,
If the address a is in the transaction area _ATR , the output match detection signal e _a-2 is set to logic “1”.
(Step S3) Since all the mask codes are set in the registers 725-2 and 726-2, the data collating circuit 722-2 and the function collating circuit 723-2 transmit the data d transmitted from the processor interface 71 and Control information c
However, the coincidence detection signals _ed-2 and ec _-2 to be output are set to logic "1".

In this state, the central controller 1 transfers the address a 'of the captured transaction 21 in the main memory 2 via the bus 4, and writes and reads various control information d' associated with the call processing. When the data is transferred via the bus 4, in the bus trace device 7, the processor interface 71 extracts the address a ′ and the data d ′ transferred via the bus 4 and transmits them to the condition determination circuit 72-2.

In the condition judging circuit 72-2, the address collating circuit 72
1-2 addresses a transmitted from the processor interface 71 'and against the transaction space A _TR stored in the register 724, address a' because is in transaction area A _TR, the coincidence detection signal e _{a- 2} is set to logic "1" (step S7).

A match detection signal e _a-2 output from the address matching circuit 721-2, a match detection signal e _d-2 output from the data matching circuit 722-2, and a match detection signal output from the function matching circuit 722-2. e _c-2 is input to the gate 727-2.

The gate 727-2 outputs the coincidence detection signals e _a-2 and e
_{When d-2} and e _c-2 are all set to logic "1", the output condition satisfaction signal e-2 is set to logic "1" and transmitted to the trace control unit 74.

When the condition satisfaction signal e-2 transmitted from the condition determination circuit 72-2 is set to logic "1", the trace control unit 74 transmits the recording control signal w to the trace memory 76, and Then, the address a ', data (call processing control information) d', and control information c 'transmitted to the trace memory 76 via the memory 2 are recorded (step S8).

As described above, when the central control device 1 writes and reads out various types of control information d 'for the captured transaction 21, unless the condition determination circuit 72-1 detects the capture of a new transaction 21 (step S9). , Are all recorded in the trace memory 76.

When the central controller 1 ends a series of processes, the transaction 21 that has been captured is released, and returns to the original free state.

Further, the central controller 1 sends a transaction capture program to the transaction capture mechanism 11 for a new call processing.
When the transaction 22 is executed and a new transaction 21 is captured, the condition determination circuit 72-1 in the bus trace device 7 detects the capture of the transaction of the central control device 1 in the same process as described above (step S9), and then returns to step S9. Repeat the process from S4.

As is apparent from the above description, according to the present embodiment, when the central controller 1 newly captures the transaction 21, the condition determination circuit 72-1 detects the capture of the transaction 21 in the bus trace device 7, and the transaction 21 is captured. By setting the area of the transaction 21 in the condition determination circuit 72-2, the usage state and the storage contents of the transaction 21 are recorded in the trace memory 76.

FIGS. 2 to 5 are merely examples of the present invention. For example, the configuration of the bus trace device 7 is not limited to the illustrated one, and various other modifications are considered. However, the effect of the present invention does not change in any case. Needless to say, the electronic exchange to which the present invention is applied is not limited to the illustrated one.

〔The invention's effect〕

As described above, according to the present invention, the bus trace device detects the transaction captured by the central control device without squeezing the processing capacity of the central control device and the storage area of the main storage device, The recorded contents can be tracked and recorded.

[Brief description of the drawings]

1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an electronic exchange to which the present invention is applied, FIG. 3 is a diagram illustrating a bus trace device in FIG. 2, and FIG. FIG. 5 is a diagram exemplifying a condition determination circuit in the figure, and FIG. 5 is a diagram showing a transaction trace process according to an embodiment of the present invention. In the figure, 1 is a central control unit (CC), 2 is a main storage unit (MM), 3 is a data channel unit (DCH), 4 is a bus,
5 is a bus connection circuit (BC), 6 is a basic console (BCN)
S), 7 is a bus trace device, 11 is a transaction capture mechanism (TRH), 12 is a register (R), 21 is a transaction (TR), 22 is a transaction capture program (THP), 71 is a processor interface, and 72 is a condition judgment. Circuit, 73 is a control unit, 74 is a trace control unit, 75 is a console control unit, 76 is a trace memory, 100 is a transaction capture detection unit, 200 is a capture transaction area setting unit, 300 is a trace unit, 721 is an address matching circuit,
722 is a data matching circuit, 723 is a function matching circuit,
724 to 726 indicate registers, and 727 indicates a gate.

Continuation of front page (56) References JP-A-63-113649 (JP, A) JP-A-60-238948 (JP, A)

Claims (1)

(57) [Claims] 1. A bus (4) for connecting a central control device (1) and a main storage device (2), wherein the bus is provided between the central control device (1) and the main storage device (2). A bus tracing device (7) for recording information transferred via (4) without being controlled by the central control device (1), wherein the transaction capture mechanism provided in the central control device (1) (11) a transaction capture detecting means (100) for detecting that any free transaction (21) provided in the main storage device (2) has been captured; and When the capture of the transaction (21) is detected, a transaction position indicating the position in the main storage device (2) of the captured transaction (21) held by the central control device (1). A capture transaction area setting means (200) for extracting information (a _TR ) and setting an area of the captured transaction (21) in the main storage device (2); and the capture transaction area setting means (200). For the area of the transaction (21) set by
A transaction trace method, comprising: a trace means (300) for recording information transferred by the central control device (1).