SU1686453A1 - Device for interfacing computer with common main line - Google Patents

Abstract

The invention relates to computing and can be used in fault-tolerant multi-machine computing systems, complexes and networks. The aim of the invention is to increase the equipment utilization rate by storing a copy of the main memory data to restore the computational process. The device contains a block for capturing a trunk, two registers, two address decoders, a memory block, a counter, five triggers, two AND elements, a group of AND elements, four OR elements, a group of OR elements, three selection blocks and two single vibrators. 4 з п. Ф-лы, 5 Il.

Description

The invention relates to computing and can be used in fault-tolerant multi-machine computing systems, complexes and networks.

The aim of the invention is to increase the equipment utilization rate by storing a copy of the RAM data and restoring the computational process.

FIG. 1 shows a functional diagram of the device; in fig. 2 - functional block diagram of the capture; in fig. 3 is a functional diagram of the first selection block; FIG. 4 - functional diagram of the second block of choice; in fig. 5 - functional diagram of the third selection block

The device for coupling the computer to the common highway (FIG. 1) contains a block 1 for capturing the highway, a first register 2, a first decoder 3 addresses, a second decoder 4 addresses, a block 5 of memory, a counter 6. triggers 7-10, element 11, element and 12. single-vibrator 13, first

trunk amplifier 14, group of elements AND, element OR 16, second trunk amplifier 17. register 18, elements OR 19-21, group of 22 elements OR, trigger 23, selection blocks 24-26, data bus 27, computer address bus 28, bus 29 common bus data, common bus clock bus 30, common rail capture bus 31, common highway read bus 32, common rail synchronization bus 33, computer initial setup input 34, computer interrupt request output 35, interrupt request confirmation input 36, inputs 37- 40 and output 41 of the block capture

Block 1 capture (Fig. 2) contains a register 42, a counter 43 and triggers 44 and 45

The first block 24 of choice (Fig 3) contains the inputs 46-48, the output 49, the element NOT 50, two blocks 51 and 52 elements AND the block 53 elements OR

The second block 25 of choice (Fig 4) contains inputs 54 and 55, outputs 56 and 57. two blocks 58 and 59 of the elements And And the element NOT 60

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The third block 26 of choice (Fig. 5) contains the inputs 61 and 62, the outputs 63 and 64, two elements And 65 and 66 and the element NOT 67.

The device works as follows.

In the initial setup, an input 34 is given a signal that resets counter 6, register 18, trigger 7, trigger 9, trigger 23. When the common highway is not available, capture bus 31 contains a low level that triggers trigger 8 and 10.

The mate can parbota in three modes.

In the first mode, the interface device performs information exchange functions between different computers connected by a common highway 29-33.

In the second mode, a copy of the data of the main memory of the computer directly connected to this device via the data bus 27 and the address bus 28 is sent to the memory block 5 of the device, and this copy is stored until a new one arrives.

In the third mode, the interface device is used to restore the computational process without loss of information in case of failures and failures.

The device always starts in the first mode.

If data (packet) is required, the source computer exposes the requirement of capturing the common highway. For this, the computer exposes a code to the data bus 27 and an address to the address bus 28, which drives the output of the decoder 3 connected to the input 37 of the capture unit 1. When receiving a signal at input 37, block1 implements the procedure for capturing a highway.

The operation of block 1 for capturing the line is that when the main line is busy, i.e. when there is a signal on bus 31 and input 39, the counters 43 of the block 1 of capture of all devices for interfacing are set to the states determined by the code from the outputs of the registers 42 of the corresponding devices. The codes recorded in the registers 42 of all devices differ from one another. In the presence of a common-line occupancy signal, the operation of the counters 43 is blocked in the counting mode. When the common highway is released and, accordingly, the signal 1 is removed from the input 39, the counting mode of the counters 43 of all devices is enabled. The capture allocation procedure is based on the fact that, as a result of the installation, the transfer signals of the counters 43 of various devices are formed at different times.

If at the transfer output of the 43K-ro device counter a signal is generated and the Kth subscriber enters a request to capture the trunk to the trigger 45, then a 1 in

trigger 44. If the subscriber connected to the K-th device is not logged in the trigger 45 (in the trigger 45 is O), then at the installation input in O of the trigger 44 there is a signal that blocks the operation of the trigger 44 via the C input,

which is supplied by the transfer signal of the counter 43. When recording 1 to the trigger 44, the output 41 of the capture unit 1 generates a signal on which a common-line busy signal is set on the bus 31. In order to release the common highway, the subscriber who captured it exposes a signal to the input 38 of the capture unit 1. On this signal, the trigger 45 is reset and, accordingly, the trigger is set to O of the trigger 44. as a result

the trunk is vacated. The requirement to capture the trunk is accompanied by the recording of G in the trigger 45 when the signal is applied to the input 37 of the capture unit 1.

When the device captures a common highway at output 41 of block 1 of capture, 1 appears. Appearance 1 at exit 41 of block 1 of capture is interrogated by the machine through group 15 of elements I. Interrogation through group 15 of elements I occurs on issuing

address bus 28 of the code exciting the output of the decoder 3 connected to the read enable input of a group of 15 elements I.

After reading 1 from exit 41 block

1 capture computer source writes in the register 2 address of the computer receiver. To do this, a word is put on the data bus 27, and on bus 28 there is a code that activates the output of the decoder 3 connected to the write input

register 2. The signal recording in register 2 at the output of the one-shot 13 generates a signal, which is the issuance of the address recorded in register 2, on the bus 29 data line through the second block 25

selection (trigger 23 is at zero). The pulse from the output of the one-shot 13 is delivered to the bus 30 through the third selection block 26 and the first main amplifier 14.

At the output of the decoder 4 addressable

0 subscriber is formed by G, supplied to the D-input of trigger 8 (trigger 8 is reset to zero when the common highway is not active, i.e. at low level on bus 31). The signal on the bus 30 is recording G trigger 10

5 (trigger 10 is reset to zero when the common highway is empty). On the signal front at the output of the trigger 10, G is written to the trigger 8 of the addressable device, the output of the decoder 4 of which contains 1 (the output of the decoder 4 is connected to the D input

trigger 8, to the C-input of which the trigger output 10 is connected.

When trigger 8 is set to state 1, the AND 12 element and the OR 21 element connect the bus 30 to the clock input of the counter 6 and to the write input of the memory block 5. When a pulse from the output of the one-shot 13 on the transmitting side is blocked, the output from the register 2 to the bus 29 is blocked.

Trigger 9 determines the occupancy of memory block 5 and the device as a whole. If trigger 9 is in state 1, then the computer and the device have not yet completed the information session, either a copy of the contents of the working memory (control point) is being sent to memory block 5, or the computational process is being restored. In all the cases listed above, this device is occupied with respect to computer sources.

If the memory block 5 of the addressable device is occupied, then the output of the element 11, one output of which is connected to the inverse output of the trigger 9, is O. The signal from the output of the element 11 is fed to the bus 32. O on the bus 32 is sensed by the computer source a group of 15 elements And as a signal of the unavailability of a receiving device for machine-to-machine exchange. With a free memory block 5 (when released), trigger 9 is O. At the same time, at the output of the element 11 and the bus 32 there is 1, perceived by the source computer through a group of 15 elements And as a ready signal of the addressed device to receive the packet. The 32-source goes to polling the bus status after passing the address of the computer-receiver through the bus 29. After reading from the bus 32 1, the source computer starts transmitting a packet of information through the register 2, the second selection block 25 and the bus 29 to the receiver's memory block 5.

To do this, each word of the packet is recorded in register 2, as described above, after which the signal from the output of the one-shot 13 produces the output of the word from the register 2 to the bus 29 via the second selector unit 25 and writing the word from the bus 29 through a group of 22 elements OR the memory of the receiver at the address taken from the output of the counter 6,

The signal from the output of the one-shot 13 is transmitted to the receiving device via the bus 30. The signal from the bus 30 in the receiving device increases the content of the counter b by one, with the result that the next word of the packet transmitted through the common line is recorded at the increased address of the memory block 5.

On the first clock signal, the counter 6 is set to 1 trigger 9. That is, the receiving device becomes inaccessible to other computers that are not participating in this 5th information transfer session.

At the completion of the packet, the computer source frees the common line by supplying to the address bus 28 a code that excites the output of the decoder 3 connected to the input

10 38 block 1 capture. When the common highway is released on the falling edge of the busy signal on bus 31 in the addressed device (receiver device), 1 is written to trigger 7, the C input of which

5 is connected to the bus 31, and the D input is connected to the output of the trigger 8. When writing 1 to the trigger 7, an interrupt signal is generated by the computer-receiver of the packet. When the machine perceives an interrupt signal at input 36 of the device

0, a signal appears where the trigger 7 is zeroed. According to the interrupt processing program from the interface, the computer-receiver starts reading the packet from the memory block 5.

5Reading each word of a packet from

memory block 5 occurs when a code is issued to the addressable bus 28, which excites the output of the decoder 3 connected to the read input of memory block 5 and to the input decreases 0 or 1 of the contents of counter b (the content of the counter 6 decreases on the falling edge of the signal at the corresponding decoder output 3). The contents of counter 6 determine the address

5 by which the word is read from the memory block 5. When reading the entire packet recorded in memory block 5, counter 6 goes to the zero state. In this case, the output transfer counter 6

0, a signal is generated by which the trigger 9 through the second element OR 19 is set to O, indicating that the device is ready to receive from the common trunk of the next packet.

5Work in the second mode is possible.

only in the case when the next session is over to receive a packet of information of a computer. For operation in the second mode, the trigger 23 is set to one.

0 The installation of the trigger 23 in 1 occurs when issuing on the address bus 28 code that excites the output of the decoder 3 connected to the S-input of the trigger 23.

The unit state of the trigger 23 defines another path of the signals passing through the selection blocks 24-26.

To eliminate the possibility of recording a checkpoint (CT) and a packet of information from other computers in the same area of the memory block 5, it is necessary to record in the counter 6 a starting address of the CT scan that would exceed the maximum packet size sent by trunk to this device.

The i is set (the anal address in the counter 6 occurs when the required address is transmitted via the bus 27 of the computer and the address is generated on the bus 28, which causes the output of the decoder 3 connected to the data recording enable input to the counter 6. At the same time, the starting address issued via the bus 27 data, through the block 24 of the selection is recorded in the counter 6. Next, the package of information of the checkpoint (copy of the operating memory, which is necessary for full restoration of the computational process in case of failures and failures) is sent to the memory block 5.

For this, each word of the packet is written to register 2, as was done in the first mode. After that, the signal from the output of the one-shot 13 reads the word from register 2 and writes it through the second selection block 25 and the group of 22 elements OR to memory block 5 at the address taken from the output of counter 6.

The write signal to the memory unit 5 is transmitted from the output of the one-shot 13 through the selection unit 26 (the trigger 23 is in the state 1). The signal from the output of the one-shot 13 increases the content of the counter 6 by one, with the result that the next word CT is recorded at the increased address of the memory block 5. According to the first recording signal, the trigger 9 is set to one state similar to the first operation mode.

Upon completion of the recording of the CT in memory block 5, the contents of the counter are stored in register 18. To do this, a code is sent to the address bus 28, which activates the output of the decoder 3 connected to the write enable input of the register 18,

The trigger 9 is transferred to the zero state. The trigger 9 is set to O when a code is issued to the address bus 28 of the computer, which excites the output of the decoder 3 connected to the R input of the trigger 9 via the element OR 19. After that, operation in the first mode is possible again.

Since the probability of a computer failure during the recording of the next CT is not excluded, it is necessary to keep the previous CT until the next CT is fully recorded in memory block 5, therefore in memory block 5 space for two CT. The area of memory block 5 for storing the CT scan should be divided into two segments. In one of them the last CT will be stored, and the other

will be used to record the next CT scan. The storage and recording segments will change periodically. The segment in which the next CT was recorded will be used for storage. Accordingly, the second segment in which the previous CT was stored will be released and can be used to record the next CT, etc.

0 A computer must analyze the occupation of a particular segment and write to counter 6 when issuing a CT the initial address of a free segment of memory block 5.

Upon completion of the recording of CT in memory block 5

5, the trigger 23 is transferred to O. To do this, a code is set up on the address bus 28 that drives the output of the decoder 3 connected to the R input of the trigger 23.

The third mode of operation is used when

The occurrence of failures or failures leading to the destruction or distortion of information in the computer's RAM.

In this mode, the computer in which the failure occurred, or the backup computer, is connected instead of the failed computer, reads the CT information from memory block 5 and thereby completely restores the computational process.

Initially, the computer (mainly in case of

0 or eliminated backup) terminates the session of receiving information from other computers, if this session was initiated before failure (failure). Next, the computer in 5 watts on the address bus 28 code that energizes the output of the decoder 3 connected to the read enable input from the register 18 to the counter 6. From the register 18 through the selector 24, the last address is transferred to the counter-6 CT (trigger 23 is in O). The computer, similar to the first mode, reads the CT information from the memory block 5 into the RAM and restores the computational process.

5In the operation of the device can be observed

conflict situations between the second (third) mode and the first, their appearance will be due to the fact that it takes some time to install the flip-flop 9 in 1.

Therefore, for example, the second (third) mode of operation of the device may start at the moment when an exchange session with this device is initiated by a computer transmitter, but trigger 9 is not yet set to 1. For

5 to avoid such situations in the operation of the device suggests the following procedure before starting work in the second and third modes.

If you need to start working in these modes, you must first poll

through a group of 15 elements AND the state of the triggers 9 and 8. If there is 1 in them, i.e. the exchange session is in progress or the session has only been initiated (an address word has been received}, then work in the second and third modes is impossible. If triggers 8 and 9 are in O, then work starts in the second (third) mode. In counter b, through the first block 24 the selection is recorded the CT address in memory block 5. Next, to eliminate the conflict situation between the modes, the state of the trigger 8 is polled again through the group of 15 Elements I. If its state has changed during the recording of the CT address in counter 6, i.e. word corresponding to this device If the exchange in the second (third) mode is stopped, the counter is zeroed and the exchange session continues, the trigger 9 is set to 1, and the second (third) mode continues.

However, it will also take some time to install the 9 in 1 trigger in the second (third) mode. During this time, the device can be accessed from the computer transmitter side, trigger 8 is set to 1, and output from element 11 is a confirmation that the device is ready to receive information, since trigger 9 has not yet been set to 1. To exclude this computer The transmitter must continue to poll the readiness bus 32 through a group of 15 elements AND for the time required for installation in 1 trigger 9 in the second (third) mode. And if it shows Wits O, the exchange session ends.

To avoid the last conflict situation is possible in another way. To do this, it is necessary after recording in the second mode 1 to the trigger 9 to interrogate again the state of the trigger 8 (the third time) and, if it is set to 1, to stop working in the second (third) mode and reset the counter. At the same time, it is also necessary to ensure in the computer transmitter such a time interval between the transfer of the address word and the first word of information, which exceeds the total installation time in 1 trigger 9 in the second (third) mode, polling the status of trigger 8 and installation in O of counter 6. At identical computers and algorithms for their exchange between each other will be automatically provided without a special time delay.

Claims (5)

1. A device for interfacing a computer with a common backbone containing a memory block, a counter, four trigger, two address decoders, pickup unit, AND group, one-shot, two AND elements, OR element, two main amplifiers, first register, 5 the information input of the first register is the device input for connecting to the computer data bus, the information input of the first the address decoder is the device input for connecting the computer’s address bus to the address bus; the second address decoder input is the device input for connecting the common bus to the data bus; wool 15 is an input device for connection to the bus synchronization common line, the first output of the main amplifier and the first input of the first AND gates are the output and input apparatus 0 connected to the common bus clock bus, the output of the second trunk amplifier is the output of the device for connection to the common rail capture bus, the first and second outputs of the first 5 address encoder are connected respectively to the capture and release inputs of the capture block, information output of the memory block and outputs elements and groups form the outputs of the device for connection to the data bus of the computing machine, the synchronous input of the first trigger is the input of the device for connection to the clock bus Tralee, installation input capture unit magi5 Strahl connected to the reset inputs of the first and second flip-flops, and the clock terminal of the third flip-flop and is an input device for connection to the bus capture the common rail, the first inputs of the AND group 0 connected to the output of the capture unit and the input of the second main amplifier, the second inputs of the group of elements And connected to the first inputs of the first and second elements And the data input of the third trigger 5 and the output of the second trigger, the third inputs of the AND elements of the group are the input of the device for connecting the common highway to the readiness bus, the fourth inputs of the AND elements of the group are connected to the inverse output of the fourth trigger and the second input of the second element AND the recording input of the first register is connected to the input one - vibrator and the third output of the first address decoder, the fourth output 5 of the first address decoder is connected to the fifth inputs of the AND elements of the group, the reading input of the memory unit is connected to the fifth output of the first address decoder and the subtraction input of the counter, the synchronization input of the second trigger is connected to the output of the first trigger, the output of the second address decoder is connected to the information input of the second trigger , the input of the initial installation of the device is connected to the reset input of the counter, the first input of the first OR element and the synchronous input of the fourth trigger, the information input of the first trigger is connected to the bus unit about the potential of the device, the output of the second element AND is the output of the device for connecting the common highway to the readiness bus, the second input of the first element OR is the input of the connection device to the acknowledgment bus of the request for interruption of the computing machine, the output of the first OR element is connected to the zero input of the third trigger, the information input (D-input) of the fourth trigger is connected to the zero potential bus of the device, the one-shot output is connected to the read input of the first register, the counting counter input is connected the entry of the memory block, the output of the counter is connected to the address input of the memory block, characterized in that, in order to increase the equipment utilization rate by providing storage of a copy of the RAM data and restoring the computational process, a second register, a group of elements OR, three are entered the OR element, three selectors, the fifth trigger, the sixth output of the first decoder is connected to the write enable input of the counter, the seventh output of the first address decoder is connected to the write enable input of the second p The register, the eighth output of the first address decoder is connected to the setup input of the fifth trigger, the ninth output of the first address decoder is connected to the zero input of the fifth trigger and the first input of the second OR element, the tenth output of the first address decoder is connected to the first input of the third OR element, synchod the fifth trigger is connected to the input of the initial setup of the device, the information input of the fifth trigger is connected to the zero potential bus of the device, the output of the fifth trigger is connected to the control inputs of the first, the second and third selection blocks, the first information input of the first selection block is connected to the bus of the given computing machine, the second information input of the first selection block is connected to the input of the second register, the output of the first selection block is connected to the information input of the counter, the output of the counter is connected to the information input of the second register, the second input of the second element OR is connected to the transfer output of the counter, the output of the second the OR element is connected to the zeroing input of the fourth trigger, the counter input of the counter is connected to the second input of the third OR element and the output of the fourth OR element, the output of the first AND element is connected to the first input of the fourth OR element, the first register output is connected to the information input of the second selection unit, the first output second block 0, the selection is connected to the first input of the group of elements OR, the second output of the second selection block is connected to the bus data bus, the second inputs of the group of elements OR are connected to the bus data master5 li. the one-shot output is connected to the information input of the third selection block, the first output of the third selection block is connected to the second input of the fourth OR element, the second output of the third selection block 0 is connected to the input of the first trunk amplifier, the second inputs of the AND elements of the group are connected to the output of the second trigger and the information input of the third trigger, the output of the third element OR is connected 5 with the setup input of the fourth trigger, the outputs of the elements OR of the group are connected to the information input of the memory unit. 2. The device according to claim 1, characterized in that it is 0 so that the line capture unit contains a register, a counter, two triggers, the installation and reset inputs of the first trigger respectively the capture and release inputs of the line capture unit 5, the recording input, the counting input of the counter and the output of the second trigger are respectively the installation input, the synchronous input and the output of the line acquisition unit, the output of the first trigger is connected to the reset input 0 of the second trigger, the synchronous input of which is connected to the transfer output of the counter, the information input of the second trigger is connected to the unit potential bus of the device, the information input of the counter 5 is connected to the register output. 3. The device according to claim 1, characterized in that the first selection block contains two blocks of AND elements, a block of OR elements and an NOT element, and the control input 0 of the first selection block is connected to the input of the element NOT and the first input of the first block of elements AND, the output of the element is NOT connected to the first input of the second block of elements AND, the output of the first block of elements AND is connected to the first input of the block of elements OR, the output of the second block of elements AND is connected to the second input of the OR block, the second input of the first block of AND elements and the second input of the second block of AND elements are respectively the first and second information inputs of the first selection block, the output of the block of OR elements is the output of the first block eye selection. 4. Device pop. 1, characterized in that the second selection block contains two blocks of AND elements and the element NOT. moreover, the control input of the selection block is connected to the first inputs of the first and second blocks of elements I. The information input of the selection block is connected to the second input of the first block of elements AND, and to the input of the element NO. the output of the element is NOT connected to the second input of the second block of AND elements, the output of the first block of AND elements is the first output of the selection block, the output is 0 five The left block of the AND elements is the second output of the select box. 5. The device according to claim 1, characterized in that the third selection block contains two elements AND and the element NOT, with the control input of the selection block connected to the first inputs of the first and second elements AND, the information input of the selection block connected to the second input of the first And with the input of the element NOT, the output of the element is NOT connected to the second input of the second element AND, the output of the first element AND is the first output of the selection unit, the output of the second element AND is the second output of the selection unit. C Initial Setup Entry 1 2930. L "L .. :: Ј2Lf 2 Schz T ;; i Bit J