JP2649360B2 - Parallel connection of gate turn-off thyristors - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a parallel connection of gate turn-off thyristors.

[Conventional technology]

FIG. 3 shows the configuration of a conventional parallel connection of gate turn-off thyristors (hereinafter referred to as GTO).
In the figure, a circuit that supplies an on-gate current to the GTO 7 is a path including an on power supply 1, a transistor 3, and a resistor 4,
The circuit that supplies the off-gate current is a path for the power supply for turning off 2, the reactor 5, and the thyristor 6. When a signal is input to the transistor 3, the on-gate current flows in the above-described path, and the two GTOs 7 are turned on. When a signal is input to the thyristor 6, an off-gate current flows in each GTO 7 in the above-described off-gate circuit path, GTO7 turns off. Here, if the static transient characteristics of the GTOs 7 are almost the same, the currents i _A1 and i _A2 flow in a balanced manner as shown in FIG.

The reason why the elements having substantially the same static and transient characteristics are turned on and off in a balanced manner is the auxiliary cathode short-circuit line 9 and the gate short-circuit line 10 shown in FIG. That is,
The gate input line and the gate short-circuit line are not strictly short-circuited, and have impedances Z _G1 , Z _G2 , and Z _S as shown in FIG. Sixth
In the figure, at turn-on, i _G1 passes through Z _G1 to GTO1,
Shall go through connexion i _G2 flows through Z _G2 to GTO2. First
When GTO1 is turned on, as shown in FIG. 5, the gate potential voltage V _GK rises as the anode current rises. Here, GTO2 is not yet turned on, so V _GK
Is low. Accordance connexion through the Yotsute Z _S to the difference between the V _GK connexion i _G1 is GT
Since it flows to O2 and i _G1 + i _G2 flows to GTO2,
GTO2 turns on rapidly and equilibrates with GTO1.

Similarly, at turn-off, it is assumed that i _G1 flows from GTO1 to Z _G1 and i _G2 flows from GTO2 to Z _G2 . GTO1 first
When is turned off, the impedance between GK of GTO1 sharply increases and i _G1 also sharply decreases. I _G2 which has been flowing to the Z _G2 from GTO2 becomes a also be diverted to Z _S, Z _G1, GTO
The gate impedance of _{2 is} from Z _G2 to Z _G2 (Z _S + Z _G1 ) /
(Z _G1 + Z _G2 + Z _S ), i _G2 increases, and GTO2 turns off rapidly. Therefore, GTO1 and GTO2 turn off in equilibrium.

[Problems to be solved by the invention]

However, in the conventional parallel connection of the gate turn-off thyristors, even if the on-voltages of the respective GTOs are matched, a difference in the respective gate potential voltages V _GK occurs as shown in FIG. Due to this, during the on-state operation, for example, the V
If _GK is higher than the GTO2, so the gate current is generated from GTO1 to GTO2 in Z _S. As a result, when the GTO is in the steady state, as shown in FIG. 4, i _G1 and i _G2 vary, and when the GTO is in the steady state, when the GTO is turned off, and when the anode current is unbalanced, the current is concentrated during the turn-off. GT
There was a problem that O was destroyed or deteriorated by operation outside the safe operation area.

In addition, at the time of turn-off, GTO1 from which the gate current at the time of steady-on was extracted has a larger gate extraction charge amount than GTO2, so it turns off first, the turn-off current is unbalanced, and GTO2 turns off while causing current concentration. . At this time, if the GTO2 operates outside the safe operation area, there is a problem that it is destroyed or deteriorated.

The present invention has been made in view of such circumstances, and it is an object of the present invention to suppress GTO transient, current imbalance during steady state operation, and to prevent turn-off switching operation near a safe operation region. Gate turn
To provide a parallel connection of off-thyristors.

[Means for solving the problem]

In order to achieve such an object, the present invention provides each gate
A gate in which a short-circuit line is connected between the gate terminals of the turn-off thyristor, and an off-gate signal or an on-gate signal corresponding to the capacity of the gate turn-off thyristor is input to each of the gate terminals.・
In a parallel connection of turn-off thyristors, a capacitor is connected in place of the short-circuit line, and a parallel connection of gate turn-off thyristors is provided.

[Action]

The conventional structure shown in FIG. 3 has an unbalanced waveform as shown in FIG. 4 by exchanging the gate current at the time of steady ON operation due to the difference in the gate potential voltage of each GTO. It is.

Therefore, even if there is a difference in the gate potential voltage, if an appropriate capacitor is connected between the gate terminals instead of the gate short-circuit line so as to eliminate the exchange of the gate current, the GTO on-state current can be reduced. And the turn-off current can be balanced.

Also, the gate current can be exchanged during the GTO transition by the capacitor, and the current at the time of turn-on and turn-off can be balanced.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a parallel connection of gate turn-off thyristors according to the present invention. In the figure, two GTOs 7, 7 'are connected in parallel in the same direction between terminals A and K, respectively. The gates of the respective GTOs 7 and 7 'are connected to each other via a capacitor 8. An on-gate signal is input to the gate terminal of the GTO7 and the gate terminal of the GTO7 'from a commonly connected wiring 21. The anodes of the respective GTOs 7 and 7 'are connected via auxiliary cathode short-circuit lines 9, respectively. An off-gate signal is input to a cathode terminal of the GTO 7 and a cathode terminal of the GTO 7 'from a commonly connected wiring 22.

The on-gate signal and the off-gate signal are output from a series connection of an on power supply 1, a transistor 3, a resistor 4, a reactor 5, a thyristor 6, and an off power supply 2. GTO7,
The circuit to be supplied to 7 'is constituted by the path of the ON power supply 1, the transistor 3, and the resistor 4. Further, a circuit for supplying the off-gate current to the GTOs 7 and 7 ′ includes a path including an off power supply 2, a reactor 5, and a thyristor 6.

FIG. 7 is a configuration diagram showing one embodiment of a mounting structure of the circuit shown in FIG. In this configuration, a different point from the related art is that a capacitor 8 is connected instead of the gate short-circuit line.

With this configuration, the gate current is exchanged only during the GTO transition via the capacitor 8, and the exchange of the gate current when the GTO is in a steady state can be prevented. Therefore, as shown in FIG. Each current in the figure can be balanced.

FIG. 8 is a block diagram showing another embodiment of a parallel connection of gate turn-off thyristors according to the present invention.

In this figure, what is different from the case of FIG. 1 is GTO7, 7 '.
Have different capacities. For this reason, each GTO7,
The on-gate signal and off-gate signal to 7 'are GTO7,7'
, A signal corresponding to the capacity is formed.
That is, a series body of the resistor 4 and the reactor 5 and a series body of the resistor 4 ′ and the reactor 5 ′ are connected in parallel, and are connected between the transistor 3 and the thyristor 6.

〔The invention's effect〕

As is clear from the above description, according to the parallel connection of the gate turn-off thyristors according to the present invention, the current imbalance during the GTO transient and the steady operation is suppressed, and the turn-off switching near the safe operation is reduced. Operation can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a parallel connection of gate turn-off thyristors according to the present invention, and FIG. 2 shows ideal current waveforms of a parallel connection of gate turn-off thyristors. FIG. 3 shows a conventional gate turn
FIG. 4 is a configuration diagram showing an example of a parallel connection of off-thyristors, FIG. 4 is a diagram showing each current waveform in a conventional parallel connection of gate turn-off thyristors, FIG. 5 and FIG.
FIG. 7 is a diagram showing a conventional problem, FIG. 7 is a configuration diagram showing an embodiment of a mounting structure of a parallel connection body of gate turn-off thyristors according to the present invention, and FIG. FIG. 13 is a configuration diagram showing another embodiment of a parallel connection of off-thyristors. 1 ... power supply for ON, 2 ... power supply for OFF, 3 ... transistor, 4 ... reactor, 5 ... reactor, 6 ... thyristor, 7 ... GTO, 8 ... capacitor, 9 ... auxiliary cathode short circuit Line, 10 ... Gate short-circuit line.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-276923 (JP, A) JP-A-62-58721 (JP, A) JP-A-59-17862 (JP, A) JP-A 63-27662 110815 (JP, A)

Claims (1)

(57) [Claims] 1. A short-circuit line is connected between the gate terminals of each gate turn-off thyristor, and each gate terminal has an off-gate signal or an on-gate signal corresponding to the capacitance of each gate turn-off thyristor. A parallel connection of gate turn-off thyristors, wherein a capacitor is connected in place of the short-circuit line.