JP2643022B2 - Active matrix liquid crystal display device and manufacturing method thereof - Google Patents
Active matrix liquid crystal display device and manufacturing method thereofInfo
- Publication number
- JP2643022B2 JP2643022B2 JP33133990A JP33133990A JP2643022B2 JP 2643022 B2 JP2643022 B2 JP 2643022B2 JP 33133990 A JP33133990 A JP 33133990A JP 33133990 A JP33133990 A JP 33133990A JP 2643022 B2 JP2643022 B2 JP 2643022B2
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- insulating film
- interlayer insulating
- forming
- transparent conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明はアクティブマトリクス液晶表示装置及びその
製造方法に係わり、特に金属配線形成以後に絵素電極を
透明導電膜で形成する工程において、金属配線の保護及
び冗長配線化により配線を防止する構造及び製造方法に
関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix liquid crystal display device and a method of manufacturing the same, and more particularly, to a process of forming a pixel electrode with a transparent conductive film after forming a metal wiring. The present invention relates to a structure and a manufacturing method for preventing wiring by protection and redundancy wiring.
［従来の技術］ アクティブマトリクス液晶表示装置の製造において、
信号線を含む配線をAlなどの金属で形成した後、ITOな
どの透明導電膜を用いて絵素電極を形成する際、例えば
ITOのエッチング液で金属が腐食されないように、従来
は単にプラズマCVDによりSiN膜やSiO膜などの絶縁膜を
金属配線と透明導電膜の間に堆積し、金属配線にエッチ
ング液が触れることを防いでいた。[Prior Art] In manufacturing an active matrix liquid crystal display device,
After forming wiring including signal lines with a metal such as Al, when forming a pixel electrode using a transparent conductive film such as ITO, for example,
Conventionally, an insulating film such as a SiN film or SiO film is simply deposited by plasma CVD between the metal wiring and the transparent conductive film to prevent the metal from being corroded by the ITO etching solution to prevent the etching solution from touching the metal wiring. Was out.
［発明が解決しようとする課題］ 上記の方法でアクティブマトリクス液晶表示装置を製
造する際、単に層間絶縁膜で金属配線を覆っても次のよ
うな問題点がある。金属配線の段差部での透明導電膜の
エッチング液の浸食および層間絶縁膜に存在するピンホ
ールからの浸食による金属配線の腐食である。これらの
腐食により金属配線が断線し歩留まりが低下する。[Problems to be Solved by the Invention] When an active matrix liquid crystal display device is manufactured by the above-described method, the following problems occur even if metal wiring is simply covered with an interlayer insulating film. Corrosion of the metal wiring due to erosion of the etching solution of the transparent conductive film at the step portion of the metal wiring and erosion from pinholes existing in the interlayer insulating film. These corrosions cause disconnection of the metal wiring and lower the yield.
本発明は、金属配線の段差部における層間絶縁膜の被
覆性を向上し、さらにピンホールからのエッチング液の
浸食を防ぐ構造及び構造方法を提供することにある。更
にまた、ダスト等により生じた金属配線の断線を救済し
ようとするものである。An object of the present invention is to provide a structure and a method for improving the coverage of an interlayer insulating film in a step portion of a metal wiring and for preventing erosion of an etching solution from a pinhole. Still another object of the present invention is to relieve a disconnection of a metal wiring caused by dust or the like.
［問題を解決するための手段］ 上記目的を達成する手段としては、金属配線にサイド
ウォール構造を設けて層間絶縁膜を堆積し、金属配線の
段差部の被覆性を向上させ、段差部からの透明導電膜の
エッチング液の浸食を防ぐ。[Means for Solving the Problem] As means for achieving the above object, a side wall structure is provided on a metal wiring, an interlayer insulating film is deposited, the coverage of a step portion of the metal wiring is improved, and Prevents etching of the transparent conductive film from erosion.
さらに、その層間絶縁膜上に透明導電膜で絵素電極を
形成すると同時に金属配線部分の上にも透明導電膜を残
すようなパターンとする。こうすることにより、透明導
電膜のエッチング工程では、金属配線上には絶縁膜を介
して透明導電膜とレジストがあるために、その部分の層
間絶縁膜は透明導電膜のエッチング液に触れることがな
いので、ピンホールからのエッチング液の浸食による金
属配線の断線が防止できる。また、金属配線上の層間絶
縁膜の一部にコンタクトホールを形成しておく事によ
り、金属配線にダスト等により生じる欠陥が存在しても
自動的に救済され、欠陥に対する歩留りを大幅に向上す
ることができる。Further, a pattern is formed such that a pixel electrode is formed of a transparent conductive film on the interlayer insulating film and at the same time the transparent conductive film is left on the metal wiring portion. By doing so, in the step of etching the transparent conductive film, since the transparent conductive film and the resist are present on the metal wiring via the insulating film, the interlayer insulating film in that portion can be exposed to the transparent conductive film etching solution. Therefore, disconnection of the metal wiring due to erosion of the etching solution from the pinhole can be prevented. Further, by forming a contact hole in a part of the interlayer insulating film on the metal wiring, even if a defect caused by dust or the like exists in the metal wiring, it is automatically relieved, and the yield for the defect is greatly improved. be able to.
［作用］ 上記した手段によれば、透明導電膜のエッチング時に
金属配線の断線を防げるのみならず、透明導電膜のエッ
チング以前に何らかの原因で生じた断線による欠陥も自
動的に救済される。[Operation] According to the above-described means, not only the disconnection of the metal wiring can be prevented at the time of etching the transparent conductive film, but also the defect due to the disconnection generated for some reason before the etching of the transparent conductive film is automatically relieved.
［実施例］ 以下、本発明の実施例について説明する。第１図は、
TFTアクテイブマトリクス基板の一つの絵素部分であ
り、Alなどの金属で形成されたデータ信号線１とn+ポリ
シリコンで形成された走査信号線２の交差部にポリシリ
コンTFT3がある。TFT3のドレインは絵素電極４のITOと
コンタクトガとられている。第２図は、第１図のＡ−
Ａ′での断面図を示しており、透明絶縁基板10上にはゲ
ート絶縁膜９及び第１層間絶縁膜８が順次形成され、該
第１層間絶縁膜８上に形成された金属配線の両側にサイ
ドウォール６が形成されている。このサイドウォールの
形成は以下のように行った。金属配線パターン形成後、
プラズマCVDによりSiO膜を9000Å堆積し、異方性エッチ
ングにより7000ÅエッチバックしてさらにプラズマCVD
によりSiO膜を4000Å堆積して、最終的にサイドウォー
ル構造を有した金属配線上に6000Åの第２層間絶縁膜７
を形成した。第３図は、アクティブマトリクス基板上の
金属配線パターンの一部を示し、ITOをエッチングする
前の状態であり、金属配線31、32及びITOのレジストパ
ターン33、34が示されている。第４図は、第３図のＢ−
Ｂ′での断面であり、金属配線31、32の上にはサイドウ
ォールを形成した第２層間絶縁膜７、ITO膜35及びレジ
ストパターン33、34が示されている。この状態でHBr等
のエッチング液でITOをエッチングした時、金属配線パ
ターン上はレジストで覆われているので、エーチング液
のピンホールからの浸食を避けることが出来る。このIT
Oの金属配線上のパターンは、配線間のリークの問題を
避けるため第３図のようにそれぞれ配線間につながらな
いようにしておく。また、第１図、第２図に示されてい
るように信号線上にもITOパターン５を絵素電極４と電
気的に独立している限り配置できる。第５図はITO工程
の前に金属配線51に何らかの原因で断線53が発生して
も、第２層間絶縁膜にコンタクトホール54を形成してお
くと、ITOパターン52を形成した際に自動的に断線が救
済される実施例を示している。[Example] Hereinafter, an example of the present invention will be described. Figure 1
A polysilicon TFT 3 is a picture element portion of the TFT active matrix substrate at an intersection of a data signal line 1 formed of a metal such as Al and a scanning signal line 2 formed of n + polysilicon. The drain of the TFT 3 is in contact with the ITO of the picture element electrode 4. FIG. 2 is a cross-sectional view of FIG.
A cross-sectional view at A ′ is shown, in which a gate insulating film 9 and a first interlayer insulating film 8 are sequentially formed on a transparent insulating substrate 10, and both sides of a metal wiring formed on the first interlayer insulating film 8. A sidewall 6 is formed on the substrate. The formation of the sidewall was performed as follows. After forming the metal wiring pattern,
Deposit 9000 mm of SiO film by plasma CVD, etch back by 7000 mm by anisotropic etching, and further plasma CVD
4,000 mm of SiO film is deposited on the resultant structure, and 6000 mm of second interlayer insulating film 7 is finally formed on the metal wiring having the sidewall structure.
Was formed. FIG. 3 shows a part of the metal wiring pattern on the active matrix substrate, which is a state before the ITO is etched, and shows metal wirings 31, 32 and resist patterns 33, 34 of the ITO. FIG. 4 is a cross-sectional view of FIG.
This is a cross-section at B ', in which the second interlayer insulating film 7 having a sidewall formed thereon, the ITO film 35, and the resist patterns 33 and 34 are shown above the metal wirings 31 and 32. In this state, when the ITO is etched with an etching solution such as HBr, the metal wiring pattern is covered with the resist, so that the etching solution can be prevented from eroding from the pinholes. This IT
The pattern on the O metal wiring should not be connected between the wirings as shown in FIG. 3 in order to avoid the problem of leakage between the wirings. Also, as shown in FIGS. 1 and 2, the ITO pattern 5 can be arranged on the signal line as long as it is electrically independent of the picture element electrode 4. FIG. 5 shows that even if a disconnection 53 occurs in the metal wiring 51 for some reason before the ITO process, if the contact hole 54 is formed in the second interlayer insulating film, the ITO pattern 52 is automatically formed. Shows an embodiment in which the disconnection is relieved.
［発明の効果］ 本発明によれば、金属配線形成後の絵素電極形成工程
で行われる透明導電膜のエッチングによる金属配線の断
線を大幅に削減することができ、また絵素電極形成前に
発生した金属配線の断線を救済することができるため、
アクティブマトリクス液晶表示装置の歩留まりを向上す
ることできる。[Effects of the Invention] According to the present invention, disconnection of a metal wiring due to etching of a transparent conductive film performed in a picture element electrode forming step after formation of a metal wiring can be significantly reduced, and before the formation of a pixel electrode, Since it is possible to rescue the disconnection of the generated metal wiring,
The yield of the active matrix liquid crystal display device can be improved.
第１図、第３図は本発明の実施例であり、それぞれTFT
アクティブマトリクス基板の一絵素部及び金属配線部で
ある。第２図は第１図のＡ−Ａ′での断面図であり、第
４図は第３図のＢ−Ｂ′での断面図である。第５図は、
金属配線の断線がITOにより救済される実施例である。 １……データ信号線、２……走査信号線、３……TFT,4
……絵素電極、５、35、52……ITOパターン、６……サ
イドウォール、７……第２層間絶縁膜、８……第１層間
絶縁膜、９……ゲート絶縁膜、10……透明絶縁性基板、
31、32、51……金属配線、33,34……ITOレジストパター
ン、54……コンナタクトホール、FIGS. 1 and 3 show embodiments of the present invention.
One pixel portion and a metal wiring portion of the active matrix substrate. FIG. 2 is a sectional view taken along the line AA 'of FIG. 1, and FIG. 4 is a sectional view taken along the line BB' of FIG. FIG.
This is an embodiment in which the disconnection of the metal wiring is relieved by ITO. 1 ... data signal line, 2 ... scanning signal line, 3 ... TFT, 4
... Picture element electrode, 5, 35, 52... ITO pattern, 6... Sidewall, 7... Second interlayer insulating film, 8. Transparent insulating substrate,
31, 32, 51 ... metal wiring, 33, 34 ... ITO resist pattern, 54 ... contact hole,
───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉村 洋二 大阪府大阪市阿倍野区長池町22番22号 シャープ株式会社内 (56)参考文献 特開 昭62−84563（ＪＰ，Ａ) 特開 昭63−316084（ＪＰ，Ａ) 特開 平２−245739（ＪＰ，Ａ) 特開 平２−278749（ＪＰ，Ａ) ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoji Yoshimura 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (56) References JP-A-62-84563 (JP, A) JP-A-63- 316084 (JP, A) JP-A-2-245739 (JP, A) JP-A-2-278749 (JP, A)
Claims (6)
及び第１層間絶縁膜と、該第１層間絶縁層上に形成され
た金属配線と、該金属配線の両側に形成されたサイドウ
ォールと、該金属配線及びサイドウォール上に形成され
た第２層間絶縁膜と、該第２相間絶縁膜上に形成された
透明導電膜とを備えていることを特徴とするアクティブ
マトリクス液晶表示装置。A gate insulating film and a first interlayer insulating film formed on a transparent insulating substrate; a metal wiring formed on the first interlayer insulating layer; and sidewalls formed on both sides of the metal wiring. An active matrix liquid crystal display device comprising: a second interlayer insulating film formed on the metal wiring and the sidewall; and a transparent conductive film formed on the second interphase insulating film.
成されている請求項１に記載のアクティブマトリクス液
晶表示装置。2. The active matrix liquid crystal display device according to claim 1, wherein said transparent conductive film is formed so as to cover said metal wiring.
成されたコンタクトホールを介して前記金属配線と電気
的に接続されている請求項２に記載のアクティブマトリ
クス液晶表示装置。3. The active matrix liquid crystal display device according to claim 2, wherein said transparent conductive film is electrically connected to said metal wiring via a contact hole formed in said second interlayer insulating film.
求項１、２又は３に記載のアクティブマトリクス液晶表
示装置。4. The active matrix liquid crystal display device according to claim 1, wherein said metal wiring is formed of A1.
間絶縁膜を形成する工程と、該第１層間絶縁膜上に金属
配線を形成する工程と、該金属配線上に絶縁膜を形成し
た後、該絶縁膜を反応性イオンエッチングしてサイドウ
ォールを形成する工程と、該金属配線及びサイドウォー
ル上に第２層間絶縁膜を形成する工程と、該第２層間絶
縁膜にコンタクトホールを形成した後、該第２層間絶縁
膜上に透明導電膜を形成する工程とを含むことを特徴と
するアクティブマトリクス液晶表示装置の製造方法。5. A step of forming a gate insulating film and a first interlayer insulating film on a transparent insulating substrate, a step of forming a metal wiring on the first interlayer insulating film, and forming an insulating film on the metal wiring Forming a sidewall by reactive ion etching of the insulating film, forming a second interlayer insulating film on the metal wiring and the sidewall, and forming a contact hole in the second interlayer insulating film. Forming a transparent conductive film on the second interlayer insulating film after forming the active layer liquid crystal display device.
該透明導電膜をHBrをエッチング液でエッチングするこ
とにより、前記金属配線上に該透明導電膜をパターンニ
ングして形成する請求項５に記載のアクティブマトリク
ス液晶表示装置の製造方法。6. The step of forming the transparent conductive film,
6. The method according to claim 5, wherein the transparent conductive film is formed by patterning the transparent conductive film on the metal wiring by etching HBr with an etchant.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33133990A JP2643022B2 (en) | 1990-11-28 | 1990-11-28 | Active matrix liquid crystal display device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33133990A JP2643022B2 (en) | 1990-11-28 | 1990-11-28 | Active matrix liquid crystal display device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04195122A JPH04195122A (en) | 1992-07-15 |
| JP2643022B2 true JP2643022B2 (en) | 1997-08-20 |
Family
ID=18242579
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33133990A Expired - Lifetime JP2643022B2 (en) | 1990-11-28 | 1990-11-28 | Active matrix liquid crystal display device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2643022B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11121783A (en) * | 1997-10-09 | 1999-04-30 | Canon Inc | Photodetector and manufacture thereof |
| US6287899B1 (en) * | 1998-12-31 | 2001-09-11 | Samsung Electronics Co., Ltd. | Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same |
| JP6277640B2 (en) * | 2013-09-13 | 2018-02-14 | セイコーエプソン株式会社 | Electro-optical device substrate manufacturing method, electro-optical device substrate, electro-optical device, and electronic apparatus |
-
1990
- 1990-11-28 JP JP33133990A patent/JP2643022B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04195122A (en) | 1992-07-15 |
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