JP2643014B2 - Electronic device and wiring chip for connecting semiconductor chip - Google Patents
Electronic device and wiring chip for connecting semiconductor chipInfo
- Publication number
- JP2643014B2 JP2643014B2 JP19911690A JP19911690A JP2643014B2 JP 2643014 B2 JP2643014 B2 JP 2643014B2 JP 19911690 A JP19911690 A JP 19911690A JP 19911690 A JP19911690 A JP 19911690A JP 2643014 B2 JP2643014 B2 JP 2643014B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- wiring
- electronic device
- semiconductor chip
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/142—Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、原子力ロボット等に組み込むのに適した、
小型、高信頼性の電子装置及び半導体チップ接続用配線
チップに関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention is suitable for being incorporated in a nuclear robot or the like.
The present invention relates to a small and highly reliable electronic device and a wiring chip for connecting a semiconductor chip.
（従来の技術） 集積回路を具備した半導体チップは、ハイブリッドIC
や高密度基板実装の電子装置などに用いられている。こ
のような半導体チップは、従来、第５図に示すように、
所定配線の銅パターン12が印刷された配線板８の上に接
着剤で固定され、半導体チップの端子は、配線板８上の
ランドパターン10にワイヤ線11で接続され、上記銅パタ
ーン12を介して電子回路を構成するものである。(Prior art) A semiconductor chip having an integrated circuit is a hybrid IC.
And electronic devices mounted on high-density substrates. Conventionally, such a semiconductor chip is, as shown in FIG.
The copper pattern 12 of the predetermined wiring is fixed on the printed wiring board 8 on which the printed copper pattern 12 is printed, and the terminal of the semiconductor chip is connected to the land pattern 10 on the wiring board 8 by the wire 11, To constitute an electronic circuit.
（発明が解決しようとする課題） 上記の電子装置は、多数の半導体チップを搭載する比
較的大きな印刷配線板を必要とし、半導体チップの端子
を印刷配線板上のランドパターンとワイヤ線で接続する
ため、接続作業が繁雑であり、かつ、実装密度に制限が
あり、狭溢部への電子装置の装着に大きな制約となって
いた。(Problems to be Solved by the Invention) The above electronic device requires a relatively large printed wiring board on which a large number of semiconductor chips are mounted, and terminals of the semiconductor chip are connected to land patterns on the printed wiring board by wire wires. Therefore, the connection work is complicated, and the mounting density is limited, and the mounting of the electronic device in the narrow overflow area is a great restriction.
そこで、本発明は、上記の問題点を解消し、半導体チ
ップの接続作業を簡便にし、大きな印刷配線板を不用と
し、実装部品点数を大幅に低減するとともに、狭溢部へ
の装着を容易にした電子装置を提供しようとするもので
ある。Therefore, the present invention solves the above-mentioned problems, simplifies the work of connecting semiconductor chips, eliminates the need for a large printed wiring board, greatly reduces the number of mounted components, and facilitates mounting on narrow overflow areas. It is an object of the present invention to provide an improved electronic device.
（課題を解決するための手段） 本発明は、集積回路を具備した半導体チップを相互に
接続した電子装置において、所定の配線を具備した配線
チップを用い、その端部に形成した接続用端子に対し、
半導体チップの端子を直接に結合して電子回路を構成し
たことを特徴とする電子装置、及び、集積回路を具備し
た半導体チップを相互に接続した電子装置を形成するた
めの配線チップにおいて、所定の配線を具備し、その端
部に接続用端子を形成したことを特徴とする半導体チッ
プ接続用配線チップである。(Means for Solving the Problems) The present invention relates to an electronic device in which semiconductor chips each having an integrated circuit are connected to each other, using a wiring chip having a predetermined wiring and connecting terminals formed at the ends thereof. On the other hand,
In an electronic device, wherein an electronic circuit is configured by directly connecting terminals of a semiconductor chip, and a wiring chip for forming an electronic device in which semiconductor chips having integrated circuits are connected to each other, A wiring chip for connecting a semiconductor chip, comprising a wiring, and a connection terminal formed at an end thereof.
なお、半導体チップは、放熱効果を得るために、熱伝
導率の大きい材料で作った基板の上に薄い絶縁層、例え
ば、薄いガラス板を介して固定し、必要に応じて、該基
板を筺体に接合することができる。また、半導体チップ
の端子と配線チップの端子との結合は、溶融接合等によ
り容易に結合することができる。The semiconductor chip is fixed on a substrate made of a material having a high thermal conductivity through a thin insulating layer, for example, a thin glass plate, in order to obtain a heat radiation effect. Can be joined. Further, the connection between the terminal of the semiconductor chip and the terminal of the wiring chip can be easily performed by fusion bonding or the like.
（作用） 本発明の電子装置は、上記のように、半導体チップと
配線チップとを適宜組み合わせることにより、電子回路
を形成することができるので、実装部品点数を大幅に低
減することができ、かつ、容易に小型化することができ
るので、ロボット等の狭溢部への適用を可能にし、ま
た、それぞれのチップの端子を溶融接合等により、極め
て簡単に接合することができるため、接合作業に簡便に
して電子装置の生産性を高めることができた。(Operation) As described above, the electronic device of the present invention can form an electronic circuit by appropriately combining a semiconductor chip and a wiring chip, so that the number of mounted components can be significantly reduced, and It can be easily miniaturized, so that it can be applied to a narrow overflow area of a robot, etc. In addition, since the terminals of each chip can be joined very easily by fusion joining, etc. The productivity of the electronic device can be improved simply.
（実施例） 本発明の実施例を図面を用いて説明する。第１図
（ａ）は、半導体チップと配線チップの接合の関係を示
した概念図、同（ｂ）は、（ａ）中のＡ方向視の配線チ
ップの概念図、第２図は、金属製基板に半導体チップ及
び配線チップを装着した電子装置の概念図、第３図は、
金属製基板上に装着した半導体チップの拡大図、第４図
は、電子装置を実装したロボットの腕の概念図である。(Example) An example of the present invention will be described with reference to the drawings. 1 (a) is a conceptual diagram showing the relationship between the bonding of a semiconductor chip and a wiring chip, FIG. 1 (b) is a conceptual diagram of the wiring chip viewed in the direction A in FIG. 1 (a), and FIG. FIG. 3 is a conceptual diagram of an electronic device in which a semiconductor chip and a wiring chip are mounted on a board made of
FIG. 4 is an enlarged view of a semiconductor chip mounted on a metal substrate, and FIG. 4 is a conceptual diagram of a robot arm on which an electronic device is mounted.
第１図（ａ）の半導体チップ３は、集積回路を具備
し、両端部に例えばアルミニウム合金、金等の端子４を
設け、また、同（ｂ）の配線チップ１は、所定の配線を
備え、両端部に例えばアルミニウム合金の端子２を設
け、（ａ）の矢印のように、半導体チップ３の端子４の
上に、配線チップ１の端子２を重ねて、同時に溶融接合
する。第２図の電子装置は、金属製基板５の上に、第３
図のように、薄いガラス板６を介して半導体チップ3,3
a,…3gを固定し、第１図のように、半導体チップ３の端
子４の上に配線チップ１の端子２を重ね、両端子を溶融
接合して電子回路を形成する。このように、半導体チッ
プ３と配線チップ１のみを組み合わせることにより、電
子回路をコンパクトに構成することができる。The semiconductor chip 3 shown in FIG. 1A has an integrated circuit, and terminals 4 made of, for example, an aluminum alloy or gold are provided at both ends. The wiring chip 1 shown in FIG. 1B has predetermined wiring. Terminals 2 made of, for example, an aluminum alloy are provided at both ends, and the terminals 2 of the wiring chip 1 are superimposed on the terminals 4 of the semiconductor chip 3 as shown by arrows in FIG. The electronic device shown in FIG.
As shown in the figure, the semiconductor chips 3, 3 are interposed via a thin glass plate 6.
3g are fixed, and as shown in FIG. 1, the terminal 2 of the wiring chip 1 is superimposed on the terminal 4 of the semiconductor chip 3 and both terminals are melt-bonded to form an electronic circuit. Thus, by combining only the semiconductor chip 3 and the wiring chip 1, the electronic circuit can be made compact.
第４図は、このような電子装置を筺体７に収納して金
属製基板５と筺体７を直接接合したものをロボットの腕
に装着したものである。FIG. 4 shows a case where such an electronic device is housed in the housing 7 and the metal substrate 5 and the housing 7 are directly joined to each other and mounted on the arm of the robot.
（発明の効果） 本発明は、上記の構成を採用することにより、半導体
チップと配線チップのみで電子装置を構成することがで
きるために容易に小型化することができ、従来の印刷配
線板により制限されていたロボット等の狭溢部への実装
を可能にし、実装部品点数を大幅に低減することがで
き、接合作業も簡便になったので、電子装置のコストを
大幅に低減することができた。さらに、金属製等の熱伝
導率の大きい基板を使用するときには、半導体チップか
らの放熱が容易になり、半導体の動作をより確実にする
ことができた。(Effects of the Invention) According to the present invention, by adopting the above configuration, an electronic device can be constituted by only a semiconductor chip and a wiring chip, so that the electronic device can be easily reduced in size. Mounting on a narrow overflow area of a limited robot, etc. was possible, and the number of mounted parts was greatly reduced.Since joining work was also simplified, the cost of electronic devices could be significantly reduced. Was. Further, when a substrate made of metal or the like having a high thermal conductivity is used, heat radiation from the semiconductor chip is facilitated, and the operation of the semiconductor can be made more reliable.
第１図（ａ）は半導体チップと配線チップの接合の関係
を示した概念図、同（ｂ）は（ａ）中のＡ方向視の配線
チップの概念図、第２図は金属製基板に半導体チップ及
び配線チップを装着した電子装置の概念図、第３図は金
属製基板上に装着した半導体チップの拡大図、第４図
は、電子装置を実装したロボットの腕の概念図、第５図
は従来の印刷配線板上に形成した電子装置の概念図であ
る。FIG. 1 (a) is a conceptual diagram showing a connection relationship between a semiconductor chip and a wiring chip, FIG. 1 (b) is a conceptual diagram of a wiring chip viewed in a direction A in FIG. 1 (a), and FIG. FIG. 3 is a conceptual diagram of an electronic device on which a semiconductor chip and a wiring chip are mounted, FIG. 3 is an enlarged view of a semiconductor chip mounted on a metal substrate, FIG. 4 is a conceptual diagram of a robot arm on which the electronic device is mounted, and FIG. FIG. 1 is a conceptual diagram of an electronic device formed on a conventional printed wiring board.
フロントページの続き (72)発明者 白須 勲 兵庫県神戸市兵庫区和田崎町１丁目１番 １号 三菱重工業株式会社神戸造船所内 (72)発明者 青山 富夫 兵庫県神戸市兵庫区和田崎町１丁目１番 １号 三菱重工業株式会社神戸造船所内Continued on the front page (72) Inventor Isao Shirasu 1-1-1, Wadazakicho, Hyogo-ku, Kobe-shi, Hyogo Prefecture Inside the Kobe Shipyard of Mitsubishi Heavy Industries, Ltd. (72) Inventor Tomio Aoyama 1 Wadasakicho, Hyogo-ku, Kobe-shi, Hyogo Prefecture No.1-1, Mitsubishi Heavy Industries, Ltd., Kobe Shipyard
Claims (3)
接続する電子装置において、所定の配線を具備した配線
チップを用い、その端部に形成した接続用端子に対し、
半導体チップの端子を直接に結合して電子回路を構成し
たことを特徴とする電子装置。An electronic device for interconnecting semiconductor chips having an integrated circuit, wherein a wiring chip having a predetermined wiring is used, and a connection terminal formed at an end of the wiring chip is provided.
An electronic device, wherein an electronic circuit is configured by directly connecting terminals of a semiconductor chip.
薄い絶縁層を介して半導体チップを固定したことを特徴
とする請求項（１）記載の電子装置。2. The electronic device according to claim 1, wherein a semiconductor chip is fixed on a substrate made of a material having high thermal conductivity via a thin insulating layer.
接続して電子装置を形成するための配線チップにおい
て、所定の配線を具備し、その端部に接続用端子を形成
したことを特徴とする半導体チップ接続用配線チップ。3. A wiring chip for connecting a semiconductor chip having an integrated circuit to each other to form an electronic device, comprising a predetermined wiring, and a connection terminal formed at an end thereof. Wiring chip for connecting semiconductor chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19911690A JP2643014B2 (en) | 1990-07-30 | 1990-07-30 | Electronic device and wiring chip for connecting semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19911690A JP2643014B2 (en) | 1990-07-30 | 1990-07-30 | Electronic device and wiring chip for connecting semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0485985A JPH0485985A (en) | 1992-03-18 |
| JP2643014B2 true JP2643014B2 (en) | 1997-08-20 |
Family
ID=16402402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19911690A Expired - Lifetime JP2643014B2 (en) | 1990-07-30 | 1990-07-30 | Electronic device and wiring chip for connecting semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2643014B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8923011B2 (en) * | 2011-11-07 | 2014-12-30 | Kathrein-Werke Kg | Interconnect board |
-
1990
- 1990-07-30 JP JP19911690A patent/JP2643014B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0485985A (en) | 1992-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5747877A (en) | Semiconductor chip package with enhanced thermal conductivity | |
| US5367435A (en) | Electronic package structure and method of making same | |
| US5586007A (en) | Circuit board having improved thermal radiation | |
| JP2501019B2 (en) | Flexible circuit board | |
| KR20010076213A (en) | Semiconductor device and its wiring method | |
| JPH09283695A (en) | Semiconductor mounting structure | |
| JPH05121644A (en) | Electronic circuit device | |
| JP2907127B2 (en) | Multi-chip module | |
| JP2643014B2 (en) | Electronic device and wiring chip for connecting semiconductor chip | |
| JPS60260192A (en) | Method of producing hybrid integrated circuit | |
| JPS6367792A (en) | Package structure of photoelectronic component | |
| JPH08148647A (en) | Semiconductor device | |
| JPH10150065A (en) | Chip-size package | |
| JPH0749804Y2 (en) | Semiconductor device | |
| JPH01225196A (en) | Manufacture of laminated hybrid integrated circuit | |
| JP2705468B2 (en) | Hybrid integrated circuit device | |
| JPS61225827A (en) | Mounting structure of semiconductor element | |
| JP3259217B2 (en) | Noise reduction package | |
| JP2595803B2 (en) | Hybrid integrated circuit device | |
| JPH0458189B2 (en) | ||
| JPH0414852A (en) | Semiconductor device | |
| JP2947468B2 (en) | Composite electronic circuit device | |
| JP2879503B2 (en) | Surface mount type electronic circuit device | |
| JPH04159799A (en) | Hybrid integrated circuit | |
| JPS61113297A (en) | Mounting of substrate |