JP2642584B2 - Distribution table creation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arrival process of cells transmitted from a channel accommodated in an asynchronous transfer mode switching system (hereinafter referred to as an ATM switching system) (probability frequency relating to the number of cells arriving per unit time). (Distribution or probability complementary distribution).

[0002]

[Prior Art] Multimedia (voice, image, data, etc.)
One of the features of the ATM (Asynchronous Transfer Mode) communication network, which is one of the broadband communication networks (B-ISDN) capable of accommodating the information, is to assemble information to be communicated into cells of a fixed length and to transmit each cell. It is to be.

FIG. 6 shows an outline of a cell format.
In this example, the cell has a header section 1 of 5 bytes and an information section 2 of 48 bytes consisting of a total of 53 bytes. The header section is made up of a virtual logical address of the transmission destination and various control information. It consists of data. ATM
In a communication network, variable cell rate communication (Variable Bit Rate communication: hereinafter referred to as VB
R communication) is possible, so that there is an advantage that charging according to the amount of information can be performed, and the use efficiency of a trunk line can be improved by a statistical multiplexing effect.

In order to make the most of these advantages of the ATM communication network, it is necessary to accurately grasp the traffic volume that changes dynamically from time to time in the ATM switching system and to implement adaptive traffic control. For this reason, the ATM exchange has an essential function of collecting traffic-related statistical information on a cell-by-cell basis in order to achieve flexible traffic adaptation control and effective use of communication network resources.

In a conventional synchronous transfer mode communication network (hereinafter referred to as an STM (Synchronous Transfer Mode) communication network), a constant bit rate communication (Constant Bit Rat
e communication, hereinafter referred to as CBR communication), and the amount of traffic is determined uniquely only by managing the user's call connection and call disconnection. Therefore, dynamic traffic control is not required, and traffic is not required. No real-time measurement of was required.

[0006]

When the traffic control based on only the call connection and call disconnection information performed in the conventional STM communication network is applied to the ATM communication network, the bandwidth of the user performing the VBR communication must be handled at the peak rate. And the use efficiency of the equipment of the ATM communication network is degraded. To avoid this problem, in an ATM switching system, traffic information such as the number of passing cells and the number of discarded cells in the system is measured in real time on a cell-by-cell basis, and these measured values are reflected in traffic control, so that adaptive control is possible. Traffic control becomes possible.

[0007] The present invention has been developed in order to eliminate the aforementioned problems.
An object of the present invention is to provide a circuit for creating a probability frequency distribution or a probability distribution relating to the number of cells arriving at a traffic observation point in an ATM switching system per fixed time.

[0008]

In order to solve the above-mentioned problem, the invention of claim 1 is to observe an arrival process of cells transmitted from a plurality of channels accommodated in an ATM switching system, In a distribution table creation circuit that creates a distribution related to the number of cells, an arrival cell detection circuit that detects cells transmitted from the plurality of channels and transmits a detection signal including channel information indicating from which channel the transmission is performed; A first memory that stores a cell count value for each of the channels, and a first memory that adds the count value stored in the first memory based on the detection signal.
A second memory for storing the cell count value for each of the channels, and a second half addition for adding the count value stored in the second memory based on the detection signal The first memory or the second memory is initialized so that a cell and a count value of cells per unit time are alternately stored in the first memory and the second memory. A first control unit that controls one of the half adder and the second half adder to operate based on the detection signal; and a frequency of the count value per unit time for each channel. A third memory for storing a probability frequency distribution of arriving cells for each channel and a value of the frequency stored in the third memory are added by storing at an address determined from the channel and the count value. 3rd half add And reading the count value per unit time for each channel from the first memory or the second memory, which stops counting under the control of the first control unit, and A second control unit that controls the third memory and the third half adder so as to add one to the frequency value stored at an address determined from the read count value. By alternately reading the count value per unit time from the first memory and the second memory, the distribution of the probability of arrival of an arrival cell for an integral multiple of the unit time is stored in the third memory. Is stored.

According to a second aspect of the present invention, there is provided a distribution table creating circuit for observing an arrival process of cells transmitted from a plurality of channels accommodated in an ATM switching system and creating a distribution relating to the number of arrival cells. An arriving cell detection circuit for detecting a cell transmitted from the channel and transmitting a detection signal including channel information indicating from which channel the cell is transmitted, and a first memory for storing a cell count value for each of the channels A first half adder that adds the count value stored in the first memory based on the detection signal, a second memory that stores a cell count value for each of the channels, A second half adder for adding the count value stored in the second memory based on the detection signal; and a count value of cells per unit time are alternately stored in the first memory. Initializing the first memory or the second memory so that the first half adder and the second half adder are stored in the second memory. A first control unit for controlling operation based on a signal, and each time the detection signal is transmitted, the number of the channel included in the detection signal and stored in the first or second memory. Storing a frequency at an address determined from the counted value, thereby adding a third memory storing a probability complement distribution of arriving cells for each channel, and adding the frequency stored in the third memory. 3 and the detection signal from either the first memory or the second memory which is performing a counting operation under the control of the first control unit each time the detection signal is transmitted. Of the channel indicated by The third memory and the third half adder are controlled so as to read out the count value and add one to the frequency stored in the address determined by the channel number and the read count value. A second control unit for reading the count value from the first memory or the second memory based on the detection signal alternately for each unit time;
By updating the frequency stored in the third memory, the established complementary distribution of arrival cells for an integral multiple of the unit time is stored in the third memory.

[0010]

[0011]

In order to measure traffic information on the number of cells in real time in an ATM switching system, a first memory and a second memory are used so that a count value of cells per unit time is alternately stored in a first memory and a second memory. The memory or the second memory is initialized, and control is performed such that one of the first half adder and the second half adder operates based on the detection signal. When the probability distribution is stored in the third memory, a count value per unit time for each channel is read from the first memory or the second memory whose counting is stopped. The third memory and the third half adder are controlled so as to add one to the frequency value stored at the address determined from the channel number and the read count value. In addition, when the probability complementary distribution is stored in the third memory, the first memory or the second memory performing the counting operation every time the detection signal is transmitted. The count value of the channel indicated by the detection signal is read from any of the above, and the frequency stored in the address determined by the channel number and the read count value is set to 1
The third memory and the third half adder are controlled to add one. Thus, by alternately reading the count value per unit time from the first memory and the second memory, the probability distribution or the probability distribution of arrival cells for an integral multiple of the unit time can be calculated in the third memory. To memorize.

[0012]

[0013]

[0014]

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a description will be given of an example of creating a probability frequency distribution and a probability complement distribution regarding the number of cells arriving per a certain time (S) at a traffic observation point. In the following description, one cell holding time of a cell passing through the ATM switching system is normalized as one unit time.

Description of Probability Frequency Distribution The probability frequency distribution is defined as Q (i); (0 ≦ i ≦ S) and initialized as follows. Q (i) = 0; (0 ≦ i ≦ S) Assuming that a count value of the number of cells arriving per S time is m,
Initialize as follows. During the m = 0 S time, every time a cell arrives, the count value m is set to m = m + 1. When the S time has elapsed, Q (m) = Q (m) +1; (0 ≦ m ≦ S).

By repeating the above processing N times, a probability frequency distribution concerning the number of cells arriving per S time can be obtained. FIG. 4 shows a specific example where S = 6 and N = 6. As shown in the figure, when N = 1, one cell arrives per unit time, when N = 2, three cells arrive per unit time, and thereafter, cells arriving per unit time up to N = 6 are observed. Can be obtained.

Description of Probability Complementary Distribution The probability complement distribution is defined as Q ^C (i); (0 ≦ i ≦ S), and initialization is performed as follows. ^{Q C (i) = N;} (i = 0) Q C (i) = 0; a (1 ≦ i ≦ S) counts the number of cells arriving per S time as m,
Initialize as follows. m = 0 S during the time, each time the cell ^{arrives, m = m + 1 Q C} (m) = Q C (m) +1; and (0 ≦ m ≦ S).

By repeating the above processing N times, a probability complementary distribution relating to the number of cells arriving per S time can be obtained. As a specific example, FIG. 5 shows a case where S = 6 and N = 6, and cells arriving per unit time can be represented in a histogram as shown in FIG.

In the above description, the case where the arrival cell is a single channel, the arrival cell counter per S time is one plane, and the distribution table is one plane, but in the following description, the traffic observation point is The case where cells arrive from a plurality of channels and a distribution table is created for each channel will be described in detail.

Description of probability frequency distribution First, a processing flow is shown below. Two counters for counting the number of cells arriving per S time are prepared, and C _A (i); 0 ≤ i ≤ (M-1), 0 ≤ C _A (i) ≤ SC _B (i); 0 ≤ i ≤ (M-1), 0 ≤ C _B (i) ≤ S Initialize as follows. C _A (i) = 0; 0 ≦ i ≦ (M-1) C _B (i) = 0; 0 ≦ i ≦ (M-1) where M is the number of channels.

Two probability frequency distribution tables are prepared, and Q _A (j, k); 0 ≦ j ≦ (M−1), 0 ≦ k ≦ S, 0 ≦ Q
_A (j, k) ≤NQ _B (j, k); 0 ≤j ≤ (M-1), 0 ≤k ≤S, 0 ≤Q
_B (j, k) ≤ N Initialize as follows. Q _A (j, k) = 0; 0 ≤ j ≤ (M-1), 0 ≤ k ≤ SQ _B (j, k) = 0; 0 ≤ j ≤ (M-1), 0 ≤ k ≤ S

Each time a cell arrives during the S time, the channel number is extracted from the header of the arriving cell, and the arriving cell counter CA (NO) is set as C _A (NO) = C _A (NO) +1. I do. Here, NO is a channel number extracted from the header part of the arrival cell, and 0 ≦ NO ≦ M−1. Also, during this S time, the arrival cell counter C _B
(i) is initialized as follows. C _B (i) = 0; 0
≤i ≤ (M-1)

When S time has elapsed, it is assumed that Q _A (j, C _A (j)) = Q _A (j, C _A (j)) + 1; 0 ≦ j ≦ (M−1). During the next S time, every time a cell arrives, the channel number is extracted from the header part of the arriving cell, and the arriving cell counter C _B (NO) is set as C _B (NO) = C _B (NO) +1. I do. Also, during this S time, the arrival cell counter C _A
(i) is initialized as follows. C _A (i) = 0; 0
≤ i ≤ (M-1) After the elapse of S time, Q _A (j, C _B (j)) = Q _A (j, C _B (j)) +1; 0 ≤ j ≤ (M-1) And

The above processing and are repeated alternately, and measurement is performed until the number of repetitions of and is repeated N times. At the time when S × N time has elapsed, the probability distribution of the arrival cell per S time is created in Q _A (j, k) corresponding to the channel. During the next S × N time, the frequency distribution for each S time is created in Q _B (j, k), and the probability frequency distribution Q
_A (j, k) is made accessible from an external circuit, and Q _A (j, k) is initialized when the access is completed. Hereinafter, the processing of-is repeated.

Description of Probability Complementary Distribution First, a processing flow will be described below. Two counters for counting the number of cells arriving per S time are prepared, and C _A (i); 0 ≤ i ≤ (M-1), 0 ≤ C _A (i) ≤ SC _B (i); 0 ≤ i ≤ (M-1), 0 ≤ C _B (i) ≤ S Initialize as follows. C _A (i) = 0; 0 ≦ i ≦ (M−1) C _B (i) = 0; 0 ≦ i ≦ (M-1) where M is the number of channels.

Two probability distribution tables are prepared, and Q ^C _A (j, k); 0 ≦ j ≦ (M−1), 0 ≦ k ≦ S, 0 ≦ Q ^C
_A (j, k) ≤NQ ^C _B (j, k); 0 ≤j ≤ (M-1), 0 ≤k ≤S, 0 ≤Q ^C
_B (j, k) ≤ N Initialize as follows. Q ^C _A (j, k) = 0; 0 ≤ j ≤ (M-1), 0 ≤ k ≤ SQ ^C _B (j, k) = 0; 0 ≤ j ≤ (M-1), 0 ≤ k ≤ S

Each time a cell arrives during the S time, the channel number is extracted from the header part of the arriving cell, and the arriving cell counter C _A (NO) and the probability complement distribution Q ^C _A (j, k) are converted to C _A (NO) = C _A (NO) +1 QC _A (NO, C _A (NO)) = Q ^C _A (NO, ^C _A (NO)) + 1. Here, NO is a channel number extracted from the header part of the arrival cell, and 0 ≦ NO ≦ M−1. During this S time, the arrival cell counter C _B (i) is initialized as follows. C _B (i) = 0; 0 ≤ i ≤
(M-1)

During the next S time, every time a cell arrives, the channel number is extracted from the header of the arrival cell, and the arrival cell counter C _B (NO) and the probability complement distribution Q
^{Let C} _A (j, k) be C _B (NO) = C _B (NO) +1 Q ^C _A (NO, C _B (NO)) = Q ^C _A (NO, C _B (NO)) + 1 . Also, during this S time, the arrival cell counter C _A
(i) is initialized as follows. C _A (i) = 0; 0
≤i ≤ (M-1)

The above processing is alternately repeated, and the number of repetitions with the number of repetitions is N.
Perform the measurement until the time. At the point in time when S × N time has elapsed, a complementary probability distribution regarding the arriving cells per S time is created in Q ^C _A (j, k) corresponding to the channel. During the next S × N times, complement distribution between every time S is created _{^{Q C B (j, k)}} , the probability complement distribution Q
^C _A (j, k) is accessible from the external circuit,
Access also to that initializes the Q ^C _A (j, k) at the time of completion. Hereinafter, the processing of-is repeated.

Description of the realization circuit The probability frequency distribution table creation circuit and the probability supplemental distribution table creation circuit can have the same circuit configuration. A specific example is shown in FIG.
This is shown in FIGS. The distribution table creation circuit is shown in Figs.
This is represented by a set of three sheets in FIG. In the figure, 200 is an arrival cell detection circuit, 206 is an external circuit, and 207 is a control circuit. 010,011,012,013,014,01
5,110,111,112,113,114,11
5, 202, 203 and 205 are selection circuits, and A0,
A1 is connected to input data, and Y is S = 0.
At this time, A0 is output, and when S = 1, A1 is output.

Reference numerals 201 and 204 denote inverters, which output an input signal whose polarity is inverted. 00000
1, 100 and 101 are random access memories (RA
M, hereinafter referred to as memory), an address bus is connected to ADR, an input data bus is connected to DI, and D
O is connected to an output data bus, WE is connected to a write enable signal, and RE is connected to a read enable signal. When a pulse is input to WE, DI data is written to the address specified by ADR, and when a pulse is input to RE, the contents of the address specified by ADR are output to DO.

020, 021, 120 and 121 are registers, CK is connected to a latch pulse, D is connected to an input data bus, and Q is connected to an output data bus. When CK is input, D data is written to the register and output to Q at the same time. 030,031,
Reference numerals 130 and 131 denote half adders, to which input data is connected to A, and a value obtained by adding 1 to A is output to Y.

Reference numeral 208 denotes an exclusive OR circuit. When the polarities of two inputs are different from each other, the output becomes 1 and 2
If the polarities of the two inputs are the same, the output will be zero.

The input signals of the control circuit 207 include a clock S201, a cell synchronization signal S202, and a cell detection signal S20.
3, a start signal S221 and a reset signal S229. The reset signal S229 is a signal for initializing the control circuit 207, and includes a clock S201 and a cell synchronization signal S20.
Reference numeral 2 is used to create various timings in the control circuit 207. The start signal S221 is supplied from the external circuit 206. When the start signal becomes "1", creation of a probability frequency distribution or a probability complementary distribution is started. The cell detection signal S203 is supplied from the arriving cell detection circuit 200, and is used during the distribution table creation.
When the arrival cell is detected at 0, the control circuit 207 informs this fact.
, The control circuit 207 generates various control signals at a predetermined timing to update the arrival cell counter or the distribution table.

The output signals of the control circuit 207 include selection signals S206 and S219, latch pulses S212 and S22.
4, write enable S208, S210, S216,
There are read enable S209, S211, S218, addresses S205, S228, and interrupt signal S227. The selection signal S206 is connected to S of the selection circuits 010 and 011.
The signal S207 whose polarity is inverted from the signal 206 is the selection circuit 11
0, 111 and the exclusive OR circuit 208. An output S232 of the exclusive OR circuit 208 is connected to S of the selection circuit 202.

The selection signal S206 is a signal for determining which memory is to be initialized when the control circuit 207 initializes the memory 000 and the memory 100 after the reset is released. 000 is initialized, and when it is “0”, the memory 100 is initialized. In addition, during the distribution table creation, “0”, “1” every S time
Are alternately repeated, and when "0", the count value of the arriving cell per S time is held in the memory (000), and when "1", the count value of the arriving cell per S time is held in the memory 100. You.

The latch pulse S212 is supplied to the register 020,
CK connected to the half-adders 030 and 130, and the registers 020 and 120 are added to the counts of the arrival cells held in the memories 000 and 100 when the cells arrived. Used to keep.

The write enable S208, S210 is connected to the WE of the memory 000, 100, and when the memory 000, 100 is initialized after reset release and during creation of the distribution table, the data is stored in the memory 000, 100 as data.
In addition to using "0" for writing, the count value of the arriving cell stored in the memory 000, 100 when the cell arrives during the creation of the distribution table is added to the half adder 031, 131.
Is used to write the value added in the above to the memories 000 and 100.

The read enable S209, S211 is connected to the RE of the memory 000, 100, and when the cell arrives during the distribution table creation, the count value of the arriving cell stored in the memory 000, 100 is stored in the memory 000, 1002. 1
It is used to read from 00 and supply it to the half adders 030 and 130. Also, the memory 0 for storing the distribution table
When updating the contents of 01, 101, the memory 000, 10
The count value of the arriving cells per S time from 0 is read and used to supply the addresses of the memories 001 and 101.

The address S205 is selected by the selection circuits 010 and 11
0 is used as an address when the control circuit 207 initializes the memory 000 and the memory 100 after the reset is released and during the creation of the distribution table, and updates the contents of the memories 001 and 101 for storing the distribution table. At this time, the count value of the arriving cell per S time is read from the memory 000,001 and used to supply the address as the address of the memory 001,101.

The write enable S216 is the selection circuit 01
3, 113 are used to update the distribution table connected to A0 and stored in the memory 001, 101.
The read enable S218 is connected to A0 of the selection circuits 014, 114, and when updating the distribution table stored in the memories 001, 101, the memories 001, 1
01, the distribution table is read out, and the half adders 031, 1
Used to supply to 31.

The selection signal S219 is the signal A1 of the selection circuit 203.
To the start signal S22 during the creation of the distribution table.
When 1 becomes "1", it appears at the output S222 of the selection circuit 203, and this output signal S222 is output to the selection circuits 012 and 01.
3, 014, 015, and a signal S223 obtained by inverting the polarity of the selection signal S219 via an inverter 204 is supplied to the selection circuits 112, 113, 114, 115,
205 is connected to S. The selection signal S219 alternately repeats “0” and “1” every S × N time during the creation of the distribution table. When the selection signal S219 is “0”, the memory 001 creates a distribution table on the number of cells arriving per S time. Then, the memory 101 is opened to the external circuit 206. When "1", a distribution table relating to the number of cells arriving per S time is created in the memory 101, and the memory 001 is stored in the external circuit 20.
Opened to 6.

The latch pulse S224 is applied to the registers 021,
Registers 211, 12 are connected to the CKs 121, 121, and the distribution data stored in the memories 001, 101 are added by the half adders 031, 131 during the distribution table creation.
Used to keep at 1.

The interrupt signal S227 is output from the external circuit 206.
By supplying a pulse to the external circuit 206 every S × N time, a distribution table relating to the number of cells arriving per S time is completed in the external circuit 206 in the memory 001 or the memory 101. Notify that.

The address S228 becomes a mixed signal S230 together with the output S213 of the selection circuit 202, and is connected to A0 of the selection circuits 012 and 112. Mixed signal S23
The MSB side of 0 is configured by the address S228, and the LSB side is configured by the output S213 of the selection circuit 202. The mixed signal S230 is used when updating the distribution table stored in the memories 001 and 101 corresponding to the channels.
01, 101, and the mixed signal S23
The address S228 constituting the MSB side of 0 is from 0 to M-
It changes in the range of 1.

The input signals of the external circuit 206 include input data S226, interrupt signal S227, and reset signal S2.
29, and the input data S226 is Y
, And the measured value of distribution data on the number of cells arriving per S time stored in the memory 001 or the memory 101 is supplied. The external circuit 206 does not need to know whether the measured value is stored in the memory 001 or the memory 101. Because the selection circuit 20
This is because, according to 5, the circuit of the present invention automatically selects the memory 001 or 101 in which the latest measured value is stored.

The interrupt signal S227 is output from the control circuit 207.
From the external circuit 20 by supplying an interrupt pulse every S × N time during the creation of the distribution table.
No. 6 can recognize that the distribution table relating to the number of arriving cells per S time is completed in the memory 001 or the memory 101. The reset signal S229 is a signal for initializing the external circuit 206.

The output signals of the external circuit 206 include output data S225, address S214, and write enable S2.
15, read enable S217, selection signal S220,
There are a start signal S221 and a mode signal S231, and the output data S225 is connected to A1 of the selection circuits 015 and 115. After the reset is released, the external circuit 206 initializes the memories 001 and 101 or creates a distribution table. Medium, after the interruption S227 reads the distribution data from the memory 001 or 101,
01 or 101, the output data S22
5 is set to "0", and the previous value "0" is written to the memory 001 or 101.

The write enable S215 is connected to the selection circuit 0
13 and 113, the interrupt S227 occurs when the external circuit 206 initializes the memories 001 and 101 after reset release, or during the creation of the distribution table.
When the memory 001 or 101 is initialized after reading distribution data from the memory 001 or 101, the output data S225 is set to “0” and the memory 001 is initialized.
Alternatively, a write enable signal S215 is sent to 101, and the previous value “0” is written. Read enable S217
Is connected to A1 of the selection circuits 014 and 114, and is used when the distribution data is read from the memory 001 or 101 when the interrupt S227 is input during the creation of the distribution table.

The selection signal S220 is A0 of the selection circuit 203.
After the reset is released, the start signal S2
21 is "0", it appears at the output Y of the selection circuit 203, and this output signal S222
014, 015 and the inverter 204
Signal S22 obtained by inverting the polarity of the selection signal S220 via
3 is a selection circuit 112, 113, 114, 115, 205
To S. The selection signal S220 is a signal that determines which memory is to be initialized when the external circuit 206 initializes the memories 001 and 101 after the reset is released. When the external signal 206 is “0”, the memory 101 is initialized. ,
When it is "1", the memory 001 is initialized.

The start signal S221 is connected to S of the selection circuit 203 and the control circuit 207.
0 "and the memory 000,001,100,1
After the initialization of 01 is completed, the distribution table creation circuit starts measurement by setting it to “1”.

In the mode S231, the exclusive OR circuit 20
Mode S when the probability frequency distribution is created.
231 is set to “0”, and the mode S231 is set to “1” when a probability complementary distribution is created.

The input signal of the arrival cell detection circuit 200 includes
There are cell data S200, a cell synchronization signal S202, and a clock S201. The cell data S200 is a cell transmitted from the user at the observation point.
2 and a clock S202 are timing signals synchronized with the cell data, and are used to generate various timing signals in the cell detection circuit 200.

The output signal of the arrival cell detection circuit 200 includes:
There are a cell detection signal S203 and a channel number S204,
The cell detection signal S203 is connected to the control circuit 207, and notifies the control circuit 207 when the arrival cell is detected. The channel number S204 of the arrival cell is stored in the memory 00 via the control circuit 207 and A0 of the selection circuits 010 and 110.
The ADR of 0,100 is used to specify and add the address of the arrival cell counter of the arrival cell stored in the memory 000 or 100 when the arrival cell is detected during the creation of the distribution table. Note that the number of channels is M, and the channel numbers take values from 0 to M-1. The channel number of the arriving cell is obtained by extracting the channel number from the header part of the arriving cell. However, since the channel number that can take a value from 0 to M-1 is not set in the header part of the cell, the channel number is assumed to be virtual. When a logical identifier is set, a means is provided for converting the virtual logical identifier into a channel number used in the present distribution table creation circuit. (For example,
When the virtual logical identifier is 16 bits and the number of processing channels M of this circuit is 2 ⁴ , a conversion table is required to make 2 ¹⁶ spaces correspond to 2 ⁴ spaces. )

Next, the operation of the circuit will be described according to the processing flow. Description of Probability Frequency Distribution Initialization of Arrival Cell Counter per S Time First, the control circuit 207 and the external circuit 206 are initialized by the reset signal S229. After the reset is released, the control circuit 207 changes the mode signal S231 of the external circuit 206 to “
0 ", and the signal having the same polarity as the output signal S207 of the inverter 201 is output from the exclusive OR circuit 208.
232, and the output signal S232 has a polarity opposite to that of the selection signal S206 output by the control circuit 207. After reset release, the control circuit 207 initializes the memory 000 for storing the arrival cell counter C _A (i) and the memory 100 for storing the arrival cell counter C _B (i).

First, the selection signal S206 is set to 1, and the address S2 is stored in ADR, WE, and DI of the memory 000, respectively.
05, a write enable S210, and “0” S002, and the address is changed from 0 to M−1.
"0" is written to all the contents of "0". Next, the selection signal S
206 is set to 0, and ADR, WE, DI
Address S205 and write enable S20, respectively.
8, "0" S102 is supplied, and the address is changed from 0 to M-1.
And write "0" to all the contents of the memory 100. By the above processing, the arrival cell counter C _A (i)
And C _B (i) are all cleared to zero.

[0058] Memory 101 for storing the probability frequency initialization probability frequency distribution of the distribution table Table Q _A (j, k) memory 001 for storing the probability frequency distribution table Q _B (j, k) after reset release external Initialized by the circuit 206. After the reset is released, the external circuit 206 initializes the memories 001 and 101 while the start signal S
221 is set to “0”. As a result, the selection circuit 203 outputs the selection signal S220 supplied from the external circuit 206 as the output signal S222, and this output signal S222 is connected to S of the selection circuits 012, 013, 0124, and 015 and the inverter 204, and Output signal S22
3 is connected to S of the selection circuits 112, 113, 114 and 115.

By setting the selection signal S220 to "1",
ADR, WE, and DI of the memory 001 are provided with an address S214, a write enable S215, and a write enable S215 from external circuits, respectively.
Output data S225 will be supplied. The external circuit 206 sets the data S 225 to “0” during the initialization, changes the address S 214 from 0 to S × M−1, and clears the contents of the memory 001 to all zeros. Here, S is a measurement unit time for counting the number of arriving cells, and M is the number of channels of cells arriving at the distribution table creation circuit.

Next, by setting the selection signal S220 to "0", the ADR, WE, and DI of the memory 101 are supplied with an address S214 and a write enable S2 from an external circuit, respectively.
16, output data S225 is supplied. The external circuit 206 sets the data S 225 to “0” during the initialization, changes the address S 214 from 0 to S × M−1, and clears the contents of the memory 001 to all zeros.

When the initialization is completed, the external circuit 206
Sets the start signal S221 to "1" and instructs the control circuit to start measurement.

Counting the number of cells arriving per S time:
C _A (i) After the measurement is started, the selection signal S206 is set to “0” and “0” every S time.
When the selection signal S206 is "0", the arrival cell counter C _A (i) is stored in the memory 000.
When the selection signal S206 is “1”, an arrival cell counter C _B (i) is created in the memory 100. Here, after the measurement is started, the selection signal S206 is “0”.
Starts with

During the S time, every time a cell arrives, the cell detection circuit 200 supplies the channel number S204 of the cell to the ADR of the memory 000, the cell detection signal S203 to the control circuit 207, and the control circuit 207. Reference numeral 207 sets the read enable S211 to "1" and supplies it to the memory 000. The value of the cell counter designated by the channel number S204 appears in the DO of the memory 000 as output data S005, and the output data S005 is output to the half adder 030. Input A
To the output data S00 of the half adder 030.
4 is a value obtained by adding 1 to the cell count value stored in the memory 000.

The output data S004 is the latch pulse S
At the same time, the selection circuit 0 stores the data in the register 020 as output data S003 of the register 020.
The selection circuit 011 supplies the output data S003 of the register 020 to the DI of the memory 000 as the output data S001 of the selection circuit 011. The control circuit 207 sets the read enable S211 to "0", and then changes the write enable S210 from "0" to "1".
→ As “0”, the value of the added arrival cell counter is
Write to the address specified by the channel number S204. Now, C _A (NO) = C _A (NO) +1 has been executed.

During this S time, the memory 100 storing the arrival cell counter C _B (i) is all-zero cleared. Since the selection signal S206 is "0", the memory 1
The ADR of 00 is the address S output by the control circuit 207.
205 is connected, and the DI
0 "is connected. At the same time as changing the address S205 from 0 to M-1, the write enable S208 is changed from 0 to 1 to 0 for each address, and the memory 1 is changed.
00 is cleared to all zeros.

Updating the probability distribution table Q _A (j, k) At the point of time when S time has elapsed, the control circuit 207 selects the selection signal S2
06 is set to “1”. The selection signal S219 output from the control circuit 207 is connected to A1 of the selection circuit 203,
During the measurement, since the start signal S221 is "1", it appears at the output S222 of the selection circuit 203, and this output signal S222
Is connected to S of the selection circuits 012, 013, 014, and 015, and the selection signal S2
19, the selection circuit 1
12, 113, 114, 115, and 205 are connected. After the start of the measurement, the selection signal S219 becomes “S × N” every time.
"0" and "1" are alternately repeated.

When the selection signal S219 is "0",
The probability distribution Q _A (j, k) is created in the memory 001, and when the selection signal S219 is “1”, the probability distribution Q A
_B (j, k) is created in the memory 101. here,
After the start of the measurement, the selection signal S219 starts from “0”. The output data S005 of the memory 000, which has finished counting the number of cells arriving per S time, is mixed with the address S228 output from the control circuit 207 via the selection circuit 202.
Connected to 0. Since the selection signal S219 is "0", the mixed signal S230 is connected to the ADR of the memory 001, and the write enable S216 and the read enable S218 output from the control circuit 207 are connected via the selection circuits 013 and 014, respectively. It will be connected to WE and RE of the memory 001.

The address S205 output from the control circuit 207 is connected to A1 of the selection circuit 010. However, since the selection signal S206 is "1", the address S20 is output.
5 is connected to the ADR of the memory 000 via the selection circuit 010. The read enable S211 output from the control circuit 207 keeps “1” while updating Q _A (j, k), and stores the value of the arrival cell counter C _A (i) stored in the memory 000 in the memory 000. DO
Then, output data S005 is output. Control circuit 207
Is the address S205 and the address S228, respectively.
0 to M−1, and for each address, the read enable S218 is first set to “1”, and the memory 0
01 is stored in the probability frequency distribution Q _A (j, CA
(J)) outputs the output data S012 from the DO,
This value is added by the half adder 031.

The output S011 of the half adder 031 is latched in the register 21 by the latch pulse S224, and the output S010 of the register 21 is connected to the DI of the memory 001 as the input S009 via the selection circuit 015. After returning the read pulse S218 to “0”, the write enable S216 is changed from 0 → 1 → 0,
_The value obtained by adding _A (j, C _A (j)) is written to the memory 001. Thus, Q _A (j, C _A (j)) = Q _A (j, C _A (j)) + 1 is executed.

Counting the number of cells arriving per S time:
Between C _B (i) The following S time, the control circuit 207 selects the signal S206
Is set to “1”, and each time a cell arrives, the arriving cell detection circuit 200 supplies the channel number S204 of the cell to the ADR of the memory 100, supplies the cell detection signal S203 to the control circuit 207, and 207 sets the read enable S209 to "1" and supplies it to the memory 100. The value of the cell counter designated by the channel number S204 appears in the DO of the memory 001 as output data S105. By supplying to the input A, the output data S104 of the half adder 130 becomes
The value is obtained by adding 1 to the cell count value stored in the memory 100.

This output data S104 is a latch pulse S
At the same time, the selection circuit 1 stores the data in the register 120 and outputs the output data S103 of the register 120 in step S212.
The selection circuit 111 supplies the output data S103 of the register 120 to the DI of the memory 100 as the output data S101 of the selection circuit 111. The control circuit 207 sets the read enable S209 to “0”, and then changes the write enable S208 from “0” to “1”.
→ As “0”, the value of the added arrival cell counter is
Write to the address specified by the channel number S204. This results in the _{C B (NO) = C B} (NO) +1 is executed.

During this S time, the memory 000 storing the arrival cell counter C _A (i) is cleared to all zeros. Since the selection signal S206 is "1", the memory 0
The ADR of 00 is the address S output by the control circuit 207.
205 is connected, and the data “
0 "is connected. At the same time as changing the address S205 from 0 to M-1, the write enable S208 is changed from 0 to 1 to 0 for each address, and the memory 0 is changed.
00 is cleared to all zeros.

Updating the probability distribution table QA (j, k) At the point in time when S time has elapsed, the control circuit 207 selects the selection signal S2
06 is set to “0”. The output data S105 of the memory 100, which has finished counting the number of cells arriving per S time, is mixed with the address S228 output from the control circuit 207 via the selection circuit 202, and the mixed signal S230 is connected to A0 of the selection circuit 012. Is done. The selection signal S219 is "0"
Therefore, the mixed signal S230 is connected to the ADR of the memory 001, and the write enable S216 and the read enable S218 output from the control circuit 207 are output.
Are stored in the memory 00 via the selection circuits 013 and 014, respectively.
1 WE and RE.

The address S205 output from the control circuit 207 is connected to A1 of the selection circuit 110. However, since the selection signal S206 is "0", the address S205 is output.
5 is connected to the ADR of the memory 100 via the selection circuit 110. The read enable S209 output from the control circuit 207 is set to “1” while updating Q _A (j, k), and the value of the arrival cell counter C _A (i) stored in the memory 100 is stored in the memory 100. DO
As output data S105. Control circuit 207
Is the address S205 and the address S228, respectively.
From 0 to M−1, for each address, first, the read enable S218 is set to “1”, and the probability frequency distribution QA (j, CA) stored in the memory 001 is set.
The value of (j)) is output as data S012 to DO, and this value is added by the half adder 031.

The output S011 of the half adder 031 is latched in the register 21 by the latch pulse S224.
The output S010 of the register 21 is connected to the DI of the memory 001 as input data S009 via the selection circuit 015. After returning the read pulse S218 to “0”, the write enable S216 is changed from 0 → 1 → 0, and the value obtained by adding Q _A (j, C _A (j)) is stored in the memory 00.
Write to 1. This means that Q _A (j, C _B (j)) = Q _A (j, C _B (j)) + 1 has been executed. The above processing and are alternately and repeatedly performed.
The measurement is performed until the number of repetitions of and is repeated N times.

At the time when S × N time has elapsed, a probability frequency distribution Q _A (j, k) relating to the number of cells arriving per S time is created in the memory 001 for each channel.
During the next S × N time, the selection signal S219 is set to “1”, and the above processing and are alternately repeated, so that the probability frequency distribution Q _B (j, k) is created in the memory 101. Will be. Also, during this S × N time,
Memory 00 storing probability frequency distribution Q _A (j, k)
1 is in a state accessible from the external circuit 206. Note that the external circuit 206 stores the data in the memory 0 when the access is completed.
Clear all 01 to zero. Hereinafter, the processing of-is repeated.

Description of Probability Complementary Distribution Initialization of Arrival Cell Counter per S Time First, the control circuit 207 and the external circuit 206 are initialized by a reset signal S229. After the reset is released, the control circuit 207 sets the mode S231 to "1" and outputs a signal obtained by inverting the polarity of the output signal S207 of the inverter 201 as the output signal S232 of the exclusive OR circuit 208. This output signal S232 The signal has the same polarity as the selection signal S206 output from the control circuit 207.

The memory 000 for storing the arrival cell counter C _A (i) and the memory 100 for storing the arrival cell counter C _B (i) are initialized. First, the selection signal S206 is set to 1, and the address S205, the write enable S210, "
0 "S002 is supplied, the address is changed from 0 to M-1, and" 0 "is written to all the contents of the memory 000.
Next, the selection signal S206 is set to 0, and A
An address S205, a write enable S208, and "0" S102 are supplied to DR, WE, and DI, respectively, and the address is changed from 0 to M-1, and "0" is written to all the contents of the memory 100. Through the above processing, the arrival cell counters C _A (i) and C _B (i) are all cleared to zero.

[0079] Memory 101 for storing a probability complement the initialization of the distribution table probability auxiliary distribution table Q ^C _A (j, k) memory 001 and a probability auxiliary distribution table Q ^C _B for storing (j, k) is reset release Thereafter, initialization is performed by the external circuit 206. After the reset is released, the external circuit 206 initializes the memories 001 and 101 while the start signal S
221 is set to “0”. As a result, the selection circuit 203 outputs the selection signal S220 supplied from the external circuit 206 as the output signal S222, and this output signal S222 is connected to S of the selection circuits 012, 013, 0124, and 015 and the inverter 204, and Output signal S22
3 is connected to S of the selection circuits 112, 113, 114 and 115.

By setting the selection signal S220 to "1",
ADR, WE, and DI of the memory 001 are provided with an address S214, a write enable S215, and a write enable S215 from external circuits, respectively.
Output data S225 will be supplied. The external circuit 206 sets the data S 225 to “0” during the initialization, changes the address S 214 from 0 to S × M−1, and clears the contents of the memory 001 to all zeros. Here, S is a measurement unit time for counting the number of arriving cells, and M is the number of channels of cells arriving at this circuit.

Next, by setting the selection signal S220 to "0", the ADR, WE, and DI of the memory 101 are supplied with an address S214 and a write enable S2 from external circuits, respectively.
16, output data S225 is supplied. The external circuit 206 sets the data S 225 to “0” during the initialization, changes the address S 214 from 0 to S × M−1, and clears the contents of the memory 001 to all zeros.

Note that the probability complement distribution Q ^C (j, k) always has the following relationship: Q ^C (j, 0) = N; 0 ≦ j ≦ (M−1). Does not access any of the distribution table creation circuit of the present invention is measured in Q ^C (j, 0),
After S × N time, Q ^C (j, 0) initialized values "
0 "remains. Therefore, the external circuit after S × N times, the probability auxiliary distribution Q ^C (j, 0) is" should be treated as N ". Alternatively, the probability auxiliary distribution Q ^C (j, k ) Is set to “N” only for Q ^C (j, 0),
The external circuit 206 may set the start signal S221 to "1" at the time of completion of the initialization, and instruct the control circuit to start measurement.

The number of arriving cells per S time and the count of the complementary distribution: C _A (i), Q ^C _A (j, k) After the start of the measurement, the selection signal S206 is changed to “0” every S time.
When the selection signal S206 is "0", the arrival cell counter C _A (i) is stored in the memory 000.
When the selection signal S206 is “1”, an arrival cell counter C _B (i) is created in the memory 100. Here, after the measurement is started, the selection signal S206 is “0”.
Starts with

Each time a cell arrives during the S time, the cell detection circuit 200 supplies the channel number S204 of the cell to the ADR of the memory 000, the cell detection signal S203 to the control circuit 207, and the control circuit 207. Reference numeral 207 sets the read enable S211 to "1" and supplies it to the memory 000. The value of the cell counter designated by the channel number S204 appears in the DO of the memory 000 as output data S005, and the output data S005 is output to the half adder 030. Input A
To the output data S00 of the half adder 030.
4. One is added to the cell count value stored in the memory 000.
Is added.

The output data S004 is the latch pulse S
At the same time, the selection circuit 0 stores the data in the register 020 as output data S003 of the register 020.
The selection circuit 011 supplies the output data S00 of the register 020 to the DI of the memory 000 as the output data S001 of the selection circuit 011.

The control circuit 207 has a read enable S21.
1 is set to "0", and then the write enable S210 is set to "0".
As 0 "→" 1 "→" 0 ", the added value of the arrival cell counter is written into the address specified by the channel number S204. _{This, C A (NO) = C} A (NO) +1 is executed It was done.

Next, the control circuit 207 sets the read enable S211 to “1” again, the value of the cell counter designated by the channel number S204 appears in the DO of the memory 000 as output data S005, and connects to the A0 of the selection circuit 202. Is done. Selection signal S connected to S of selection circuit 202
232, the external circuit 20
Since the mode signal S231 output from the control signal No. 6 is "1", the selection signal S232 and the selection signal S206 have the same polarity. Therefore, the output data S005 of the memory 000
Appears at the output S213 of the selection circuit 202 and the control circuit 2
07 is mixed with the output address S228, and this mixed signal S230 is connected to A0 of the selection circuit 012.
Since the selection signal S219 is "0", the mixed signal S230 is connected to the ADR of the memory 001.
The write enable S216 and the read enable S218 output from the control circuit 207 correspond to the selection circuit 013 and the selection circuit 013, respectively.
014 via the WE and the RE.

The control circuit 207 controls the arrival cell detection circuit 20
The channel number S204 supplied from 0 is assigned to the address S2.
Outputs 28, as a read enable S218 "1", the probability auxiliary distribution stored in the memory 001 ^{Q C}
_{The value of A} (CH, C _A (CH)) is output to DO as output data S
012, and this value is added by the half adder 031. The output S011 of the half adder 031 is latched in the register 21 by the latch pulse S224, and the output S010 of the register 021 is passed through the selection circuit 015. Data S009 is input to DI of the memory 001. After returning the read pulse S218 to “0”, the write enable S216 is changed from 0 → 1 → 0, and Q _A (j, C _A
The value obtained by adding (j)) is written to the memory 001. _{^{This, Q C A (CH, C}} A (CH)) = Q C A becomes _{(CH, C A (CH)} ) that + 1 is executed. Here, CH is the channel number of the arriving cell and is output as signals S204 and S228.

During this S time, the memory 100 storing the arrival cell counter C _B (i) is cleared to all zeros. Since the selection signal S206 is "0", the memory 1
The ADR of 00 is the address S output by the control circuit 207.
205 is connected, and the DI
0 "is connected. At the same time as changing the address S205 from 0 to M-1, the write enable S208 is changed from 0 to 1 to 0 for each address, and the memory 1 is changed.
00 is cleared to all zeros.

Count of arrival cells and probability complementary distribution per S time: C _B (i), Q ^C _B (j, k) During the next S time, the selection signal S 206 is set to “1”. S
Each time a cell arrives during time, the cell detection circuit 200
Is the channel number S2 of the cell in the ADR of the memory 100.
04, and supplies a cell detection signal S20 to the control circuit 207.
3 and the control circuit 207 supplies the read enable signal S20
9 is set to "1" and supplied to the memory 000, and the value of the cell counter designated by the channel number S204 is stored in the memory 100.
DO as output data S105.

The output data S105 is added to the half adder 130
, The output data S104 of the half adder 130 becomes a value obtained by adding 1 to the cell count value stored in the memory 100, and this output data S10
4 is held in the register 120 by the latch pulse S212, and at the same time, the output data S103 of the register 120 is output.
Is supplied to A0 of the selection circuit 111 and the selection circuit 1
11 supplies the output data S103 of the register 120 to the DI of the memory 100 as the output data S101 of the selection circuit 111. The control circuit 207 has a read enable S
209 to “0”, and then write enable S208
Is changed from “0” → “1” → “0”, and the value of the added arrival cell counter is written to the address specified by the channel number S204. Thus, C _B (NO) = C _B (NO) +1 has been executed.

Next, the control circuit 207 sets the read enable S209 to "1" again, and the value of the cell counter designated by the channel number S204 appears in the DO of the memory 100 as output data S105, and is connected to A1 of the selection circuit 202. Is done. Selection signal S connected to S of selection circuit 202
232, the external circuit 20
Since the mode signal S231 output from the control signal No. 6 is "1", the selection signal S232 and the selection signal S206 have the same polarity. Therefore, the output data S105 of the memory 100
Appears at the output S213 of the selection circuit 202 and the control circuit 2
07 is mixed with the output address S228, and this mixed signal S230 is connected to A0 of the selection circuit 012.
Since the selection signal S219 is "0", the mixed signal S230 is connected to the ADR of the memory 001.
The write enable S216 and the read enable S218 output from the control circuit 207 correspond to the selection circuit 013 and the selection circuit 013, respectively.
014 via the WE and the RE.

The control circuit 207 controls the arrival cell detection circuit 20
The channel number S204 supplied from 0 is assigned to the address S2.
28, the read enable S218 is set to “1”, and the probability complement distribution Q stored in the memory 001 is output.
^{The value of C} _A (CH, C _A (CH)) is output to DO as output data S
012, and this value is added by the half adder 031. The output S011 of the half adder 031 is latched in the register 21 by the latch pulse S224, and the output S010 of the register 021 is passed through the selection circuit 015. The signal S009 is connected to DI of the memory 001. After returning the read pulse S218 to “0”, the write enable S216 is changed from 0 → 1 → 0 to Q _A (j, C
_The value obtained by adding _A (j)) is written to the memory 001. _{^{This, Q C A (CH, C}} B (CH)) = Q C A (CH, C B (CH)) + 1 is executed. Here, CH is the channel number of the arriving cell and is output as signals S204 and S228.

During this S time, the memory 000 storing the arrival cell counter C _A (i) is all-zero cleared. Since the selection signal S206 is "1", the memory 0
The ADR of 00 is the address S output by the control circuit 207.
205 is connected, and the data “
0 "is connected. At the same time as changing the address S205 from 0 to M-1, the write enable S208 is changed from 0 to 1 to 0 for each address, and the memory 0 is changed.
00 is cleared to all zeros.

The above processing is alternately repeated, and the number of repetitions with the number of repetitions is N
Perform the measurement until the time. At the point in time when S × N time has elapsed, a complementary probability distribution regarding the arriving cells per S time is created in Q ^C _A (j, k) corresponding to the channel. During the next S × N time, the complementary distribution for each S time is created in Q ^C _B (j, k) and the probability complement distribution Q ^C
_A (j, k) is from an external circuit to the access enabled state, access is assumed to initialize the Q ^C _A (j, k) at the time of completion.

At the time when S × N time has elapsed, the complementary probability distribution QC _A (j, k) relating to the number of cells arriving per S time is created in the memory 001 for each channel.
During the next S × N time, the selection signal S219 is set to “1”, and the above processing is alternately and repeatedly performed.
The probability complementary distribution QCB (j, k) is created in the memory 101. During this S × N time, the memory 001 storing the complementary probability distribution Q ^C _A (j, k) is in a state where it can be accessed from the external circuit 206. It is assumed that the external circuit 206 clears the memory 001 to all zeros when the access is completed. Hereinafter, the processing of-is repeated.

[0097]

The distribution table creation circuit of the present invention comprises a first memory and a second memory for alternately counting arrival cells per unit time, and a first half adder corresponding to each memory. Since the second half adder is provided, the count value measured from the memory in which the measurement of the unit time is completed and the measurement is stopped in the first memory or the second memory is stored in the third memory.
Can be transferred to an external circuit including the memory of the above.

Further, even when the measurement per unit time has been completed and the memory for which the measurement has been completed is being initialized, the arrival cells per unit time can be continuously counted using the other memory. Accordingly, the probability distribution or the probability complement distribution can be created on the third memory without interrupting the measurement, and the measurement data can be obtained in real time.

[Brief description of the drawings]

FIG. 1 is a distribution table creation circuit diagram of the present invention (part 1).

FIG. 2 is a distribution table creation circuit diagram of the present invention (part 2).

FIG. 3 is a circuit diagram for creating a distribution table according to the present invention (part 3);

FIG. 4 is an explanatory diagram of a probability frequency distribution of the present invention.

FIG. 5 is an explanatory diagram of a probability frequency distribution according to the present invention.

FIG. 6 is an explanatory diagram showing a cell format.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Header part 2 ... Information part 000, 001, 100, 101 ... Random access memory 010,011,012,013,014,015 ... Selection circuit 110,111,112,113,114,115 ... Selection circuit 020,021 , 120, 121 ... Registers 030, 031, 130, 131 ... Half adder 200 ... Arrival cell detection circuit 202, 203, 205 ... Selection circuit 201, 204 ... Inverter 206 ... External circuit 207 ... Control circuit 208 ... Exclusive OR circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (73) Patent holder 000004237 NEC Corporation 5-7-1 Shiba, Minato-ku, Tokyo (72) Inventor Koichi Kihara 1-7-112 Toranomon, Minato-ku, Tokyo Oki Electric Inside the Industrial Co., Ltd. (72) Katsumi Uehara 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Tsutomu Kobayashi 1-7-12 Toranomon, Minato-ku, Tokyo Within Kogyo Co., Ltd. (72) Inventor Kohei Shiomoto 1-6-1, Uchisaiwaicho, Chiyoda-ku, Tokyo Within Nippon Telegraph and Telephone Corporation (72) Inventor Toshiya Ouchi 1-280 Higashi Koikebo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Inventor Hiroshi Ikeda 5-chome, Shiba 5-chome, Minato-ku, Tokyo No. 1 NEC Corporation

Claims (2)

(57) [Claims] 1. A multi contained in the ATM switching system
Creates a distribution table that observes the arrival process of cells transmitted from a number of channels and creates a distribution related to the number of arrival cells.
A circuit for detecting cells transmitted from the plurality of channels,
Channel information indicating the channel from which
An arrival cell detection circuit for transmitting a detection signal, and a first memo for storing a cell count value for each channel.
And checking the count value stored in the first memory.
A first half adder for adding a count value based on the output signal, and a second memorandum for storing a cell count value for each channel.
And the count value stored in the second memory is checked.
A second half adder for adding based on the output signal and the first memory for alternately counting the cell count per unit time.
And the first memory as stored in the second memory.
Initializing a memory or the second memory;
Either the half adder or the second half adder is used for the detection.
A first control unit that controls to operate based on the output signal
And the count value per unit time for each channel
Frequency to an address determined from the channel and the count value
By storing, it is possible to check the arrival cell for each channel.
A third memory for storing the rate frequency distribution, the value of the third of the frequency stored in the memory adder
And a third half adder that stops counting under the control of the first control unit.
The channel from the first memory or the second memory
Read the count value per unit time for each
A channel determined by the channel number and the read count value
I will add one of the frequency values stored in the dress
Control the third memory and the third half adder
And a second control unit that performs the control from the first memory and the second memory alternately.
By reading the count value per unit time,
Degree of arrival cell arrival for an integral multiple of the unit time
The number distribution is stored in the third memory.
Distribution table creation circuit. 2. A multi contained in the ATM switching system
Creates a distribution table that observes the arrival process of cells transmitted from a number of channels and creates a distribution related to the number of arrival cells.
A circuit for detecting cells transmitted from the plurality of channels,
Channel information indicating the channel from which
An arrival cell detection circuit for transmitting a detection signal, and a first memo for storing a cell count value for each channel.
And checking the count value stored in the first memory.
A first half adder for adding a count value based on the output signal, and a second memorandum for storing a cell count value for each channel.
And the count value stored in the second memory is checked.
A second half adder for adding based on the output signal and the first memory for alternately counting the cell count per unit time.
And the first memory as stored in the second memory.
Initializing a memory or the second memory;
Either the half adder or the second half adder is used for the detection.
A first control unit that controls to operate based on the output signal
When, every time the detection signal is sent, before the detection signal comprises
Channel number and the first or second memory
Frequency to the address determined from the count value stored in
Is stored, the arrival cell of each channel is
Adding a third memory for storing a probability complement distribution and the frequency stored in the third memory;
A third half adder, which controls the first control unit each time the detection signal is transmitted.
The first memory or the previous memory which performs counting operation
The channel indicated by the detection signal from any of the second memories.
Read the count value of the channel and read the channel number and
Stored at the address determined from the counted value
The third memory and the third memory are added so as to add the frequency by one.
And a second control unit for controlling the third half adder.
And alternately with the first memory or the previous memory every unit time.
The count value based on the detection signal from the second memory;
And updates the frequency stored in the third memory.
By renewing, the time of an integral multiple of the unit time
The probability complementary distribution of all arriving cells is stored in the third memory.
A distribution table creation circuit characterized in that a distribution table is created.