JP2641705B2 - Logic device exhibiting optical bistability without externally applied voltage and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical bistable logic element.
The present invention relates to a symmetrical seed (Symmetric Self Electro-optic Effect Device; hereinafter, referred to as 'S-SEED') which is an (optical bistable logic device) and a method of manufacturing the same. More specifically, the bistable property of light (o
Non-biased optically non-biased symmetrical seeds (non-biased optical) that exhibit optical bistable characteristics without the application of an external voltage for obtaining ptical bistability and can exhibit the function of optical logic circuits. Bistable S-SEED: Below, 'N
OBS ') and a method for producing the same.

[0002]

2. Description of the Related Art The bistable characteristic of light is a basic core concept that is fundamental in realizing future-oriented parallel signal processing, light conversion, and optical computers. Several devices that can implement this are known.

[0003] Among them, typical optical bistable logic elements include a multiple quantum well (hereinafter, referred to as "multiple quantum well") in an intrinsic region (intrinsic region).
A symmetrical seed (S-SEE) in which two PIN diode seeds having 'MQW' are connected in series
D) can be increased.

[0004] Such an S-SEED structure is described in David A.
B. Miller (US Pat. No. 4,546,2).
44).

An S-type semiconductor having a multiple quantum well (MQW) structure
In SEED, a photocurrent is generated by light absorbed from inside the MQW, and the voltage due to this photocurrent is applied again to the MQW, thereby affecting the light absorption characteristics of the MQW.

The S-SEED has an arrangement of two-dimensional elements which facilitates parallel light signal processing by utilizing the relatively small switching energy and utilizing the existing compound semiconductor manufacturing process. Has the advantage that it can be easily realized.

FIG. 1 is a sectional view of a conventional S-SEED, and FIGS. 2 and 3 are a plan view and an equivalent circuit diagram of FIG.

In FIG. 2, the same parts as those in FIG. 1 are denoted by the same reference numerals.

In FIG. 2, reference numeral 7 denotes a mesa (mes) of a PIN diode.
a) A boundary of a portion to be etched. Reference numeral 8 denotes a boundary of a portion to be etched for electrical isolation between elements.

As shown in FIG. 3, a conventional S-SEED
Are the same two PIN diodes SEED (D1, D
2) has a structure connected to each other in series.

A reverse voltage (VAP) is applied to the S-SEED, and each SEED is connected to another S-SEED.
It acts as a mutual load on the EED and has the property of bistable light. The reverse voltage (VAP) is applied to the metal pad 5 shown in FIGS.

In FIG. 1, reference numerals 1 and 2 indicate an n-contact layer and a p-contact layer for ohmic contact, respectively.

The n-contact layer 1 and the p-contact layer 2 between the two PIN diodes are interconnected by a metal wiring 4. The remaining n-contact layer and p-contact layer are formed by metal layer 4 formed by the same process.
An external power supply (not shown) is connected to the element through the metal pad 5. The two PIN diodes are an undoped quater-wavelength reflector stac on a semi-insulating substrate.
By etching up to k), they are electrically separated from each other.

On the structure thus formed, Si
An insulating layer 3 made of N _x or SiO ₂ is deposited to prevent electric crosstalk and oxidation of the surface.

The light source is a light input / output window (optical window) 6.
To the PIN diode.

The method for manufacturing such an S-SEED will be described below with reference to FIGS.

A) Mesa wet etching up to n-layer, each PIN
The diode 7 is formed.

B) To electrically isolate each PIN diode, etch down to a non-doped quarter-wave reflective layer.

C) Deposit n-contact layer 1 for ohmic contact of n-layer.

D) An insulating layer 3 is deposited to prevent electrical crosstalk and oxidation of the surface.

E) The light input / output window 6 is opened, and the insulating layer 3 of the n-contact layer 1 and the p-contact layer (see 2) is etched for connection between metals.

F) Deposit p-contact layer 2 for ohmic contact of p-layer.

G) Deposit a wiring metal 4 for electrical wiring.

H) Deposit a thick metal pad 5 for wire bonding.

As described above, when two identical PIN-type diode SEED modulators are connected in series with each other, and when a voltage VAP in the opposite direction is applied, each SEED
Acts as a load on other SEEDs.

At this time, the voltage in the reverse direction of SEED (VA
The characteristic of the photocurrent with respect to P) is a multiple quantum well (MQW).
Therefore, the voltage applied to each diode does not become VAP / 2 as in a general linear circuit.

FIG. 17 shows a 4 × 8 two-dimensional array using a general S-SEED.

Even if the two-dimensional array becomes large, a similar composition can be obtained.

As shown in FIG. 17, in a general two-dimensional S-SEED arrangement as shown in FIG. 17, since a reverse voltage must be applied to each S-SEED, a metal wire is provided between the S-SEEDs. Must be located and require metal pads for wire bonding.

FIG. 18 shows an equivalent circuit of such a two-dimensional array. All S-SEEDs are electrically connected.

In such a composition, one SS
When an electric short circuit occurs even in the EED, the desired reverse voltage cannot be applied between both electrodes.
The whole array cannot be used.

Further, when the number of arrangements in manufacturing is large, the danger of mutual contact between the metal wire for p-layer contact and the metal wire for n-layer contact increases.

The S-SEED having such a structure is shown in FIG.
As shown in the figure, when manufacturing with a two-dimensional array,
A metal wiring for applying a voltage in the reverse direction, a metal wiring for connecting elements, and a metal pad for wire bonding must be included. In configuring a circuit, an electric wire to an external power supply is required.

The arrangement of the electric wires on the board and the external electric wires cause mutual induction between the electric wires, mutual interference by an electromagnetic field, crosstalk, and the like.

In particular, when forming an array of S-SEEDs, the cathode of each S-SEED connected to a power source is
It must be connected to all ones (similarly for the anode connected to the power supply). Each S-SE
The ED cannot be electrically isolated.

Therefore, S-SEE forming a two-dimensional array
When the number of D is increased, the above problem becomes more serious, and the yield of the device is greatly reduced, and the degree of integration is also reduced.

Further, since the metal wiring and the electric wire act as a parasitic passive component when forming the SEED and S-SEED circuits, they have disadvantages in high-speed switching.

S-S which requires a general reverse voltage
The above-mentioned problems of the EED and S-SEED arrangements can be solved by an element which exhibits bistable characteristics of light without externally applying a voltage and can function as an optical logic circuit. can do.

FIG. 5 shows a load curve of the photocurrent Ip of a general S-SEED circuit.

In FIG. 5, the voltage V is a voltage applied to the first diode (D1) shown in FIG. The solid curve and the dotted curve show the relationship between the voltage (V) and the diode D1.
And D2 load curves, respectively.

In the case of the operating point A, the diode D1 has V ≒
0 is applied, and VAP-VＶ is applied to the diode D2.
A voltage of VAP is applied.

On the other hand, in the case of the operating point B, V ≒ V is applied to D1.
The voltage of the AP is applied, and VAP-V is applied to the diode D2.
A voltage of $ 0 is applied. That is, the S-SEED circuit is
Two PIN diodes having the same structure are connected in series, but different voltages are stably applied to each SEED.

Therefore, mutually different electric fields are applied to the MQWs located in the intrinsic regions of the respective elements constituting the S-SEED, whereby the light absorption rates of the respective elements are different. The different light absorptances are the reflectivities of the SEEDs (transmission S
In the case of the EED, the transmittance is made different. The S-SEED circuit has a positive feedback characteristic due to the characteristic of the nonlinear photocurrent generated by the absorbed light.
The SEED circuit can have optical bistability, which is a requirement of the optical logic element as shown in FIG.

In FIG. 6, R indicates the reflectivity of the light of the SEED, Pin indicates the intensity of the input light input to the SEED, and ΔP indicates the stable width of the light from the S-SEED. , Ron is the reflectance in the ON state, Ro
ff is a reflectance in an off state, and ΔR is
The differences in light reflectance (Ron-Roff) are shown.

A general SEED is based on the quantum constraint effect (Quantum effect).
um Confined Stark Effect; hereinafter, referred to as “QCSE”).

Here, the QCSE is a heavy hole exciton absorption peak of a heavy hole exciton of MQW.
peak) is changed to red by application of an electric field, so that the absorptivity of light from the fixed operating wavelength of the MQW is reduced nonlinearly, thereby changing the photocurrent and reflectivity of the device nonlinearly. , The optical on / off state can be changed.

The non-linear characteristics of the MQW enable the SEED to be used as an optical logic element according to the principle of the S-SEED circuit described above.

FIG. 7 shows such a quantum constraint effect (QCS
S-SEE composed of SEED using E)
From the D circuit, when the external applied voltage VAP = 0,
4 shows a load curve of a SEED circuit.

As can be seen from FIG. 7, when VAP = 0, the intersection of the two curves, that is, the operating point of S-SEED is
One of C. Accordingly, in each of the SEEDs constituting the S-SEED, a voltage of V = 0 is constantly applied to the two diodes even if a photocurrent is induced by the incident light. As shown, the energy band in a state of thermal equilibrium is maintained.

Therefore, only the electric field due to the intrinsic voltage VBI generated by the PIN diode is applied to the MQW forming the intrinsic region of each SEED.
Since the two diodes are identical to each other, when VAP = 0, optical bistability cannot be obtained.

This is the SEE using the general QCSE.
ΔEC which is the difference between the energy of the conduction band of the barrier layer and the energy of the conduction band of the well layer in D is large, and
This is because the total thickness d of the MQW in the intrinsic region is large, and the electric field due to the intrinsic voltage distributed in the intrinsic region is small (in FIG. 8, EC indicates the energy of the conduction band, and EV indicates the valence band. And EF indicate Fermi energy, respectively).

Such an electric field is not enough to separate the electron-hole pairs generated in the quantum well by light absorption through the barrier layer into the anode layer and the cathode layer. Even if the rate decreases due to the increase of the electric field, the point D, which is the maximum value of the photocurrent, is changed to the voltage in the opposite direction (the right side in FIG.
In other words, when VAP = 0 obtained from the first upper limit), a stable operating point having non-linear photocurrent characteristics other than point C is not allowed.

FIG. 9 shows a load curve of the S-SEED circuit when the intrinsic region of the SEED structure is formed by a thin multiple quantum well (hereinafter, referred to as “SMQW”) structure.

In FIG. 9, VE represents the voltage applied to the diode D1 when the operating point of the S-SEED circuit composed of the thin quantum well (SMQW) is E when VAP = 0. VF indicates the voltage applied to the diode D1 when the operating point of the S-SEED circuit composed of the MQW when VAP = 0 is F.

FIG. 10 shows an S-band having the same load characteristics as FIG.
FIG. 3 illustrates an energy band of a SEED circuit in a state of thermal equilibrium.

FIG. 9 differs from FIG. 7 in that stable operating points E and F exist even when VAP = 0. this is,
This means that different voltages can be applied to the two SEED elements forming the S-SEED. Thus, even when VAP = 0, optical bistability is formed.

This can be seen from FIG.
This is because the difference between the conduction band energies of the well layer and the barrier layer is very small at 30 meV or less at room temperature, so that low voltage absorption is not performed. That is, S of the SMQW structure
The EED is a flat band (Flat Band) (electric field = electric field) by ionization by an electric field only by an intrinsic voltage generated by a PIN type diode.
Only in the presence of 0) or a very small electric field, the trappable exciton level is eliminated, greatly reducing the light absorption from the operating wavelength.

Therefore, the maximum value of the photocurrent (point G) is
When a certain positive voltage is applied to the PIN type diode and only a very small electric field is present in the symmetric SMQW (ie, the exciton can be bound and generated while maintaining a high optical absorptance). Electron-hole pairs can be easily separated into an anode and a cathode to produce many positive photocurrents). Therefore, SEED using SMQW can maintain optical bistability even when VAP = 0.

As described above, the self-biased S-SEED which is operated without applying an external voltage is different from the case where an existing external voltage is required when forming an array. However, since it can be designed to be electrically independent, high-density integration is possible and the yield can be increased.

Further, such an S-SEED is required to electrically install a wiring connection pad for applying an external voltage, a long metal wire from an array to a pad, an electric wire from an array to a power supply source, and the like. Since there is no need, there is no mutual induction between wires, preventing mutual interference and crosstalk due to electromagnetic fields, and it also has advantages such as not requiring special element design for high-speed switching. Can be.

However, even in the case of the SEED using the SMQW structure as described above, in order to absorb a large amount of positive light, similarly to the SEED using the general QCSE, the SEED using the MQW structure forming the intrinsic region is used. All thickness d is 1 μm
It is necessary to make it large. The structure of the most widely used PIN-type diode SEED made of AlGaAs / GaAs will be described as an example.

VB1 ≒ 1.5 Volts, and the operating point in FIG.
, The voltage VE applied to the diode D1 =
Assuming that 0.9 Volts and d = 1.0 μm, the diodes D1 and D2 have VBI-VE = 0.6 Volts respectively.
And electric field 6.0 due to a voltage of VB1 + VE = 2.4 Volts
× 103 V / cm and 2.4 × 104 V / cm are formed respectively.

The electric field difference of this degree is from VAP = 0 to S
Although it is a value that can measure the bistable of light from the MQW structure S-SEED, its value is not enough, so that the value of the reflectance difference ΔR = Ron-Roff is small, and the practical possibility in an optical system is low. It is sparse.

As described above, a thin multi-quantum well (SMQW) is used as a self-biased S-SEED that can have optical bistability without application of an external voltage. A structure and a structure using an asymmetric quantum well are known.

The existing PIN-type diode SEED structure utilizing these features does not differ much from a general SEED structure utilizing the quantum confinement effect (QCSE). That is, in order to absorb a lot of positive light, the total thickness of the multiple quantum well (MQW) forming the intrinsic region had to be increased.

Therefore, the self-bias type S-SEE
Since the intrinsic electric field due to the intrinsic voltage of the PIN type diode that enables D is small, the change in reflectivity for optical bistable and the width of optical bistable are difficult to use in a substantial optical system. There were not enough disadvantages.

As an existing non-voltage bistable symmetric seed (NOBS) capable of achieving optical bistability without application of an external voltage, a thin quantum well (Extremely Shallow Quantum Well) as MQW is used. Hereinafter, “ESQ
W "), Asymmetric Coupled
Quantum Well (hereinafter referred to as “ACQW”), Strained MQW (hereinafter referred to as “SMQW”)
Asymmetric Fabry Perot (asymmetr)
ic Fabry-Perot) resonance structure and thin multiple quantum wells (E
SQW), an asymmetric Fabry-Perot resonance structure and an asymmetric quantum well (asymmetr).
An S-SEED having a structure of ic coupled quantum well (hereinafter, referred to as “ACQW”) is known.

However, when these are applied to the existing general reflection type SEED structure, that is, the total thickness of the MQW which constitutes the intrinsic region due to the absorption of a lot of positive light is reduced by one.
When the thickness is increased to about μm, there is a disadvantage that the bistable characteristic of light without voltage is very small. This is NO
The intrinsic electric field due to the intrinsic voltage of the PIN diode that enables BS is a SE with a typical intrinsic region thickness of 1 μm.
This is because it is small in the ED structure.

As a method proposed to solve the problem of NOBS and to increase the ON / OFF contrast ratio (hereinafter, referred to as “CR”), there is a light input method. There have been proposals that use the resonance structure of AFP with matched resistance. This is because when considering the degree of light absorption of MQW, the thickness of all quantum wells for light absorption required to form the resonance structure of the AFP with matched light input resistance is generally reduced. This is because the intrinsic electric field with respect to the intrinsic voltage set by the simple structure can be greatly increased.

However, the reflectance in the off state is set to zero (zero)
In the case of using an AFP whose input resistance of light to be matched is equal to that of the AFP, there is an advantage that the CR is very large (theoretically infinite). There is a disadvantage that the difference (ΔR) and the width of the bistable light (ΔP) are relatively small.

FIG. 11 shows a well-known reflection type SE.
1 shows one example of an ED structure.

In this structure, the first λ / 4n reflective layer 12 having a large refractive index on the substrate 11 and having a large refractive index at which the operating wavelength of the excitons of MQW is １ ／ is formed on the substrate 11. A lower reflective layer is formed by periodically growing a second λ / 4n reflective layer 13 having a refractive index, and a PIN diode having an MQW intrinsic region is formed thereon. Generally, the uppermost layer is subjected to an antireflection treatment to increase the light absorption efficiency of the device. In the formation of the PIN diode, the layer 14 is an n- layer and the layer 18 is a p-layer.
The layer 14 may be formed as a p-layer and the layer 18 may be formed as an n-layer.

The p-layer, the n-layer, the barrier layer, the buffer layer, and the reflection layer, excluding the quantum well layer, must all be materials that do not absorb light at the operating wavelength.

On the other hand, as shown in FIG. 12, an upper reflective layer is formed by laminating a QWL on the upper part, and the thickness (L) from the lower reflective layer to the upper reflective layer is determined by setting the optical distance to be one of the operating wavelength. / 4
If the adjustment is made so as to be a constant multiple of AFP, an AFP structure in which the mode of the AFP and the resonance wavelength of the exciton are matched is formed. At this time, it is possible to obtain an AFP structure in which the reflectance (Rf) of the upper reflection by the air / semiconductor interface is 0.32 without laminating the QWL for the upper reflective layer.

FIG. 13 shows the MQ of the reflection type SEED.
It shows one example of the reflectance by the square of the light absorption coefficient (α) of W and the total thickness (D) of the light absorption layer, and shows a general reflection in which the antireflection layer is filled. SEED in shape
And the reflectance (Rf) of the upper reflection is 0.3
2. It is related to the structure of AFP-SEED which is 0.5.

In FIG. 13, A1 and A2 are respectively Rf =
The value of αD that satisfies the condition for matching the light input resistance of AFP-SEED with 0.32 and AFP-SEED with Rf = 0.5 is displayed.

Since the absorption coefficient (α) of light of MQW is determined by the structure of MQW, it generally decreases from the resonance wavelength of the excitons of MQW by increasing the electric field, as shown in FIG. .

Therefore, a decrease in α due to an increase in the electric field induces an increase in the reflectivity (R) as shown in FIG. 13 and normally satisfies the condition that the reflectivity increases due to an increase in the electric field. As a result, the light has bistable characteristics.

Such a normally-off condition is based on AFP-
In the case of SEED, it is possible from the area on the left side of the fulcrums A1 and A2 that satisfies the coincidence of the light input resistance from FIG.

As one example, the reflectance of the on-state and the off-state with respect to the square of D and αoff (α in the off-state) of the SEED filled with the antireflection layer and the AFP-SEED with Rf = 3.2. FIGS. 15 and 16 show the ratio (or on / off intensity ratio) (CR) and the difference (ΔR) in consideration of the case where the value of αon / αoff is 0.35.

From FIG. 15 and FIG. 16, point A1 is AFP-SEED with resistance matching, and point B1 is AF with resistance mismatch.
Each shows P-SEED.

From the point A1 in the AFP-SEED which satisfies the condition that the input resistance of light is matched, the value of CR is very large as shown in FIG. 15, but the ΔR value in FIG. 16 is small to 0.2 or less. Value.

On the other hand, the value of the on / off intensity ratio (CR) is 1 from the point B1 which satisfies the condition of the light input resistance mismatch.
Maintaining a sufficient value of about 0 allows the value of the reflectance difference (ΔR) to be maintained at about 0.3. In particular, NOB
In S, since the value of α is changed only by the intrinsic voltage without an external applied voltage, the value of αon / αoff becomes smaller than 0.35, so that the value of ΔR becomes relatively small, and the value of CR becomes smaller. It becomes more necessary to keep the value at the required minimum and to maximize the value of ΔR.

In the case where the input resistances of the light are not matched, A
FP-SEED is phase-matched.
ng), that is, the mode of AFP and the resonance wavelength of the exciton are matched. The thickness of L satisfying the conditions can be maintained, and the number of MQW cycles can be reduced to facilitate implementation.

[0085]

SUMMARY OF THE INVENTION The present invention eliminates the problems associated with optical logic devices that require a reverse voltage by greatly increasing the optical bistability without the application of an external voltage. At the same time, the main object is to provide a self-biased S-SEED light logic element that can be put to practical use in an optical system.

Another object of the present invention is to significantly increase the bistability of light even without the application of an external voltage, thereby reducing the problems of a general optical logic element requiring a reverse voltage. A voltageless optical bistable logic element, such as an asymmetric Fabry-Perot thin quantum well seed (AFPSQWS-SEED) or an asymmetric Fabry-Perot asymmetric quantum well seed (AFPACQWS-SEED) that can be removed. An object of the present invention is to provide a device layout (lay-out) that can be manufactured simply and efficiently.

It is still another object of the present invention to provide a structure for simplifying the electrical connection between the diodes of the optical bistable logic element and increasing the degree of integration of the element.

Yet another object of the present invention is to enable electrical isolation of a voltageless optical bistable logic element that operates without the application of an external voltage so that it can be implemented in an overall two-dimensional array. Even if a defect occurs in a part, the remaining S-SEED elements are not affected, and a two-dimensional array of non-biased optical bistable S-SEs (NOBSs) unrelated to some defects.
ED).

Still another object of the present invention is to appropriately maintain CR in the production of NOBS using an AFP resonance structure that can significantly increase the bistable characteristics of light without the application of an external voltage. It is intended to provide a structure for maximizing ΔR and Δ.

[0090]

According to a first aspect of the present invention, there is provided a SEED (Selr Electr
o-optic Effective Device)
A semi-insulating GaAs substrate, a first reflective layer grown on the substrate to a predetermined thickness and having a predetermined refractive index (n), and grown to a predetermined thickness on the first reflective layer; A reflective layer comprising a second reflective layer having a refractive index different from the refractive index of the first reflective layer; and a lower reflective layer formed repeatedly at least 12 periods or more, and a predetermined reflective layer formed on the lower reflective layer. A first electrode contact layer grown to a thickness, a first buffer layer grown on the first electrode contact layer, and a barrier layer and a thin quantum well layer on the first buffer layer at a predetermined period. A thin multi-quantum well layer to be grown; a second buffer layer grown on the thin multi-quantum well layer; and a second buffer layer grown on the second buffer layer.
A voltageless optical bistable logic element including an electrode contact layer is provided.

The thin multi-quantum well layer may be formed by growing a barrier layer and a thin quantum well layer in 36 cycles.

[0092] The refractive index of the first reflective layer may be relatively smaller than the refractive index of the second reflective layer.

Further, the refractive index of the first reflective layer may be relatively larger than the refractive index of the second reflective layer.

The contact layer of the first electrode may be a P ⁺ anode contact layer, and the second electrode contact layer may be a N ⁺ cathode contact layer.

The first electrode contact layer may be an N ⁺ cathode contact layer, and the second electrode contact layer may be a P ⁺ anode contact layer.

The first reflection layer is made of undoped AlAs, and the second reflection layer is made of undoped Al _{x Gal x} As (0.1 < x < 0.3). be able to.

Further, in order to achieve the above object, the present invention
According to the second embodiment, SEED (Self Electro-optic
Effective Device)
And a predetermined refractive index on a semi-insulating GaAs substrate.
The first λ / 4n reflection layer made of AlAs having (n)
Here, [lambda] is the wavelength of light) grown to a thickness of about 72.1 nm.
Al having a relatively high refractive index_xGa_lxA
s (0.1<x<0.3) second λ / 4n reflection layer
Is grown to a thickness of about 60.7 nm, and the first λ / 4
n reflection layer and the second λ / 4n reflection layer in at least 12 periods.
Forming a lower reflective layer by forming
N on the lower reflective layer⁺Mold Al_xGa_lxAs (0.1
<x<0.3) is grown to a thickness of about 500 nm.
Forming a sword contact layer; and
Undoped Al_xGa_lxAs (0.1
<x<0.3) is grown to a thickness of about 20 nm to form the first
Forming a buffer layer; and forming a barrier layer on the first buffer layer.
Al with a thickness of about 6 nm_xGa_lxAs (0.1<
x<0.4) A layer having a thickness of about 10 nm
GaAs layers that have not been doped are sequentially grown,
The barrier layer and the well layer are grown in 36 cycles to be thin.
Forming a multi-quantum well layer (SMQW);
On a thin multiple quantum well layer, a thickness of about 20 nm is formed.
Al not pinged_xGa_lxAs (0.1<x<
0.3) forming a second buffer layer by growing
On the second buffer layer, a thickness of about 506.7 nm⁺Type
Al_xGa_lxGrow As (0.1 <x <0.3)
Forming an anode contact layer by applying
A method of manufacturing a bistable optical element is provided.

Further, according to a third aspect of the present invention, there is provided a structure in which the logic elements of the first aspect are two-dimensionally arranged.

According to a fourth aspect of the present invention, there is provided an n-contact layer, a p-contact layer, and a light input / output window. A first and second PIN diodes are connected in series, and the optical absorption from the quantum well region is changed by a photocurrent generated from the PIN diode. A non-voltage optical bistable logic element is provided that directly connects the contact layer of the diode and the contact layer of the second PIN diode.

The n-contact layer of said first PIN diode,
The light input / output window, the p-contact layer and the n-contact layer of the second PIN diode, the light input / output window, the p-contact layer The first PIN is arranged in a straight line in the horizontal direction.
The n-contact layer of the diode and the p-contact layer of the second PIN diode, and the p-contact layer of the first PIN diode and the n-contact layer of the second PIN diode may be connected to each other by a metal wiring.

The first PIN diode and the second PI
Although it is arranged in parallel with the N diode, the first P
The p-contact layer of the second PIN diode is located at a predetermined distance on the right side immediately adjacent to the n-contact layer of the IN diode, and the light input / output windows of the first and second PIN diodes are parallel. And the n-contact layer of the second PIN diode is located on the same straight line to facilitate the processing of the optical signal of the second PIN diode at a predetermined distance from the p-contact layer of the first PIN diode. And an n-contact layer of the first PIN diode and the second PIN diode.
The p-contact layer of the PIN diode, the p-contact layer of the first PIN diode, and the n-contact layer of the second PIN diode may be connected to each other by a metal wiring.

According to a fifth aspect of the present invention, there is provided a multi-quantum well (MQ) as an intrinsic region.
W) and an upper reflective layer and a lower reflective layer having mutually different reflectivities with respect to the resonance wavelength of the exciton in the multiple quantum well, wherein the resonator length is equal to the resonance wavelength of the exciton. Multiplexing of an asymmetric Fabry-Perot optical bistable logic element (AFP-SEED) having a matched optical input resistance in a Fabry-Perot (AFP) optical bistable logic element Quantum well (MQ
By having multiple quantum wells with a period number relatively smaller than the period number of W), the total thickness of the light absorbing layer (D)
A non-voltage optical bistable logic element with a mismatched light input resistance is provided.

[0103]

FIG. 19 is a circuit diagram of a seed device (NOBS) according to the present invention that exhibits optical bistability without application of an external voltage.

The production process of the NOBS according to the present invention is almost the same as that of a general S-SEED.
SEED is a voltage-free optical bistable element (Nobiased Optic
al Bistable devics), so conventional circuit (Fig. 3)
No external applied voltage is required as in the above. Therefore, unlike FIGS. 1 and 2, the metal pad 5 is not required.

FIGS. 20 and 21 are plan views showing the configuration of a bistable seed of a voltageless light having a structure according to the present invention. FIG. 20 shows a composition of an arrangement in which diodes D1 and D2 identical to those of a general S-SEED structure are arranged in parallel, and FIG. 21 is different from a general PIN diode arrangement in that each diode has an opposite arrangement. 2 shows a composition arranged in the direction of.

20 and 21, the same or corresponding components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals as those in FIGS. 1 and 2.

Referring to FIG. 21, D1 on the left side in FIG.
Has an n-layer on the upper side, a p-layer on the lower side, and D2 on the right side.
Indicates that the p-layer is located on the upper side and the n-layer is located on the lower side.
The layers and the n-layer are positioned to be easily connected to the n-layer and the p-layer of D2, respectively.

On the contrary, the p layer is positioned above D1 on the left side, the n layer is positioned below D1, the n layer is positioned above D2 on the right side, and the p layer is positioned below D2.
It is also possible to position the layers. At this time, the window 6 (Optical window) of each diode must be horizontally aligned in order to easily perform parallel optical signal processing.

With such an arrangement, the portion 8 wet-etched for electrical isolation to the lower reflective layer shown in FIG. 1 is not positioned on a horizontal line. In this way, the length of the metal 4 for connecting the diodes D1 and D2 and the area forming the S-SEED can be minimized.

FIG. 22 and FIG. 23 are diagrams showing the NO proposed by the present invention.
1 shows an example of a configuration in which BSs are two-dimensionally arranged.

FIG. 22 shows a configuration in which the NOBSs of FIG. 20 are two-dimensionally arranged, and FIG.
Are arranged two-dimensionally.

As can be seen from the equivalent circuit shown in FIG. 24, unlike the prior art (FIGS. 17 and 18), it is understood that the respective NOBSs are completely electrically separated from each other.

Therefore, NOBS forming a two-dimensional array
The occurrence of a short-circuited NOBS does not affect other NOBSs that form a two-dimensional array together.

Therefore, when an apparatus for performing parallel optical signal processing is configured using the NOBS configuration presented by the present invention, an optical signal processing apparatus complementary to some defects is configured. It is possible.

Further, the two-dimensional array based on the NOBS composition proposed by the present invention is a general S-SEED array (FIG. 1).
Unlike 7), since a metal line for applying an external voltage between elements is not required, the degree of integration can be increased, and the metal line between elements can be minimized. Thus, parasitic passive elements (resistance, inductance, capacitance) induced on the semiconductor substrate can be reduced. This can be further reduced, especially using the example composition of FIG.

As described above, according to the present invention, an AFP having a large optical bistability without an applied voltage is provided.
ESQW S-SEED, AFP ACQW SS
EEDs or their two-dimensional arrays and mixed-type applied optical elements and arrays using the same can be easily manufactured.

When the structure of the bistable logic element of no-voltage light according to the present invention is used, when forming a two-dimensional array, each element can be electrically separated, so that the yield of the elements is increased. Can be irrelevant to some defects 2
Since it is possible to arrange the dimensions, and since a metal wiring for applying an external voltage and a space for the metal wiring for the external voltage are not required, the degree of integration can be greatly increased.

In addition, it is possible to reduce not only a mutual induction effect between electric wires, a mutual interference by an electromagnetic field, a phenomenon of crosstalk between elements, etc., but also to easily realize a circuit for a high-speed switching element.

Also, when assembling a semiconductor component using the logic element of the present invention, it is not necessary to connect wires for wire bonding and external voltage application, so that the process is simplified and the unit cost of the process is reduced. It is also expected to have the economic effect of being able to do so.

FIG. 25 shows a bistable seed (N
SMQW-AS according to the invention for realizing OBS)
It is sectional drawing which shows the desirable example of FP-SEED structure.

First, a first λ / 4n reflection layer (Quarter Wavelength Reflector) made of AlAs having a relatively low refractive index (n = 2.98) is formed on a semi-insulating GaAs substrate 21.
or Stack) (where λ is the wavelength of light) 22 is 72.1n
m and a relatively high refractive index (n = 3.
54) the second λ / 4n made of Al _0.1 Ga _0.9 As
The reflection layer 23 is grown to a thickness of about 60.7 nm, and the first λ / 4n reflection layer 22 and the second λ / 4n reflection layer 23 are formed.
Λ / 4n reflection layer (Quarter Wavelength R)
eflector Stack, QWRS) is formed. In this case, the optical thickness of each layer is set to be １ ／ of the operating wavelength of 860 nm (wavelength of the absorption peak of excitons of SMQW). At this time, the reflectance of the reflective layer 30 becomes 95% or more.

As described above, the first λ / 4n reflection layer 2
2 and the second λ / 4n reflective layer 23 are repeatedly grown for 12 cycles or more (preferably 14 cycles) to form the lower reflective layer 30, and then the N ⁺ type (5 5 × 10 ¹⁸ cm ~ ³ ) Al _0.1 Ga _0.9 As
The cathode contact layer 24 is formed by growing to a thickness of about 00 nm.

Subsequently, undoped A1 _0.1 Ga _0.9 As is grown on the cathode contact layer 24 to a thickness of about 20 nm to form a first buffer layer 25.

Thereafter, an Al _0.04 Ga _0.96 As barrier layer 26 having a thickness of about 6 nm is formed on the buffer
A thin quantum well layer (SMQW) 31 having a small thickness is formed by growing multiple (preferably 36 periods) thin quantum wells composed of the GaAs well layer 27 having a thickness of about the same.

Subsequently, the thin multiple quantum well layer 31 described above is formed.
On top, A which is not doped to a thickness of about 20 nm
The second buffer layer 28 is formed by growing 1 _0.1 Ga _0.9 As.

Finally, 506. on the second buffer layer 28.
A1 of P ⁺ type (1 × 10 ¹⁹ cm ~ ³ ) with a thickness of about 7 nm
_An anode contact layer 29 is formed by growing _0.1 Ga _0.9 As.

The PI manufactured by the above steps
In an N-type SEED, the total thickness (L) of the layers 24-29 above the λ / 4 reflective layer (ie, the lower reflective layer) 30
Becomes 1622.7 nm, and the reflection layer 30 is formed of an asymmetric Fabry-Bellow resonator (Cavity).
(ASPF). The length of the cavity is λ
/ 4n _avg (where n _avg is the average refractive index of the cavity)
27 times (odd constant times).

As a result, an upper reflection having a reflectivity of about 30% is naturally generated at the boundary between the air and the semiconductor.

Therefore, P which sets SMQW as a genuine region
In the structure of the -I (MQW) -N diode, an ASFP resonance structure is formed in which the reflectances of the upper and lower reflections are different from each other. At this time, the number of repetitions (number of cycles) of the MQW is a condition that satisfies the following equation 1 in which the reflectance (RT) of the entire ASFP cavity becomes zero from a state without an external voltage application, that is, from zero bias. It is determined as a numerical value m.

RF = RBexp (−2α ₀ mt) (1) where RF is the reflectance of the upper reflection, RB is the reflectance of the lower reflection, and α ₀ is the quantum well at zero bias. And the t is the quantum well thickness.

In the structure of FIG. 25, α ₀ is 16000
cm ~ ¹ , RF = 0.3, RB = 0.
Since 95 and t = 10 nm, the value of m that satisfies Equation 1 for RT = 0 is 36. Therefore, the number of periods 36 of the quantum well is determined. Therefore, the total thickness of the genuine region including the SMQW is reduced to about 0.62 μm, and the electric field due to the intrinsic potential in a state of thermal equilibrium is
It has a value of 2.4 × 104 V / cm.

As described above, the electric field due to the increased intrinsic potential can further increase the reflectance Ron by further reducing the light absorption of the SMQW. Assuming that the electric field applied to the diode D1 is a general SMQWS-SEED value of 0.6 × 103 V / cm, d = 0.62 μm.
2 can be increased to 4.2 × 10 4 V / cm to increase optical bistability. This value is
This is similar to the electric field value applied to D2 when a reverse voltage of 1.8 Volts is applied to a general SMQWS-SEED with d = 1.0 μm.

Equation 1 is a condition for setting the value of Roff of ASFP-SEED to 0. The structure of the ASFP resonance is
When the uppermost layer of the lower reflective layer is made of a material having a high refractive index (in the case of FIG. 25 of this embodiment, an AlGaAs layer), it can be obtained by setting its thickness to only an odd multiple of λ / 4n _avg. it can. When the Roff value of ASFP-SEED is allowed to be about 5%, the number of periods of the quantum well can be further reduced, and the inherent electric field can be further increased. 21
When the ASFP structure made of a periodic SMQW is further reduced to, for example, the thickness of the intrinsic region to 0.38 μm, the electric field applied to the diode D1 is reduced by a general SMQWS-S
Assuming an EED value of 0.6 × 10 ³ V / cm, the electric field applied to D2 increases to 7.3 × 10 ⁴ V / cm. This value is SMQWS where d = 1.0 μm
-A value similar to the electric field applied to D2 when a reverse voltage of 5.0 Volts is applied to SEED.

Therefore, S shown in the present embodiment is
Using MQW-ASPF-SEED, existing SM
Much larger than S-SEED circuit using QW,
Not only can the optical bistability without external voltage be obtained, but also the S-SE made of the existing SMQW-SEED
A light bistability similar to that obtained when VAP = 5.0 Volts is applied to the ED circuit is possible.
A self-biased S-SEED that is a bistable element of light without an externally applied voltage can be realized.

FIG. 26 is an explanatory view showing the structure of an SMQW-ASPP-SEED according to another embodiment of the present invention for realizing a light bistable seed (NOBS) without an external voltage.

In FIG. 26, is it the same as FIG.
Alternatively, corresponding parts are indicated by the same reference numerals.

The method of manufacturing this structure will be described as follows.

Referring to FIG. 26, first, semi-insulating GaAs
On the s substrate 21, Al _x Ga _{1 -x} As (0.1 < x <
0.3), a λ / 4n reflective layer (here, λ is the wavelength of light) 23 is grown, and a λ / 4n reflective layer 22 made of undoped AlAs having a relatively low refractive index is formed. Let it grow. By forming these two reflective layers 23 and 22 for 12 cycles or more (preferably 14 times), the lower reflective layer 30 composed of a λ / 4 reflective layer (QWRS) is formed. At this time, the optical thickness of each layer is set to be 1/4 of the operating wavelength (the wavelength of the absorption peak of the exciton of SMQW).

As described above, the two λ / 4n reflection layers 2
After the lower reflective layer 30 is formed by repeatedly growing 3,22 over 12 periods (preferably 14 periods), N ⁺ -type Al _x Ga _{1 -x} As is formed on the lower reflective layer 30.
(0.1 < x < 0.3) to grow the cathode contact layer 2
4 is formed.

Subsequently, undoped Al _x Ga _{1 -x} As (0.1 < x <
0.3) is grown to a predetermined thickness to form the first buffer layer 25.

Thereafter, an undoped Al _x Ga _{1 -x} As barrier layer (0.01 < x
< 0.04) 26 and a thin quantum well composed of undoped GaAs well layer 27 (preferably 3
Multi-quantum well layer 31 grown to 6 periods)
Is formed.

Subsequently, the thin multiple quantum well layer 31 described above is formed.
On top, undoped Al _x Ga _{1 -x} As (0.
By growing 1 < x < 0.3), the second buffer layer 26 is formed.

Finally, a P ⁺ -type Al _x Ga _{1 -x} As (0.1 < x < 0.3) is grown on the second buffer layer 28 to form an anode contact layer 29.

FIG. 27 shows a bistable seed (N
FIG. 11 is an explanatory diagram showing a structure of an SMQW-ASPP-SEED according to another embodiment of the present invention for realizing (OBS).

In FIG. 27, parts that are the same as or correspond to those in FIG. 25 are denoted by the same reference numerals.

The method of manufacturing this structure will be described as follows.

Referring to FIG. 27, first, semi-insulating GaAs
On the s-substrate 21, Al _x Ga _{1 -x} As (0.1 < x <
0.3), a λ / 4n reflective layer (here, λ is the wavelength of light) 23 is grown, and a λ / 4n reflective layer 22 made of undoped AlAs having a relatively low refractive index is formed. Let it grow. The two reflective layers 23 and 22 are 1
The lower reflective layer 30 composed of a λ / 4 reflective layer (QWRS) is formed by forming the reflective layer 30 in two or more cycles (preferably 14 times). At this time, the optical thickness of each layer is determined by the operating wavelength (the wavelength of the absorption peak of the exciton of SMQW).
To 1/4 of

As described above, the two λ / 4n reflection layers 23, 2
After the lower reflective layer 30 is formed by repeatedly growing 2 over 12 periods (preferably 14 periods),
On the lower reflective layer 30, a P ⁺ -type Al _x Ga _{1 -x} As
(0.1 < x < 0.3) to grow the anode contact layer 2
9 is formed.

Subsequently, undoped Al _x Ga _{1 -x} As (0.1 < x <
0.3) is grown to a predetermined thickness to form the first buffer layer 25.

Thereafter, an undoped Al _x Ga _{1 -x} As barrier layer (0.01 < x
< 0.04) 26 and undoped GaAs
A thin quantum well consisting of the well layer 27 is grown in multiple (preferably 36 periods) to form a thin multiple quantum well layer 31.
Is formed.

Subsequently, undoped Al _x Ga _{1 -x} As (0.1
< X < 0.3) is grown to form the second buffer layer 28.

Finally, a cathode contact layer 24 is formed on the second buffer layer 28 by growing N ⁺ type Al _x Ga _{1 -x} As (0.1 < x < 0.3).

As described above, when the present invention described through the preferred embodiments is used, an S-SEED having excellent bistable characteristics of light without an applied voltage, and a two-dimensional S-SEED can be used.
It is possible to manufacture an array, an application element using the array, a two-dimensional array thereof, and the like.

When a two-dimensional array is formed using the non-voltage optical bistable element according to the present invention, each element can be electrically separated, so that the yield of elements can be increased. A metal wire for applying an external voltage,
Since the space on the substrate for this is unnecessary, the degree of integration of the array can be greatly increased.

In addition, it is possible not only to reduce mutual induction between electric wires, mutual interference by an electromagnetic field, crosstalk phenomenon, etc., but also to easily realize a circuit for a high-speed switching element. Since there is no need to connect wires and connect wires for applying an external voltage in assembling a semiconductor component having the element of the present invention, the manufacturing process is simplified, and the economical effect that the unit cost of the process can be reduced. There is expected.

The bistable seed (NOBS) of the voltageless light of FIG. 19 according to the present invention, which has the bistable characteristic of light even without the application of an external voltage, is in a state where no externally applied voltage is applied. The voltage between V1 and V2 is NO in FIG.
As shown in the load curve of BS, it can be considered that the voltage Vop and -Vop of the stabilized operating point.

This means that when NOBS exhibits optical bistability, the electric field applied to each diode is (Vbi-Vo).
p) / ti and (Vbi + Vop) / ti (where ti
Is the total thickness of the intrinsic region).

Therefore, it is advantageous to reduce ti as much as possible in order to make the electric field difference between the two diodes have a large difference in the absence of an externally applied voltage. A where the input resistance of light is mismatched
Since the FP-SEED is configured such that the total thickness (D) of the light absorbing layer is smaller than that of the AFP-SEED having the matched light input resistance, ti can be further reduced. is there.

One example of the optical bistable characteristic of NOBS based on the above-mentioned principle of NOBS is shown in FIG. The difference between the AFP-NOBS with the matched resistance and the AFP-NOBS with the mismatched resistance can be reliably grasped. Since the off-state value of the AFP-NOBS whose resistance is matched is closer to zero than that of the AFP-NOBS whose resistance is not matched, the CR is surely large, but the width of ΔR and the bistable light (ΔP ) Has a relatively small value.

In particular, in the case of NOBS, the value of the reflectance in the ON state is very small when the resistance is matched, so that
Somewhat unsuitable for application in optical systems.

[0161]

Therefore, by designing the structure of the AFP-SEED using the concept of mismatch of the input resistance of light proposed by the present invention, it is possible to maintain an appropriate CR required from the optical system, It is possible to enable a NOBS having a ΔR and a bistable width (ΔP) of light necessary for application of an optical system.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a typical symmetric seed (S-SEED) device.

FIG. 2 is a top view of FIG. 1;

FIG. 3 is an equivalent circuit diagram of FIG. 1;

FIG. 4 is an equivalent circuit diagram of FIG. 1;

FIG. 5 is a graph showing a load curve of the circuit shown in FIG.

6 is a graph showing an optical bistable characteristic curve of the circuit shown in FIG. 4;

FIG. 7 is a graph showing a load curve when VAP = 0 in the circuit shown in FIG. 4;

FIG. 8 is an explanatory diagram showing an energy band in a state of thermal equilibrium of a conventional PIN diode SEED.

FIG. 9 is a graph showing a load curve in a case where the reverse voltage (VAP) is 0 in an S-SEED circuit including a thin quantum well structure SEED.

FIG. 10 shows a PIN having a thin quantum well structure.
FIG. 4 is an explanatory diagram showing an energy band of a type diode SEED in a state of thermal equilibrium.

FIG. 11 is an explanatory view showing a structure of a general reflection type SEED.

FIG. 12: Asymmetric Fabry bellow seed (AFP-
FIG. 3 is an explanatory diagram showing the structure of (SEED).

FIG. 13 is a graph showing the light absorption coefficient of the reflection type SEED at the wavelength of the exciton and the reflectance with respect to the square of the thickness of the light absorption layer.

FIG. 14 is a graph showing a change in light absorption coefficient with respect to a vertical electric field at a wavelength of an exciton in a multiple quantum well having nonlinear light absorption characteristics.

FIG. 15 shows the relationship between the ON / OFF intensity ratio of the light absorption coefficient of the AFP-SEED and the square of the thickness of the light absorption layer in the resistance bistable AFP-SEED and the resistance mismatched AFP-SEED in the light bistable characteristic of the AFP-SEED. Graph showing characteristics.

FIG. 16 is a graph showing the characteristics of the difference in ON / OFF reflectance in the light bistable characteristics of AFP-SEED with respect to the light absorption count and the square of the thickness of the light absorption layer.

FIG. 17 is a top view of a two-dimensional array of optical bistable elements made of the S-SEED of FIG. 2;

18 is an equivalent circuit diagram of FIG.

FIG. 19 is a circuit diagram of an S-SEED according to the present invention which shows bistable characteristics of light without an externally applied voltage.

FIG. 20 is a top view showing one example of a voltageless optical bistable element according to the present invention.

FIG. 21 is a top view showing another example of the non-voltage optical bistable element according to the present invention.

FIG. 22 shows a non-voltage optical bistable element 2 shown in FIG.
FIG. 3 is a top view of a three-dimensional array.

FIG. 23 shows a second example of the non-voltage optical bistable element shown in FIG.
FIG. 3 is a top view of a three-dimensional array.

FIG. 24 is an equivalent circuit diagram of a two-dimensional array of no-voltage optical bistable elements according to the present invention.

FIG. 25 is an explanatory view showing the structure of an SEED according to one embodiment of the present invention.

FIG. 26 is an explanatory view showing the structure of an SEED according to another embodiment of the present invention.

FIG. 27 is an explanatory view showing the structure of an SEED according to still another embodiment of the present invention.

FIG. 28 shows S-SEE enabling bistability of voltage-free light
The graph which shows the load curve of D.

FIG. 29: AFP-NOBS (Nonbiased
3 is a graph showing one example of optical bistability characteristics of AFP-NOBS with mismatched resistance according to the present invention and Optical Bistable S-SEED).

[Explanation of symbols]

1 ... n-contact layer, 2 ... p-contact layer, 3 ... insulating layer, 4 ... metal wiring, 5 ... metal pad, 6 ... light input / output window.

Claims (12)

(57) [Claims] 1. SEED (Self Electro-optic Effectiv)
e device) optical logic element, comprising: a semi-insulating GaAs substrate; and a predetermined refractive index (n) grown on the substrate to a predetermined thickness.
And a second reflective layer grown to a predetermined thickness on the first reflective layer and having a refractive index different from the refractive index of the first reflective layer, At least 12
A lower reflective layer formed repeatedly over a period; a first electrode contact layer grown to a predetermined thickness on the lower reflective layer; a first buffer layer grown on the first electrode contact layer A thin multi-quantum well layer in which a barrier layer and a thin quantum well layer are grown at a predetermined period on the first buffer layer; and a second buffer layer grown on the thin multi-quantum well layer. And a second electrode contact layer grown on the second buffer layer. 2. The non-voltage optical bistable logic device according to claim 1, wherein the thin multi-quantum well layer has a barrier layer and a thin quantum well layer grown in 36 periods. . 3. The non-voltage light bistable logic device according to claim 2, wherein the refractive index of the first reflective layer is relatively smaller than the refractive index of the second reflective layer. 4. The device according to claim 2, wherein the refractive index of the first reflective layer is relatively greater than the refractive index of the second reflective layer. 5. The structure according to claim 1, wherein the contact layer of the first electrode is a P ⁺ anode contact layer, and the second electrode contact layer is a N ⁺ cathode contact layer. Voltage optical bistable logic element. 6. The non-voltage contact of claim 1, wherein the first electrode contact layer is a N ⁺ cathode contact layer, and the second electrode contact layer is a P ⁺ anode contact layer. Optical bistable logic element. 7. The first reflection layer is made of undoped AlAs, and the second reflection layer is made of undoped Al _x Ga.
_2. The non-voltage optical bistable logic element according to claim 1, wherein the element consists of _lx As (0.1 < x < 0.3). 8. SEED (Self Electro-optic Effectiv)
In the method of manufacturing an optical logic device of (e Device), a first λ / 4n reflection layer (here, λ is a wavelength of light) of AlAs having a predetermined refractive index (n) is formed on a semi-insulating GaAs substrate. ) is grown to a thickness of about 72.1nm a, Al has a relatively high refractive index _x Ga _lx As (0.1
< X < 0.3), the second λ / 4n reflection layer is made up of 60.7
forming a lower reflection layer by growing the first λ / 4n reflection layer and the second λ / 4n reflection layer in at least 12 periods, and forming the lower reflection layer on the lower reflection layer. N ⁺ type Al _{x Gal x} As (0.
Forming a cathode contact layer by growing 1 < x < 0.3) to a thickness of about 500 nm; and forming undoped Al on the cathode contact layer.
forming a first buffer layer _x Ga _lx As the (0.1 <x <0.3) is grown to a thickness of about 20 nm, on the first buffer layer, thickness of about 6nm as a barrier layer Al _{x Gal x} As (0.1 < x < 0.4) layer and undoped Ga having a thickness of about 10 nm as a well layer.
As layers are sequentially grown, and the barrier layers and the well layers are grown for 36 periods to form a thin multi-quantum well layer (SMQ).
W); and forming Al _{x Gal x} As (0.1 < x) on the thin multi-quantum well layer, which is not doped to a thickness of about 20 nm.
Forming a second buffer layer by growing < 0.3); and forming P ⁺ on the second buffer layer to a thickness of about 506.7 nm.
Growing an Al _{x Gal x} As (0.1 <x <0.3) type to form an anode contact layer. 9. A quantum well comprising an n-contact layer, a p-contact layer, and first and second PIN diodes each having a light input / output window and having a quantum well region as an intrinsic layer. An optical bistable logic element in which light absorption from a well region is changed by a photocurrent generated from the PIN diode, wherein the contact layer of the first PIN diode and the second PI
A voltageless optical bistable logic element directly connected to the contact layer of an N diode. 10. The n-contact layer, light input / output window and p-contact layer of the first PIN diode, and the n-contact layer, light input / output window and p-contact layer of the second PIN diode,
When the logic elements are viewed from above, they are arranged in a straight line in the horizontal direction in the order described above, and the first P
The n-contact layer of the IN diode and the p-contact layer of the second PIN diode, and the p-contact layer of the first PIN diode and the n-contact layer of the second PIN diode are connected to each other by a metal wiring. The non-voltage optical bistable logic element according to claim 9. 11. The first PIN diode and the second PIN diode
The p-contact layer of the second PIN diode is arranged in parallel with the PIN diode, but at a predetermined distance on the right side immediately adjacent to the n-contact layer of the first PIN diode. The light input / output windows of the first and second PIN diodes are located on the same straight line to facilitate processing of parallel optical signals, and the p-
The second PI is provided at the predetermined distance immediately next to the contact layer.
An n-contact layer of an N-diode is located, and an n-contact layer of the first PIN diode and the second PI
10. The non-voltage non-voltage layer according to claim 9, wherein the p-contact layer of the N diode, the p-contact layer of the first PIN diode, and the n-contact layer of the second PIN diode are respectively connected by metal wiring. Optical bistable logic element. 12. A multiple quantum well (MQ) as an intrinsic region.
W) and an upper reflecting layer and a lower reflecting layer having mutually different reflectivities with respect to the resonance wavelength of the exciton of the multiple quantum well, wherein the resonator length is the same as the resonance wavelength of the exciton. Multiplexing of an asymmetric Fabry-Perot optical bistable logic element (AFP-SEED) having a matched input resistance of light in a Fabry-Perot (AFP) optical bistable logic element By having multiple quantum wells with a period number relatively smaller than the period number of the quantum well (MQW), the light input resistance of the structure in which the total thickness (D) of the light absorbing layer is reduced is reduced. Unmatched voltageless optical bistable logic element.