JPH07209681A - Logic element displaying bistability of light without applied voltage from outside and its manufacture - Google Patents

Abstract

PURPOSE: To improve bi-stability of light in SEED where the bi-stable characteristic of light is obtained with improvement without external voltage. CONSTITUTION: The thickness of an intrinsic area is reduced by appropriately reducing the frequency of a multiplex quantum well 31. Thus, SEED of an asymmetrical Fabry rot structure where resistance for considerably increasing the difference (ΔR) of a reflection factor between on/off states and the bi-stable width (ΔP) of light does not match while the appropriate on/off intensity ratio is maintained which is required from an optical system can be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical bistable logic element.
The present invention relates to a symmetrical seed (Symmetric Self Electro-optic Effect Device; hereinafter referred to as “S-SEED”) which is an (optical bistable logic device) and a manufacturing method thereof. More specifically, the bistability characteristic of light (o
Non-biased symmetric bi-stable seeds of non-voltage light that exhibit optical bistable characteristics without the application of external voltage to achieve vertical bistability and can perform the functions of optical logic circuits. Bistable S-SEED: Below, 'N
OBS ') and its manufacturing method.

[0002]

2. Description of the Related Art The bistable characteristic of light is a fundamental concept that is the basis for realizing future-oriented parallel light signal processing, light conversion, and optical computer. Several devices are known that can implement this.

Among these, as a typical optical bistable logic element, a structure of multiple quantum well (intrinsic region) (multiple quantum well;
Symmetrical seed (S-SEE) in which two PIN diode seeds with "MQW" are connected in series.
D) can be raised.

Such an S-SEED structure is described by David A.
Disclosed by B. Miller (USP 4,546,2
44).

S-with a multiple quantum well (MQW) structure
In SEED, photocurrent is generated by the light absorbed from within the MQW, and the voltage due to this photocurrent is applied to the MQW again, so that the light absorption characteristics of the MQW are affected.

Such an S-SEED has a relatively small switching energy, and an array of two-dimensional elements that facilitates parallel light signal processing by utilizing the existing compound semiconductor manufacturing process. Has the advantage that it can be easily realized.

FIG. 1 shows a sectional view of a conventional S-SEED, and FIGS. 2 and 3 are a plan view and an equivalent circuit diagram of FIG.

In FIG. 2, the same parts as in FIG. 1 are indicated by the same reference numerals.

In FIG. 2, 7 is the PIN diode mess.
a) The boundary of the etched portion, and 8 indicates the boundary of the etched portion for electrical isolation between the elements.

As shown in FIG. 3, a conventional S-SEED is used.
Are two identical PIN diodes SEED (D1, D
2) has a structure in which they are connected in series with each other.

In addition, a reverse voltage (VAP) is applied to this S-SEED, and each SEED changes to another S-SEED.
They act as a load on the EED, and have the characteristic of optical bistable. A reverse voltage (VAP) is applied to the metal pad 5 shown in FIGS.

In FIG. 1, reference numerals 1 and 2 respectively indicate an n-contact layer and a p-contact layer for ohmic contact.

The n-contact layer 1 and the p-contact layer 2 between the two PIN diodes are interconnected by a metal wire 4. The remaining n-contact layer and p-contact layer are formed by the metal layer 4 formed by the same process.
An external power source (not shown) is connected to the device through the metal pad 5. The two PIN diodes consist of an undoped quarter-wavelength reflector stac on a semi-insulating substrate.
They are electrically isolated from each other by etching up to k).

On the structure thus formed, Si
An insulating layer 3 made of N _x or SiO ₂ is vapor-deposited to prevent electrical crosstalk and surface oxidation.

The light source is an optical input / output window 6
Through a PIN diode.

A method of manufacturing such an S-SEED will be described below with reference to FIGS. 1 and 2.

A) Mesa wet etching up to the n-layer, each PIN
The diode 7 is formed.

B) Etch up to the undoped quarter-wave reflective layer for electrical isolation of each PIN diode.

C) Deposit n-contact layer 1 for ohmic contact of the n-layer.

D) Deposit an insulating layer 3 for preventing electrical crosstalk, surface oxidation and the like.

E) Open the light input / output window 6 and etch the insulating layer 3 of the n-contact layer 1 and the p-contact layer (see 2) for metal-to-metal connection.

F) Deposit p-contact layer 2 for ohmic contact of the p-layer.

G) Evaporating a wiring metal 4 for electrical wiring.

H) Deposit thick metal pads 5 for wire bonding.

As described above, when two identical PIN type diode SEED modulators are connected in series to each other and a reverse voltage VAP is applied, the respective SEED modulators are applied.
Acts as a load on other SEEDs.

At this time, the reverse voltage (VA) of SEED
The characteristic of the photocurrent with respect to P) is the multiple quantum well (MQW)
Since it has a non-linear characteristic due to the non-linear change of the optical absorption coefficient, the voltage applied to each diode does not become VAP / 2 as in a general linear circuit.

FIG. 17 shows a 4 × 8 two-dimensional array using general S-SEED.

Even if the two-dimensional array becomes large, it is possible to have a similar composition.

As shown in FIG. 17, in the general two-dimensional S-SEED array, since a reverse voltage must be applied to each S-SEED, a metal wire is formed between S-SEED. Must be located and requires metal pads for wire bonding.

An equivalent circuit of such a two-dimensional array is shown in FIG. All S-SEEDs are electrically connected.

In such a composition, one S-S
When an electrical short circuit occurs even in EED, the desired reverse voltage cannot be applied between both electrodes.
You cannot use the entire array.

Further, if the number of arrays in fabrication becomes large, the risk that the metal wire for contacting the p-layer and the metal wire for contacting the n-layer increase with each other.

The S-SEED having such a structure is shown in FIG.
As shown in Fig.2, when manufacturing with a two-dimensional array,
A metal wire for applying a reverse voltage, a metal wire for connecting elements, and a metal pad for wire bonding must be included, and an electric wire to an external power source is required when the circuit is constructed.

The arrangement of the electric wires on the substrate and the external electric wires cause mutual induction between the electric wires, mutual interference due to an electromagnetic field, and crosstalk.

In particular, when forming an S-SEED array, the cathode of each S-SEED connected to the power source is
All must be tied to one (as well as the anode tied to the power supply). Each S-SE
The ED will not be able to be electrically isolated.

Therefore, S-SEE forming a two-dimensional array
When the number of D is increased, the above problems become more serious, the yield of the device is significantly reduced, and the integration degree thereof is also reduced.

Further, since the metal wiring and the electric wire act as parasitic passive element components when forming the SEED and S-SEED circuits, they have a disadvantage in high speed switching.

SS which requires a general reverse voltage
The above-mentioned problem that the EED and S-SEED arrays have is solved if it is an element that exhibits the characteristics of optical bistable even if no voltage is applied from the outside and can function as an optical logic circuit. can do.

FIG. 5 shows a load curve of the photocurrent Ip of a general S-SEED circuit.

In FIG. 5, the voltage V is the voltage applied to the first diode (D1) shown in FIG. The solid curve and the dotted curve are the diode D1 with respect to the voltage (V).
And the load curve of D2 are shown, respectively.

At the operating point A, the diode D1 has V≈
A voltage of 0 is applied, and VAP-V≈ is applied to the diode D2.
The voltage of VAP is applied.

On the other hand, in the case of the operating point B, D≈V≈V
The voltage of AP is applied, and VAP-V is applied to the diode D2.
A voltage of ≈ 0 is applied. That is, the S-SEED circuit
Two PIN diodes having the same structure are connected in series, but different voltages are stably applied to each SEED.

Therefore, different electric fields are applied to the MQWs located in the intrinsic region of each element forming the S-SEED, whereby the absorptance of light of each element is different. The absorptance of different light is the reflectance of each SEED (transmission type S
In case of EED, the transmittance is different. Since the S-SEED circuit has a positive feedback characteristic due to the characteristic of the non-linear photocurrent generated by the absorbed light, the S-SEED circuit has a positive feedback characteristic.
The SEED circuit can have the optical bistability which is a requirement of the optical logic device as shown in FIG.

In FIG. 6, R represents the reflectance of the light of SEED, Pin is the intensity of the input light input to SEED, and ΔP is the stable width of the light from S-SEED. , Ron is the reflectance in the ON state, Ro
ff is the reflectance in the off state, and ΔR is
The difference in light reflectance (Ron-Roff) is shown.

A general SEED is a quantum binding effect (Quant
um Confined Stark Effect; hereinafter referred to as “QCSE”).

Here, QCSE is the absorption peak of heavy hole exciton absorption of MQW.
peak) is changed to red by the application of an electric field to reduce the absorption rate of light from the fixed operating wavelength of MQW in a non-linear manner, thereby changing the photocurrent and reflectance of the device in a non-linear manner. The optical ON / OFF state can be changed.

The non-linear characteristic of the MQW enables the SEED to be used as an optical logic element according to the principle of the S-SEED circuit described above.

FIG. 7 shows such a quantum binding effect (QCS).
S-SEE configured by SEED using E)
From the D circuit, S when the external applied voltage VAP = 0
-Shows the load curve of the SEED circuit.

As shown in FIG. 7, when VAP = 0, the intersection of the two curves, that is, the operating point of S-SEED,
It is one of the places of C. Therefore, in each SEED constituting the S-SEED, the voltage of constant V = 0 is constantly applied to the two diodes even if the photocurrent caused by the incident light is induced, and all of the two diodes are shown in FIG. As shown, the energy band in thermal equilibrium is maintained.

Therefore, only the electric field due to the internal voltage VBI generated by the PIN diode is applied to the MQW forming the intrinsic region of each SEED, and the electric field is 2
Since the two diodes are the same as each other, when VAP = 0, it is impossible to have optical bistable.

This is SEE using general QCSE
ΔEC which is the difference between the energy of the conduction band of the barrier layer and the energy of the conduction band of the well layer in D is large, and
This is because the total thickness d of MQW in the intrinsic region is large, so that the electric field due to the internal voltage distributed in the intrinsic region is small (in FIG. 8, EC indicates the energy of the conduction band and EV indicates the valence band). , EF is the energy of Fermi respectively).

Such an electric field is not sufficient for the electron-hole pairs generated in the quantum well by light absorption to pass through the barrier layer and be separated into the anode layer and the cathode layer. Even if the rate decreases due to the increase of the electric field, the point D, which is the maximum value of the photocurrent, is applied to the voltage in the opposite direction (from the right side of FIG. 7,
That is, when VAP = 0 obtained from the first upper limit), a stable operating point of the characteristic of the nonlinear photocurrent is not allowed except for the point C.

FIG. 9 shows the load curve of the S-SEED circuit when the intrinsic region of the SEED structure is formed by the structure of thin multiple quantum wells (Shallow MQW; hereinafter referred to as'SMQW ').

In FIG. 9, VE represents the voltage applied to the diode D1 when the operating point of the S-SEED circuit composed of thin quantum wells (SMQW) when VAP = 0 is E. VF represents the voltage applied to the diode D1 when the operating point of the S-SEED circuit composed of MQW when VAP = 0 is F.

FIG. 10 shows S- having the same load characteristics as FIG.
7 illustrates the energy band of the SEED circuit in thermal equilibrium.

Unlike FIG. 7, FIG. 9 has stable operating points E and F even when VAP = 0. this is,
This means that different voltages can be applied to the two SEED elements forming the S-SEED. This creates a light bistable even when VAP = 0.

As can be seen from FIG. 10, this is SMQW.
This is because the difference in energy between the conduction band of the well layer and the barrier layer is very small at 30 meV or less at room temperature, so that low voltage absorption is not performed. That is, S of SMQW structure
The EED has a flat band (electric field = electric field), which is ionized by an electric field only by an internal voltage generated by a PIN diode.
0) or only in the presence of a very small electric field, the bindable exciton level is removed, greatly reducing the optical absorption from the operating wavelength.

Therefore, the maximum value of the photocurrent (point G) is
When a positive voltage is applied to the PIN diode to some extent and only a very small electric field exists in the symmetrical SMQW (ie, excitons can be bound and generated while maintaining high optical absorption). Electron-hole pairs can be easily separated into the anode and the cathode to generate a large amount of positive photocurrent). Therefore, SEED using SMQW can maintain the bistability of light even when VAP = 0.

As described above, the self-biased S-SEED that is operated without applying an external voltage is different from each S-SEED when forming an array, unlike the case where an existing external voltage is required. Since they can be designed to be electrically independent, high density integration is possible and the yield can be increased.

In addition, such S-SEED has electrical connection such as a pad for wiring connection for applying an external voltage, a long metal wire from the array to the pad, and an electric wire from the array to the power supply source. Since it is not necessary, there is no mutual induction effect between electric wires, mutual interference and crosstalk due to electromagnetic fields can be prevented, and special element design for high-speed switching is not particularly required. You can

However, even in the SEED using the SMQW structure as described above, in order to absorb a large amount of the positive light, the MQW structure forming the intrinsic region is formed like the SEED using the general QCSE. All thickness d is 1 μm
It is necessary to make it large. The structure of the PIN diode SEED made of AlGaAs / GaAs, which is the most widely used, will be described as an example.

VB1≈1.5 Volts, the operating point in FIG. 9 is E
, The voltage applied to the diode D1 is VE =
Assuming that 0.9 Volts and d = 1.0 μm, VBI-VE = 0.6 Volts is respectively applied to the diodes D1 and D2.
And an electric field of 6.0 due to a voltage of VB1 + VE = 2.4 Volts
X 103 V / cm and 2.4 x 104 V / cm are formed, respectively.

The electric field difference of this degree is from VAP = 0 to S.
It is a value that can measure the bistability of light from the MQW structure S-SEED, but since the magnitude is not sufficient, the difference in reflectance ΔR = Ron-Roff is small, which makes it practically applicable in optical systems. It is thin.

As described above, a thin multiquantum well (SMQW) is used as a self-biased S-SEED that can maintain optical bistability even when an external voltage is not applied. A structure and a structure using an asymmetric quantum well are known.

An existing PIN type diode SEED structure using these is not much different from a general SEED structure using the quantum constraint effect (QCSE). That is, in order to absorb a lot of positive light, it was necessary to increase the total thickness of the multiple quantum wells (MQW) forming the intrinsic region.

Therefore, the self-biased S-SEE
Since the internal electric field due to the internal voltage of the PIN diode that enables D is small, the change in the reflectance for the optical bistable and the width of the optical bistable is not suitable for practical optical systems. There was a flaw that was not enough.

As a symmetric bi-stable seed (NOBS) of light without voltage capable of achieving light bistability without applying an existing external voltage, an MQW thin quantum well (Extremely Shallow Quantum Well: Below, "ESQ
W ”, asymmetric quantum well (Asymmetric Coupled)
Quantum Well: hereinafter referred to as "ACQW"), strained MQW (Strained MQW: hereinafter referred to as "SMQW")
, Asymmetric Fabry-Perot (asymmetr
ic Fabry-Perot) resonance structure and thin multiple quantum well (E
SQS) coupled S-SEED, and asymmetric Fabry-Perot resonance structure and asymmetric quantum well (asymmetr)
ic coupled quantum well (hereinafter referred to as "ACQW") is known as an S-SEED.

However, when these are applied to the existing general reflection-type SEED structure, that is, the total thickness of the MQW forming the intrinsic region is 1 because of the large amount of positive light absorption.
If it is increased to about μm, the bistable characteristic of voltageless light is very small. This is NO
The intrinsic electric field due to the intrinsic voltage of the PIN diode that enables the BS is SE with a typical intrinsic region thickness of 1 μm.
This is because the ED structure is small.

As a method presented in order to solve such a problem of NOBS, and in particular to increase the ON / OFF intensity ratio (ON / OFF Contrast Ratio: hereinafter, referred to as “CR”), a light input is used. There has also been proposed that utilizes the resonance structure of AFP with matched resistance. This is because when the MQW light absorption degree is taken into consideration, it is common to reduce the total thickness of the quantum wells for light absorption necessary to form the AFP resonance structure in which the light input resistances are matched. This is because the internal electric field with respect to the internal voltage set by such a structure can be significantly increased.

However, the off-state reflectance is set to zero (zer
When using AFPs whose light input resistances are matched to each other, the CR is very large (theoretically infinite), but the reflectance in the ON state and the reflectance in the OFF state are different from each other. There is a disadvantage that the difference (ΔR) and the width of the bistable light (ΔP) are relatively small.

FIG. 11 shows the well-known reflection type SE.
An example of an ED structure is shown.

In this structure, the optical thickness of the substrate 11 is small, and the optical thickness of the first λ / 4n reflecting layer 12 is large, which has a large refractive index such that the operating wavelength of the excitons of the MQW is 1/4. A second λ / 4n reflective layer 13 having a refractive index and a lower reflective layer which is periodically grown are provided, and a PIN diode having MQW as an intrinsic region is formed thereon. Generally, the uppermost layer is subjected to antireflection treatment to increase the light absorption efficiency of the device. In forming the PIN diode, the layer 14 is an n-layer and the layer 18 is a p-layer.
Layer 14 may be formed as a p-layer, and layer 14 may be formed as an n-layer.

The p-layer, the n-layer, the barrier layer, the buffer layer, and the reflective layer excluding the quantum well layer must all be materials that do not absorb light at the operating wavelength.

On the other hand, as shown in FIG. 12, the QWL is laminated on the upper portion to form the upper reflecting layer, and the thickness (L) from the lower reflecting layer to the upper reflecting layer is determined by setting the optical distance to the operating wavelength of 1 / 4
When adjusted so as to be a constant multiple of, an AFP structure is formed in which the resonant wavelength of the excitons and the AFP mode are matched. At this time, it is possible to obtain an AFP structure in which the reflectance (Rf) of the upper reflection by the air / semiconductor interface is 0.32 without stacking the QWL for the upper reflection layer.

FIG. 13 shows the above-mentioned reflective SEED MQ.
One example of the reflectance by the square of the light absorption coefficient (α) of W and the total thickness (D) of the light absorbing layer is shown, and a general reflection in which an antireflection layer is filled is shown. Shape SEED
Structure, the reflectance (Rf) of the upper reflection is 0.3, respectively.
It relates to the structure of AFP-SEED which is 2, 0.5.

In FIG. 13, A1 and A2 are Rf =
The value of αD that satisfies the condition of matching the optical input resistances of AFP-SEED of 0.32 and AFP-SEED of Rf = 0.5 is displayed.

Since the absorption coefficient (α) of light of MQW is determined by the structure of MQW, it generally decreases as the electric field increases from the resonant wavelength of excitons of MQW, as shown in FIG. .

Therefore, the decrease of α due to the increase of the electric field satisfies the condition that the reflectivity (R) increases as shown in FIG. 13 and is normally off, that is, the reflectivity increases as the electric field increases. As a result, it comes to have the bistable characteristic of light.

Such a normal-off condition is AFP-
In the case of SEED, it is possible from the area on the left side of the fulcrums A1 and A2 that satisfy the agreement of the input resistance of light from FIG.

As one example thereof, SEED filled with an antireflection layer and αoff (α in the off state) of AFP-SEED with Rf = 3.2 and the reflectance of the on state and the off state with respect to the square of D FIGS. 15 and 16 show the ratio (or on / off intensity ratio) (CR) and the difference (ΔR) in consideration of the case where the value of αon / αoff is 0.35.

From FIG. 15 and FIG. 16, point A1 is AFP-SEED where the resistances match, and point B1 is AF where the resistances do not match.
P-SEED is shown respectively.

From the point A1 in AFP-SEED which satisfies the condition that the light input resistances are matched, the CR value is very large as seen from FIG. 15, but the ΔR value in FIG. 16 is as small as 0.2 or less. It becomes a value.

On the other hand, the value of the on / off intensity ratio (CR) is 1 from the point B1 which satisfies the condition of the mismatch of the light input resistances.
If a sufficient value is maintained at about 0, the reflectance difference (ΔR) value can be maintained at about 0.3. Especially NOB
In S, since the value of α is changed only by the internal voltage without an externally applied voltage, the value of αon / αoff becomes smaller than 0.35, so the value of ΔR becomes relatively small, and CR It is more necessary to maintain the required minimum value and maximize the value of ΔR.

When the light input resistances are not matched with each other, A
FP-SEED is a phase-matching
ng), that is, the mode of AFP and the resonant wavelength of excitons are matched. The thickness of L satisfying the conditions can be maintained, and the number of periods of MQW can be reduced to be easily realized.

[0085]

SUMMARY OF THE INVENTION The present invention eliminates the problems associated with optical logic devices that require reverse voltage by significantly increasing the bistability of light without the application of an external voltage. At the same time, its main purpose is to provide a self-biased S-SEED optical logic element that can be put to practical use in an optical system.

Another object of the present invention is to increase the bistability of light significantly without applying an external voltage, and thereby to solve the problems of general optical logic elements which require reverse voltage. An asymmetric Fabry-Perot thin quantum well seed (AFPESQWS-SEED) or an asymmetric Fabry-Perot asymmetric quantum well seed (AFPACQWS-SEED) that can be eliminated. Is to provide a device layout (lay-out) capable of being manufactured simply and efficiently.

Still another object of the present invention is to provide a structure for simplifying the electrical connection between the respective diodes of the optical bistable logic element and increasing the degree of integration of the element.

Still another object of the present invention is to enable the electrical isolation of voltageless light bistable logic elements that operate without the application of an external voltage so that in the overall two-dimensional array. Even if a defect occurs in a part, the remaining S-SEED element is not affected, and a two-dimensional array of NOBS (Nonbiased Optical Bistable S-SE) irrelevant to the part of the defect.
ED) structure.

Still another object of the present invention is to appropriately maintain CR in the production of NOBS utilizing the structure of AFP resonance which can significantly increase the bistable characteristics of light without applying an external voltage. A structure for maximizing ΔR and Δ is provided.

[0090]

According to the first aspect of the present invention to achieve the above object, SEED (Selr Electr
In the optical element of (o-optic Effective Device),
A semi-insulating GaAs substrate, a first reflective layer grown to a predetermined thickness on the substrate and having a predetermined refractive index (n), and grown to a predetermined thickness on the first reflective layer, A lower reflective layer having a second reflective layer having a refractive index different from that of the first reflective layer, the lower reflective layer being repeatedly formed for at least 12 cycles, and a predetermined reflective layer on the lower reflective layer. A first electrode contact layer grown to a thickness, a first buffer layer grown on the first electrode contact layer, a barrier layer and a thin quantum well layer on the first buffer layer in a predetermined cycle. A thin multi-quantum well layer to be grown, a second buffer layer grown on the thin multi-quantum well layer, and a second buffer layer grown on the second buffer layer.
A voltageless light bistable logic element including an electrode contact layer is provided.

The thin multi-quantum well layer may be formed by growing a barrier layer and a thin quantum well layer in 36 periods.

The refractive index of the first reflective layer can be made relatively smaller than that of the second reflective layer.

Further, the refractive index of the first reflective layer can be made relatively higher than that of the second reflective layer.

The contact layer of the first electrode may be a P ⁺ anode contact layer, and the second electrode contact layer may be an N ⁺ cathode contact layer.

The first electrode contact layer may be an N ⁺ cathode contact layer, and the second electrode contact layer may be a P ⁺ anode contact layer.

The first reflective layer is made of undoped AlAs, and the second reflective layer is made of undoped Al _{x Gal x} As (0.1 < x < 0.3). be able to.

In order to achieve the above object, the present invention
According to the second aspect of SEED (Self Electro-optic
Effective Device) method of manufacturing optical logic elements
A semi-insulating GaAs substrate with a predetermined refractive index
The first λ / 4n reflective layer (this
Here, λ is the wavelength of light) and is grown to a thickness of about 72.1 nm.
Al having a relatively high refractive index_xGa_lxA
s (0.1<x<0.3) second λ / 4n reflective layer
Is grown to a thickness of about 60.7 nm, and the first λ / 4
The n reflection layer and the second λ / 4n reflection layer have 12 periods or more.
Forming a lower reflective layer by forming
On the lower reflective layer, N⁺Type of Al_xGa_lxAs (0.1
<x<0.3) to a thickness of about 500 nm and
Forming a sword contact layer on the cathode contact layer
Undoped Al_xGa_lxAs (0.1
<x<0.3) is grown to a thickness of about 20 nm and the first
Forming a buffer layer, and a barrier layer on the first buffer layer
With a thickness of about 6 nm_xGa_lxAs (0.1<
x<0.4) layer and well layer with a thickness of about 10 nm
Ungrown GaAs layers are grown sequentially and
The barrier layer and the well layer are grown for 36 periods to be thin.
Forming a multi-quantum well layer (SMQW);
On the thin multi-quantum well layer, the thickness is about 20 nm.
Unpinged Al_xGa_lxAs (0.1<x<
0.3) to form a second buffer layer, and
On the second buffer layer, a P layer having a thickness of about 506.7 nm is formed.⁺Type
Al_xGa_lxGrow As (0.1 <x <0.3)
Forming an anode contact layer with
A method of making an optical bistable logic device is provided.

Further, in order to achieve the above object, according to the third aspect of the present invention, there is provided a structure in which the logic elements of the first aspect are two-dimensionally arranged.

In order to achieve the above object, according to the fourth aspect of the present invention, an n-contact layer, a p-contact layer, and a quantum well region each having an input / output window for light are provided as an intrinsic layer. In the optical bistable logic element, the first and second PIN diodes are connected in series, and the light absorption from the quantum well region is changed by the photocurrent generated from the PIN diode. A voltageless light bistable logic element is provided that directly connects the contact layer of the diode and the contact layer of the second PIN diode.

An n-contact layer of the first PIN diode,
The light input / output window, the p-contact layer, the n-contact layer of the second PIN diode, the light input / output window, and the p-contact layer are in the order described above when the logic element is viewed from above. The first PINs are arranged in a straight line in the horizontal direction.
The n-contact layer of the diode and the p-contact layer of the second PIN diode, and the p-contact layer of the first PIN diode and the n-contact layer of the second PIN diode may be connected by metal wiring.

The first PIN diode and the second PI
Although it is arranged in parallel with the N diode,
The p-contact layer of the second PIN diode is located at a predetermined distance on the right side of the n-contact layer of the IN diode, and the light input / output windows of the first and second PIN diodes are parallel to each other. The n-contact layer of the second PIN diode is located on the same straight line for facilitating the processing of the optical signal of the second PIN diode, and is located at a predetermined distance from the p-contact layer of the first PIN diode. And the n-contact layer of the first PIN diode and the second PIN diode.
The p-contact layer of the PIN diode, the p-contact layer of the first PIN diode and the n-contact layer of the second PIN diode may be connected to each other by metal wiring.

In order to achieve the above object, according to the fifth aspect of the present invention, a multiple quantum well (MQ) is used as an intrinsic region.
W) and an upper reflecting layer and a lower reflecting layer having reflectances different from each other with respect to the resonant wavelength of the excitons of the multiple quantum well, and the resonator length is asymmetrical with the resonant wavelength of the excitons. Bistable logic element (SEED) having a Fabry-Perot (AFP) structure, the asymmetric Fabry-Perot optical bistable logic element (AFP-SEED) having multiple input resistances is matched. Quantum well (MQ
By having multiple quantum wells with a period number relatively smaller than that of W), the total thickness (D) of the light absorption layer is
A voltage-free optical bistable logic element having a mismatched resistance of the optical input is provided.

[0103]

FIG. 19 is a circuit diagram of a seed element (NOBS) showing bistable light without applying an external voltage according to the present invention.

The manufacturing process of NOBS according to the present invention is almost the same as the general S-SEED, but the S-SEED of the present invention is used.
SEED is a bistable element of no voltage light (Nobiased Optic
al Bistable devics), so the conventional circuit (Fig. 3)
No external applied voltage is required. Therefore, unlike FIGS. 1 and 2, the metal pad 5 is not required.

20 and 21 are plan views showing the structure of a bistable seed of voltageless light having a structure according to the present invention. FIG. 20 shows the composition of an array in which the same diodes D1 and D2 as in a general S-SEED structure are arranged in parallel, and FIG. 21 differs from the general PIN diode array in that each diode is opposite. The composition is arranged in the direction of.

20 and 21, the same or corresponding components as those shown in FIGS. 1 and 2 are indicated by the same reference numerals as those in FIGS. 1 and 2.

Referring to FIG. 21, D1 on the left side of the drawing
Has an n-layer on the upper side and a p-layer on the lower side.
Has a p-layer on the upper side and an n-layer on the lower side.
The layer and the n-layer are located so as to be easily connected to the n-layer and the p-layer of D2, respectively.

On the contrary, the p layer is located on the upper side of D1 on the left side, the n layer is located on the lower side, the n layer is located on the upper side of D2 on the right side, and the p layer is located on the lower side.
It is also possible to position the layers. At this time, the windows 6 (optical windows) of the respective diodes must be horizontally aligned in order to easily perform parallel optical signal processing.

With such an arrangement, the wet-etched portion 8 for electrical separation up to the lower reflection layer shown in FIG. 1 is not located on the horizontal line. In this way, the length of the metal 4 for connecting the diodes D1 and D2 and the area forming S-SEED can be minimized.

22 and 23 show NO presented by the present invention.
The figure shows an example of a configuration in which BSs are two-dimensionally arranged.

22 shows a configuration in which the NOBSs of FIG. 20 are two-dimensionally arranged, and FIG. 23 shows FIG.
This is a configuration in which the NOBSs of 2 are arranged two-dimensionally.

As can be seen from the equivalent circuit of FIG. 24, unlike the conventional technique (FIGS. 17 and 18), it can be seen that the NOBSs are electrically completely separated from each other.

Therefore, NOBS forming a two-dimensional array
Even if a short-circuited NOBS occurs, it has no effect on other NOBSs that form a two-dimensional array together.

Therefore, when an apparatus for performing parallel optical signal processing is constructed by using the NOBS configuration presented by the present invention, an optical signal processing apparatus complementary to some defects is constructed. It is possible.

The two-dimensional array according to the NOBS composition proposed by the present invention is a general S-SEED array (see FIG. 1).
Unlike 7), since a metal wire for applying an external voltage between elements is not required, the integration degree can be increased and the metal wire between elements can be minimized. This can reduce parasitic passive elements (resistance, inductance, capacitance) induced on the semiconductor substrate. This can be further reduced particularly by using the composition of the example of FIG.

As described above, according to the present invention, an AFP having a large light bistability without an applied voltage.
ESQW S-SEED, AFP ACQW S-S
It becomes possible to easily manufacture an EED or a two-dimensional array thereof and a mixed-type applied optical element and array using the same.

When the configuration of the bistable logic element of voltageless light according to the present invention is used, each element can be electrically separated when forming a two-dimensional array, thus increasing the yield of the element. 2 that is irrelevant to some defects
Since there is no need for a metal wiring for applying an external voltage and a space on the substrate for this purpose, there is an advantage that the degree of integration can be significantly increased.

Further, not only the mutual induction action between the electric wires, the mutual interference due to the electromagnetic field and the phenomenon of the crosstalk between the elements can be reduced, but also the circuit for the high speed switching element can be easily realized.

Also, when assembling a semiconductor component using the logic element of the present invention, it is not necessary to connect wires for wire bonding and external voltage application, so the process is simplified and the unit cost of the process is reduced. The economic effect of being able to do so is also expected.

FIG. 25 shows a bistable seed (N
SMQW-AS according to the present invention for implementing OBS)
It is sectional drawing which shows the desirable example of FP-SEED structure.

First, on the semi-insulating GaAs substrate 21, a first λ / 4n reflection layer (Quarter Wavelength Reflect) made of AlAs having a relatively low refractive index (n = 2.98) is formed.
or Stack) (where λ is the wavelength of light) 22 7n
A relatively high refractive index (n = 3.
Second λ / 4n consisting of Al _0.1 Ga _0.9 As with
The reflective layer 23 is grown to a thickness of about 60.7 nm, and the first λ / 4n reflective layer 22 and the second λ / 4n reflective layer 23 are grown.
By forming the λ / 4n reflective layer (quarter wave length R
The lower reflective layer 30 made of eflector Stack, QWRS is formed. At this point, the optical thickness of each layer is set to 1/4 of the operating wavelength of 860 nm (the wavelength of the absorption peak of excitons of SMQW). At this time, the reflectance of the reflective layer 30 becomes 95% or more.

As described above, the first λ / 4n reflective layer 2
2 and the second λ / 4n reflective layer 23 are repeatedly grown over 12 cycles (preferably 14 cycles) to form the lower reflective layer 30, and then the N ⁺ -type (5 × 10 ¹⁸ cm ~ ³ ) Al _0.1 Ga _0.9 As 5
The cathode contact layer 24 is formed by growing the cathode contact layer 24 to a thickness of about 00 nm.

Then, undoped A1 _0.1 Ga _0.9 As is grown to a thickness of about 20 nm on the cathode contact layer 24 to form a first buffer layer 25.

Then, an Al _0.04 Ga _0.96 As barrier layer 26 having a thickness of about 6 nm and a 10 nm layer are formed on the buffer layer 25.
A thin quantum well layer (SMQW) 31 having a small thickness is formed by growing a thin quantum well layer composed of a GaAs well layer 27 having a certain thickness in multiple layers (preferably 36 periods).

Then, the thin multi-quantum well layer 31 is formed.
A, which is not doped to a thickness of about 20 nm
The second buffer layer 28 is formed by growing _0.1 Ga _0.9 As.

Finally, on the second buffer layer 28, 506.
P ⁺ type (1 × 10 ¹⁹ cm ~ ³ ) A1 with a thickness of about 7 nm
_An anode contact layer 29 is formed by growing _0.1 Ga _0.9 As.

PI manufactured by the above steps
In N-type SEED, all thicknesses (L) of layers 24-29 above λ / 4 reflective layer (ie lower reflective layer) 30.
Is 1622.7 nm, and the reflection layer 30 is an asymmetric Fabry-bellow cavity (cavity).
(ASPP) is formed. The length of the cavity is λ
/ 4n _avg (where n _avg is the average refractive index of the cavity)
27 times (a constant multiple of an odd number).

As a result, the upper reflection having a reflectance of about 30% is naturally generated at the boundary between the air and the semiconductor.

Therefore, P where SMQW is the real area
A structure of ASFP resonance is formed in the structure of the -I (MQW) -N diode in which the reflectances of the upper and lower reflections are different from each other. At this time, the number of times MQW is repeated (the number of cycles) is a constant that satisfies the following formula 1 in which the total reflectance (RT) of the ASFP cavity becomes zero from the state without external voltage application, that is, zero bias. It is defined as the number m.

RF = RBexp (−2α ₀ mt) (1) where RF is the reflectance of the upper reflection, RB is the reflectance of the lower reflection, and α ₀ is the quantum well at zero bias. Is the optical absorptivity of, and t is the thickness of the quantum well.

In the structure of FIG. 25, α ₀ is 16000.
Assuming that C m ^-1 , RF = 0. 3, RB = 0.
Since 95 and t = 10 nm, the value of m that satisfies Expression 1 at RT = 0 is 36. Therefore, the number of periods 36 of the quantum well is determined. Therefore, the total thickness of the genuine region including SMQW is reduced to about 0.62 μm, and the electric field due to the internal potential in the thermal equilibrium state is
It has a value of 2.4 × 10 4 V / cm.

As described above, the electric field due to the increased internal potential can further increase the reflectance Ron by further reducing the light absorption rate of the SMQW. Assuming that the electric field applied to the diode D1 is a typical SMQWS-SEED value of 0.6 × 10 3 V / cm, d = 0.62 μm.
The electric field applied to 2 can be increased to 4.2 × 10 4 V / cm to increase the bistability of the light. This value is
This is similar to the electric field value applied to D2 when a reverse voltage of 1.8 Volts is applied to a general SMQWS-SEED with d = 1.0 μm.

Formula 1 is a condition for setting the Roff value of ASFP-SEED to 0. The structure of the ASFP resonance is
When the uppermost layer of the lower reflective layer is a substance having a high refractive index (the AlGaAs layer in the case of FIG. 25 of the present embodiment), it can be obtained by making the thickness only an odd multiple of λ / 4n _avg. it can. When the Roff value of ASFP-SEED is allowed up to about 5%, the number of periods of the quantum well can be further reduced and the internal electric field due to this can be further increased. 21
When the ASFP structure composed of periodic SMQWs is further reduced, for example, to a thickness of 0.38 μm in the intrinsic region, the electric field applied to the diode D1 is reduced to a general SMQWS-S.
Assuming an EED value of 0.6 × 10 ³ V / cm, the electric field applied to D2 increases to 7.3 × 10 ⁴ V / cm. This value is SMQWS with d = 1.0 μm.
-SEED is a value similar to the electric field value applied to D2 when a reverse voltage of 5.0 Volts is applied.

Therefore, S presented from this embodiment is
Using MQW-ASFP-SEED, existing SM
Much larger than the S-SEED circuit using QW,
Not only the bistability of light without external voltage can be obtained, but also S-SE made of existing SMQW-SEED
Bistability of light similar to that obtained when VAP = 5.0 Volts is applied to the ED circuit,
A self-biased S-SEED, which is a light bistable element without an externally applied voltage, can be realized.

FIG. 26 is an explanatory view showing the structure of the SMQW-ASFP-SEED according to another embodiment of the present invention for realizing a light bistable seed (NOBS) without an external voltage.

26, is the same as FIG. 25,
Alternatively, corresponding parts are indicated by the same reference numerals.

The manufacturing method of this structure is as follows.

Referring to FIG. 26, first, semi-insulating GaA is used.
An undoped Al _x Ga _1-x As (0.1 < x < having a relatively high refractive index on the s substrate 21.
0.3), a λ / 4n reflective layer (where λ is the wavelength of light) 23 is grown, and a λ / 4n reflective layer 22 made of undoped AlAs having a relatively low refractive index is formed. Grow. By forming these two reflective layers 23 and 22 in 12 cycles or more (preferably repeating 14 times), the lower reflective layer 30 made of a λ / 4 reflective layer (QWRS) is formed. At this time, the optical thickness of each layer is set to ¼ of the operating wavelength (wavelength of the absorption peak of excitons of SMQW).

As described above, the two λ / 4n reflective layers 2
After forming the lower reflective layer 30 by repeatedly growing 3, 22 for 12 cycles or more (preferably 14 cycles), N ⁺ -type Al _x Ga _1-x As is formed on the lower reflective layer 30.
(0.1 < x < 0.3) is grown to form the cathode contact layer 2
4 is formed.

Then, on the cathode contact layer 24, undoped Al _x Ga _1-x As (0.1 < x <
0.3) is grown to a predetermined thickness to form the first buffer layer 25.

After that, on the buffer layer 25, an undoped Al _x Ga _1-x As barrier layer (0.01 < x
< 0.04) 26 and a thin quantum well consisting of an undoped GaAs well layer 27 (preferably 3).
Thin multiple quantum well layer 31 grown for 6 periods)
To form.

Then, the thin multi-quantum well layer 31 is formed.
On top, undoped Al _x Ga _1-x As (0.
The first buffer layer 26 is formed by growing 1 < x < 0.3).

Finally, P ⁺ -type Al _x Ga _1-x As (0.1 < x < 0.3) is grown on the second buffer layer 28 to form the anode contact layer 29.

FIG. 27 shows a bistable seed (N
FIG. 6 is an explanatory view showing a structure of SMQW-ASFP-SEED according to still another embodiment of the present invention for realizing OBS).

In FIG. 27, portions which are the same as or correspond to those in FIG. 25 are indicated by the same symbols.

The manufacturing method of this structure is as follows.

Referring to FIG. 27, first, semi-insulating GaA is used.
On the s substrate 21, undoped Al _x Ga _1-x As (0.1 < x < having a relatively high refractive index is used.
0.3), a λ / 4n reflective layer (where λ is the wavelength of light) 23 is grown, and a λ / 4n reflective layer 22 made of undoped AlAs having a relatively low refractive index is formed. Grow. The two reflective layers 23, 22 are
The lower reflective layer 30 made of a λ / 4 reflective layer (QWRS) is formed by forming the reflective layer 30 in two cycles or more (preferably, repeating 14 times). At this time, the optical thickness of each layer is determined by the operating wavelength (wavelength of the absorption peak of excitons of SMQW).
Make it 1/4 of that.

As described above, the two λ / 4n reflective layers 23, 2
After the lower reflective layer 30 is formed by repeatedly growing 2 for 12 cycles or more (desirably 14 cycles),
P ⁺ type Al _x Ga _1-x As is formed on the lower reflective layer 30.
(0.1 < x < 0.3) is grown to form the anode contact layer 2
9 is formed.

Then, on the anode contact layer 29, undoped Al _x Ga _1-x As (0.1 < x <
0.3) is grown to a predetermined thickness to form the first buffer layer 25.

Then, on the buffer layer 25, an undoped Al _x Ga _1-x As barrier layer (0.01 < x
< 0.04) 26 and undoped GaAs
A thin quantum well layer composed of well layers 27 is grown in multiple layers (preferably 36 periods) to form thin multiple quantum well layers 31.
To form.

Then, on the thin multi-quantum well layer 31, undoped Al _x Ga _1-x As (0.1
< X < 0.3) is grown to form the second buffer layer 28.

Finally, the cathode contact layer 24 is formed on the second buffer layer 28 by growing N ⁺ -type Al _x Ga _1-x As (0.1 < x < 0.3).

As described above, when the present invention described through the preferred embodiments is used, S-SEED and two-dimensional S-SEED having excellent bistable characteristics of light without an applied voltage are used.
It is possible to manufacture an array, an application device using the array, and a two-dimensional array of these.

When a two-dimensional array is formed by utilizing the bistable element for voltageless light according to the present invention, each element can be electrically separated, so that the yield of the element can be increased. , A metal wire for applying an external voltage,
Since a space on the substrate for this purpose is unnecessary, the degree of integration of the array can be greatly increased.

Further, not only the mutual induction action between the electric wires, the mutual interference due to the electromagnetic field, the crosstalk phenomenon and the like can be reduced, but also the circuit for the high speed switching element can be easily realized. Since it is not necessary to connect an electric wire for assembling a semiconductor component including the device of the present invention and an electric wire for applying an external voltage, the manufacturing process can be simplified and the unit cost of the process can be reduced. There is expected.

The voltageless optical bistable seed (NOBS) of FIG. 19 according to the present invention, which has optical bistable characteristics even when no external voltage is applied, is in a state where no externally applied voltage is applied. The voltage between V1 and V2 is NO in FIG.
As shown in the load curve of BS, it can be considered as the voltages Vop and -Vop at the stable operating point.

This is because when NOBS exhibits bistability of light, the electric field applied to each diode is (Vbi-Vo).
p) / ti and (Vbi + Vop) / ti (where ti
Means the total thickness of the intrinsic region).

Therefore, in order to make a large difference in the electric field between the two diodes in the state where there is no voltage applied from the outside, it is advantageous to reduce ti as much as possible. The input resistance of light is not matched A
Since the FP-SEED is configured such that the total thickness (D) of the light absorption layer is smaller than that of the AFP-SEED having the matched light input resistance, ti can be further reduced. is there.

An example of the NOBS light bistable characteristics based on the above-mentioned NOBS principle is shown in FIG. The difference between the resistance-matched AFP-NOBS and the resistance-mismatched AFP-NOBS can be reliably grasped. Since the resistance-matched AFP-NOBS is closer to zero in the off-state value than the non-resistance-matched AFP-NOBS, CR is certainly large, but the width of ΔR and the bistable width of light (ΔP ) Has a relatively small value.

In particular, in the case of NOBS, the value of the reflectance in the ON state is very small when the resistances are matched.
It is somewhat unsuitable for application in optical systems.

[0161]

Therefore, by designing the structure of the AFP-SEED by utilizing the concept of the mismatch of the optical input resistances proposed by the present invention, it is possible to maintain an appropriate CR required from the optical system, It is possible to enable a NOBS having ΔR and a width of optical bistable (ΔP) required for application of an optical system.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a typical symmetrical seed (S-SEED) device.

FIG. 2 is a top view of FIG.

3 is an equivalent circuit diagram of FIG.

FIG. 4 is an equivalent circuit diagram of FIG.

5 is a graph showing a load curve of the circuit shown in FIG.

6 is a graph showing a light bistable characteristic curve of the circuit shown in FIG. 4;

7 is a graph showing a load curve when VAP = 0 in the circuit shown in FIG. 4;

FIG. 8 is an explanatory diagram showing an energy band in a thermal equilibrium state of a conventional PIN diode SEED.

FIG. 9 is a graph showing a load curve when the reverse voltage (VAP) of the S-SEED circuit including the structure SEED of the thin quantum well is 0.

FIG. 10: PIN composed of a thin quantum well structure
Explanatory drawing showing the energy band in the state of thermal equilibrium of the diode SEED of the type.

FIG. 11 is an explanatory diagram showing the structure of a general reflective SEED.

FIG. 12 shows an asymmetric Fabry bellow seed (AFP-
Explanatory drawing which shows the structure of SEED).

FIG. 13 is a graph showing the light absorption coefficient of the reflective SEED at the wavelength of excitons and the reflectance with respect to the square of the thickness of the light absorbing layer.

FIG. 14 is a graph showing a change in absorption coefficient of light with respect to a vertical electric field at a wavelength of an exciton of a multiple quantum well having a nonlinear light absorption characteristic.

FIG. 15 shows the resistance-matching AFP-SEED and the resistance-mismatching AFP-SEED with respect to the square of the light absorption coefficient of the ON / OFF intensity ratio and the light absorption layer thickness in the light bistable characteristic of AFP-SEED. A graph showing the characteristics.

FIG. 16 is a graph showing the characteristics of the difference in ON / OFF reflectance in the light bistable characteristics of AFP-SEED with respect to the light absorption coefficient and the square of the light absorption layer thickness.

FIG. 17 is a top view of a two-dimensional array of S-SEED light bistable elements of FIG.

18 is an equivalent circuit diagram of FIG.

FIG. 19 is a circuit diagram of S-SEED showing characteristics of light bistable without externally applied voltage according to the present invention.

FIG. 20 is a top view showing one example of a voltage-free light bistable element according to the present invention.

FIG. 21 is a top view showing another example of a voltage-free light bistable element according to the present invention.

FIG. 22 is a view of the voltage-free light bistable element 2 shown in FIG.
Top view of an array of dimensions.

FIG. 23 is a schematic view of the bistable element 2 of voltageless light shown in FIG.
Top view of an array of dimensions.

FIG. 24 is an equivalent circuit diagram of a two-dimensional array of voltage-free light bistable elements according to the present invention.

FIG. 25 is an explanatory view showing the structure of SEED according to one embodiment of the present invention.

FIG. 26 is an explanatory view showing the structure of SEED according to another embodiment of the present invention.

FIG. 27 is an explanatory view showing the structure of SEED according to another embodiment of the present invention.

FIG. 28: S-SEE enabling bistable light without voltage
The graph which shows the load curve of D.

FIG. 29 is a resistance mismatched AFP-NOBS (Nonbiased)
FIG. 6 is a graph showing one example of the optical bistable characteristics of AFP-NOBS having a resistance mismatch according to the present invention and Optical Bistable S-SEED).

[Explanation of symbols]

1 ... n-contact layer, 2 ... p-contact layer, 3 ... insulating layer, 4 ... metal wiring, 5 ... metal pad, 6 ... light input / output window.

Claims (12)

[Claims] 1. SEED (Self Electro-optic Effectiv)
e Device) optical logic element, a semi-insulating GaAs substrate and a predetermined refractive index (n) grown on the substrate to a predetermined thickness.
And a second reflective layer which is grown on the first reflective layer to a predetermined thickness and has a refractive index different from the refractive index of the first reflective layer. At least 12
A lower reflective layer that is repeatedly formed in a cycle or more; a first electrode contact layer that is grown to a predetermined thickness on the lower reflective layer; and a first buffer layer that is grown on the first electrode contact layer. A thin multiple quantum well layer in which a barrier layer and a thin quantum well layer are grown in a predetermined cycle on the first buffer layer, and a second buffer layer grown on the thin multiple quantum well layer. A voltage-free light bistable logic device comprising a second electrode contact layer grown on the second buffer layer. 2. The voltage-free optical bistable logic device according to claim 1, wherein the thin multi-quantum well layer comprises a barrier layer and a thin quantum well layer grown for 36 periods. . 3. The voltage-free light bistable logic device according to claim 2, wherein the refractive index of the first reflective layer is relatively smaller than the refractive index of the second reflective layer. 4. The voltage-free light bistable logic device according to claim 2, wherein a refractive index of the first reflective layer is relatively larger than a refractive index of the second reflective layer. 5. The non-contact electrode of claim 1, wherein the contact layer of the first electrode is a P ⁺ anode contact layer, and the second electrode contact layer is an N ⁺ cathode contact layer. Bistable logic element of voltage light. 6. The non-voltage-applied electrode according to claim 1, wherein the first electrode contact layer is an N ⁺ cathode contact layer, and the second electrode contact layer is a P ⁺ anode contact layer. A bistable logic element of light. 7. The first reflective layer is made of undoped AlAs, and the second reflective layer is undoped Al _x Ga.
_{2. The voltageless} light bistable logic element according to claim 1, wherein the logic element is made of _lx As (0.1 < x < 0.3). 8. SEED (Self Electro-optic Effectiv)
In the method of manufacturing a light logic element of e Device), a first λ / 4n reflective layer (where λ is the wavelength of light) made of AlAs having a predetermined refractive index (n) on a semi-insulating GaAs substrate. ) is grown to a thickness of about 72.1nm a, Al has a relatively high refractive index _x Ga _lx As (0.1
The second λ / 4n reflective layer made of < x < 0.3) is 60.7
a step of forming a lower reflection layer by growing the first λ / 4n reflection layer and the second λ / 4n reflection layer for 12 cycles or more, and growing the layer to a thickness of about nm. N ⁺ type Al _{x Gal x} As (0.
1 < x < 0.3) to a thickness of about 500 nm to form a cathode contact layer, and undoped Al on the cathode contact layer.
_x Ga _lx As (0.1 < x < 0.3) is grown to a thickness of about 20 nm to form a first buffer layer, and a thickness of about 6 nm as a barrier layer is formed on the first buffer layer. is the _{Al x Ga lx as (0.1 <} x <0.4) undoped of about 10nm thickness as layer and the well layer Ga
An As layer is sequentially grown, and the barrier layer and the well layer are grown for 36 periods to form a thin multi-quantum well layer (SMQ).
Forming a W), on the well layer of the thin multi-quantum, undoped to about 20nm thick _{Al x Ga lx As (0.1 <} x
< 0.3) to form a second buffer layer, and P ^{+ with} a thickness of about 506.7 nm on the second buffer layer.
And a step of growing Al _{x Gal x} As (0.1 <x <0.3) of a type to form an anode contact layer. 9. An n-contact layer, a p-contact layer, and first and second PIN diodes each having an input / output window for light and having a quantum well region as an intrinsic layer are connected in series to form the quantum layer. In a light bistable logic element in which light absorption from a well region is changed by a photocurrent generated from the PIN diode, the contact layer of the first PIN diode and the second PI are provided.
A voltage-free light bistable logic element directly connected to the contact layer of an N diode. 10. The n-contact layer of the first PIN diode, the light input / output window, and the p-contact layer, and the n-contact layer, the light input / output window, and the p-contact layer of the second PIN diode,
When the logic elements are viewed from above, they are arranged in a straight line in the horizontal direction in the order described above.
The n-contact layer of the IN diode and the p-contact layer of the second PIN diode, and the p-contact layer of the first PIN diode and the n-contact layer of the second PIN diode are respectively connected by metal wiring. A voltage-free light bistable logic device according to claim 9. 11. The first PIN diode and the second PIN diode.
Although arranged in parallel with the PIN diode, the p-contact layer of the second PIN diode is located at a predetermined distance on the right side of the n-contact layer of the first PIN diode, The light input / output windows of the first and second PIN diodes are located on the same straight line in order to facilitate the processing of optical signals in parallel.
The second PI is placed at the predetermined distance directly on the contact layer.
The n-contact layer of the N diode is positioned so that the n-contact layer of the first PIN diode and the second PI are disposed.
10. The non-voltage application method according to claim 9, wherein the p-contact layer of the N diode, the p-contact layer of the first PIN diode and the n-contact layer of the second PIN diode are respectively connected by metal wiring. A bistable logic element of light. 12. A multi-quantum well (MQ) as an intrinsic region.
W) and an upper reflection layer and a lower reflection layer having reflectances different from each other with respect to the resonance wavelength of the excitons of the multiple quantum well, and the cavity length is asymmetrical with the resonance wavelength of the excitons. Bistable logic element (SEED) having a Fabry-Perot (AFP) structure, in which an asymmetric Fabry-Perot bistable logic element (AFP-SEED) having a matched optical input resistance is multiplexed. By having multiple quantum wells with a period number relatively smaller than that of the quantum well (MQW), the resistance of the light input of the structure in which the total thickness (D) of the light absorption layer is reduced. Mismatched voltageless light bistable logic element.