JP2634403B2 - Video signal processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device, and more specifically, to a video signal processing device that compensates for a drop-out of a video signal.

[Conventional technology]

The signal reproduced from the VTR has time axis non-uniformity, drop out and additional noise.Drop out compensation is performed in analog or digital mode at the same time as time axis correction in the video signal time axis correction circuit. Various methods are described in various documents, and as a noise reduction circuit, a circuit that improves S / N by focusing on the correlation between adjacent scanning lines or between fields or frames is known (for example, a specific example of such a circuit). See JP-A-56-40380).

In recent years, both the time axis correction and the noise reduction circuit have been implemented as digital circuits due to the low cost of digital elements and the ease of signal processing after digitization.

[Problems to be solved by the invention]

In general, drop-out compensation in a video signal substitutes a signal approximating a missing portion of a video signal, and the closest approximation to the missing portion is generally made of an adjacent scanning line, a previous field or This is the corresponding part of the frame. Therefore, the conventional drop-out compensation circuit is
When dropouts were detected, they were mechanically substituted for one of these.

However, apart from a still object or an object with little movement, in the case of an object with fast movement, the adjacent scanning line or the previous field or frame is not always strongly correlated with the drop-out part. Depending on the situation, it is preferable to switch such that the adjacent scanning line signal is used, and in another situation, the previous field is used.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a video signal processing device capable of realizing more appropriate compensation for a video signal having an abnormality than before.

[Means for Solving the Problems] A video signal processing apparatus according to the present invention comprises: input means having an input terminal for a video signal and an input terminal for an abnormal signal indicating an abnormality of the video signal; For both, the inter-screen correlation between the screen having the abnormality and the previous screen and the intra-screen correlation of the video signal between the adjacent scanning lines of the screen having the abnormality are both determined, and which is better in correlation. Determining means for outputting such a signal, and interpolating means for interpolating the video signal based on the abnormal signal and the output of the determining means, wherein the interpolating means displays the abnormal video signal in the screen. A first interpolation mode for interpolating with the video signal of the adjacent scanning line used in determining the correlation, and a video signal of a previous screen used in determining the inter-screen correlation of a video signal having an abnormality; The second interpolation mode interpolated by And selecting the interpolation mode having the higher correlation based on the output of the determination means.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic block diagram of an embodiment of the present invention. Reference numeral 10 denotes an input terminal of an analog video signal reproduced from, for example, a BTR or the like. The video signal is converted to a digital signal by the A / D converter 12 and has a capacity of 2H for time axis correction.
Is input to the line memory 14. A color burst signal and a horizontal synchronization signal synchronized with the video signal supplied to the terminal 10 are supplied to the terminals 16 and 18, respectively.The color burst signal is input to a well-known APC circuit 20 such as a VTR, and the horizontal synchronization signal Is also input to the APC circuit 20 via the well-known AFC circuit 22. As a result, the APC circuit 20 outputs a timing signal synchronized with the above-described color burst signal and horizontal synchronization signal. The output of the APC circuit 20 controls the timing of the A / D converter 12 and writes ( W) Address counter
24 to control writing of the digital video signal into the memory 14. Reference numeral 26 denotes a crystal oscillator which oscillates stably, and its output controls a read (R) address of the memory 14 to output a digital video signal having a fixed time axis on a line 28. 29 is a read address counter.

The circuits 20, 22, 24, 26, 29 and the line memory 14 constitute a time axis correction circuit, and the configuration and operation itself are already known.

The video signal on the line 28 is supplied to an adder 32 after being multiplied by a coefficient k (0 to 1) in a multiplier 30 capable of externally controlling a multiplication coefficient k. Although details will be described later, the adder 32 includes:
A signal obtained by multiplying the video signal approximately one field before by (1-k) is input. Thus, the adder 32 outputs a video signal with reduced noise. Details of this noise reduction are described in the above-mentioned Japanese Patent Application Laid-Open No. 56-40380.

The output of the adder 32 is the switching terminal 34a of the flow path switch 34.
The common pole 34c is connected to the input of the field memory 36 having a capacity of 262H (corresponding to almost one field). This memory 36 is not a field memory but a 1
A so-called frame memory for storing the equivalent of a frame may be used. The capacity of the memory 36 is preferably equal to the even number H, but if the memory 36 is equal to the odd number H, a chroma signal inverting circuit is required at an appropriate place. The output of the memory 36, that is, the video signal 262H before the video signal on the line 28 is D / A
The converter 40 returns the signal to an analog signal.

The output of the memory 36 is multiplied by (1-k) by a multiplier 42 capable of externally controlling the multiplication coefficient (1-k) corresponding to the multiplication coefficient k of the multiplier 30. Supplied to input.

The subtraction circuit 44 sequentially compares the output of the memory 36 and the signal on the line 28 on the time axis, and outputs a signal indicating the absolute value of the instantaneous difference. The subtraction circuit 46 connects the signal on line 28 with the A / D
It compares the output of the converter 12 (the signal 2H after the signal on the line 28) and outputs a signal indicating the absolute value of the instantaneous difference. The subtraction circuit 44 indicates the degree of image movement or correlation between fields, while the subtraction circuit 46 indicates the degree of correlation between 2H different adjacent scanning lines in the field.

The comparison circuit 48 compares the output of the subtraction circuit 44 with the output of the subtraction circuit 46 and outputs a binary signal (high or low) indicating which correlation is stronger between adjacent scanning lines and between fields. The output of the comparison circuit 48 is connected to a switching control input of a flow path switch 52 via a 1H delay circuit 50. The common pole 52c of the switch 52 is connected to the second terminal 34b of the switch 34, the output of the memory 36 is supplied to the first terminal 52a of the switch 52, and the second terminal 52b is
The output of the A / D converter 12 is supplied.

The drop-out detection signal at pin 56 is a 2H delay circuit
It is supplied to the switching control terminal of the switch 34 via 58. The delay circuit 58 is for adjusting to the delay by the memory 14 for time axis correction. Switch 34 is normally connected to terminal 34
Although a is connected to the common pole 34c, the terminal 34b is connected to the common pole 34c with a delay of 2H when dropout is detected.

When the correlation between adjacent scanning lines in a field is stronger than the correlation between fields (the output of the subtraction circuit 46 is larger than the output of the subtraction circuit 44), the switch 52 switches the terminal 52b with a delay of 1H by the output of the comparison circuit 48. The terminal 52a is connected to the common pole 52c, and vice versa.

Next, the operation of the circuit shown in FIG. 1 will be described focusing on the drop-out function. FIG. 2 illustrates several scan lines of two consecutive fields. Now, it is assumed that the scanning line i of the field # 2 is on the line 28 and a drop-out is detected on the scanning line i. When the scan line i is on the line 28, the scan line i-262 is supplied from the memory 36 to the subtraction circuit 44, and the scan line i + 2 is supplied to the output of the A / D converter 12. Therefore, the comparison circuit
48 compares the degree of correlation between the scanning line i and the scanning line i-262 (the output of the subtraction circuit 44) with the degree of correlation between the scanning line i and the scanning line i + 2 (the output of the subtraction circuit 46), A signal indicating the larger correlation (the smaller output value) is output.

However, actually, since there is a 1H delay circuit 50, the switch
52, a scan line i-1, i-263, i +
A switching control signal indicating the same comparison result between 1 is applied. The provision of the 1H delay circuit 50 cannot be used as a signal for checking the degree of correlation because the scan line i itself has a dropout, and therefore, the 1H delay circuit 50 cannot be used between adjacent scan lines in the field. This is for judging which correlation degree is higher between the field and the field based on the normal signal one scanning line before.

If the correlation between the fields is greater than the correlation within the field, the common pole 52c of the switch 52 connects to the terminal 52a, otherwise connects to the terminal 52b. Of course, the common pole 34c of the switch 34 is connected to the terminal 34b by the drop-out detection signal.

Therefore, when the correlation between the fields is strong, the memory 36
(Ie, the signal at the corresponding position in the previous field) is input again to the memory 36 via the switches 52 and 34, and when the correlation in the field is stronger, the A / D The output of the converter 12 (the signal of the adjacent scanning line in the same field) is supplied to the memory 36.

In general, it is considered that a signal from a corresponding position in the field memory 36 or the frame memory has a stronger correlation than an adjacent scanning line. Therefore, the output of the memory 36 is dropped out as a system default state. It is preferable to initialize it so that it is used as a substitute signal at the time. In this sense, it is not necessary to always compare the intra-field correlation and the inter-field or inter-frame correlation, and it may be possible to select which signal to substitute based on one correlation. FIG. 3 focuses on controlling the coefficient k of the multipliers 30 and 42 by the correlation signal between fields or between frames for noise reduction. The subtraction circuit 46 is omitted, and the comparison circuit 48 4 shows a configuration in which the output is compared with a constant reference signal _Vref .

In a signal standardized to a certain extent such as a television signal, the degree of correlation between fields is used to select a video signal of the previous field or a signal of an adjacent scanning line in the same field as an alternative signal at the time of dropout. Also, more favorable results can be obtained as compared with the conventional example in which only one of them is always used. It should be noted that the reason why the scanning lines different by 2H are used as the adjacent scanning lines is that the phases of the chroma signals are the same, and if a chroma signal phase inverting circuit is provided, 1H
The difference scanning line may be used.

The operation of the circuit of FIG. 3 is the same as that of the circuit of FIG. 1 except that the number of reference signals for determining the degree of correlation is one. However, it goes without saying that the delay circuit 50 may be connected not to the output side of the comparison circuit 48 but to the input side.

In the above description, the input signal of the D / A converter 40 may be taken not from the output side of the memory 36 but from the input side, that is, from the common pole 34c of the switch 34. The video signal at the terminal 10 may be a composite color television signal, a luminance signal only, a chrominance signal or a carrier chrominance signal. Therefore, unless otherwise noted, a video signal should be construed broadly as such.

〔The invention's effect〕

As can be seen from the above description, according to the present invention, as an alternative signal of the abnormal video signal, the inter-screen correlation between the abnormal screen and the previous screen and the adjacent scanning of the abnormal screen Since both the in-screen correlation of the video signal between the lines is determined and the video signal with the better correlation is used,
It is possible to realize more appropriate compensation for an abnormal video signal than to perform interpolation based on prediction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a video signal digital processing circuit including a drop-out compensation circuit according to the present invention, and FIG. 2 is a diagram showing some scanning lines of a video signal in two continuous fields. FIG. 3 shows a modification of an alternative embodiment of the invention. 10 video signal input terminal, 12 A / D converter, 14 2H
Memory, 16 ... Color burst signal input terminal, 18 ...
Horizontal synchronization signal input terminal, 20 APC circuit, 22 AFC circuit, 24 Write address counter, 29 Read address counter, 30 Multiplier, 32 Adder, 34 Switch, 36: Field memory, 40: D / A converter, 42: Multiplier, 44, 46: Subtraction circuit, 48: Comparison circuit, 50: Delay circuit, 52: Switch, 56 …… Drop-out detection signal input terminal, 58 …… Delay circuit

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hiroto Yasumura 770 Shimonoge, Takatsu-ku, Kawasaki-shi, Kanagawa Prefecture Inside the Canon Co., Ltd.Tamagawa Office (72) Inventor Riki Sato 770 Shimonoge, Takatsu-ku, Kawasaki-shi, Kanagawa Canon Inc. In-house (72) Inventor Tadayoshi Nakayama 770 Shimonoge, Takatsu-ku, Kawasaki-shi, Kanagawa Prefecture Tamagawa Works of Canon Inc. (56) References JP-A-60-86985 (JP, A) JP-A-61-56584 (JP, A)

Claims (1)

(57) [Claims] An input unit having an input terminal for a video signal and an input terminal for an abnormal signal indicating an abnormality of the video signal; and Judgment means for judging both the inter-screen correlation and the intra-screen correlation of the video signal between adjacent scanning lines of the abnormal screen, and outputting a signal indicating which is more relevant, the abnormal signal and Interpolating means for interpolating the video signal based on the output of the judging means, the interpolating means of the adjacent scanning line used when judging the in-screen correlation of the abnormal video signal A first interpolation mode for interpolating with a video signal, and a second interpolation mode for interpolating an abnormal video signal with a video signal of a previous screen used in determining the inter-screen correlation, and Based on the output of the judgment means, A video signal processing apparatus characterized by selecting the interpolation mode for the better sexually.