JP2633505B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2633505B2
JP2633505B2 JP7133680A JP13368095A JP2633505B2 JP 2633505 B2 JP2633505 B2 JP 2633505B2 JP 7133680 A JP7133680 A JP 7133680A JP 13368095 A JP13368095 A JP 13368095A JP 2633505 B2 JP2633505 B2 JP 2633505B2
Authority
JP
Japan
Prior art keywords
wiring pattern
mounting
semiconductor device
electric wiring
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP7133680A
Other languages
Japanese (ja)
Other versions
JPH08330492A (en
Inventor
浩守 鳥羽瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP7133680A priority Critical patent/JP2633505B2/en
Publication of JPH08330492A publication Critical patent/JPH08330492A/en
Application granted granted Critical
Publication of JP2633505B2 publication Critical patent/JP2633505B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
複数の実装面を有する半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a plurality of mounting surfaces.

【0002】[0002]

【従来の技術】従来の半導体装置は、図5および図6に
示すように、半導体素子1の各信号端子と金属細線2に
て接続された1系統の電気的配線層13の電気的配線パ
ターン13aを介して図7に示すように、外部端子7に
電気的に接続され、外部端子7は、一定面が実装面とな
るように配置されていた。近年、図8および図9に示す
ように、半導体素子1の信号端子に接続する電気的配線
パターン13aがパッケージ部材の幅の狭い一つの側面
に向って引き出され、その先端部がパッケージ面で露出
し外部端子7とするような構造とすることにより、パッ
ケージを配線基板に垂直に立てて狭い面での高密度実装
を可能にしようとする例もある(特開平5−20631
5号公報参照)。
2. Description of the Related Art In a conventional semiconductor device, as shown in FIGS. 5 and 6, an electrical wiring pattern of a single electrical wiring layer 13 connected to each signal terminal of a semiconductor element 1 by a thin metal wire 2. FIG. As shown in FIG. 7, the external terminal 13 is electrically connected to the external terminal 7 via the terminal 13a. The external terminal 7 is arranged such that a fixed surface is a mounting surface. In recent years, as shown in FIGS. 8 and 9, the electrical wiring pattern 13a connected to the signal terminal of the semiconductor element 1 is drawn out toward one narrow side surface of the package member, and its tip is exposed on the package surface. In some cases, the package is set up vertically on the wiring board to enable high-density mounting on a narrow surface by adopting a structure in which the external terminals 7 are provided (Japanese Patent Laid-Open No. Hei 5-20631).
No. 5).

【0003】[0003]

【発明が解決しようとする課題】この従来の半導体装置
では、実装面が固定化されているため、半導体装置の高
密度実装化及び薄型化に伴う実装高制限等の実装者側の
要求に対し個別に実装形態の異なる半導体装置を用意し
ておく必要があり、半導体製造者側では同一の半導体素
子を搭載した同一機能の半導体装置でも多品種対応を図
らなければならないという問題点があった。
In this conventional semiconductor device, since the mounting surface is fixed, there is a need for a mounter to meet a demand such as a mounting height limitation due to high density mounting and thinning of the semiconductor device. It is necessary to separately prepare semiconductor devices having different mounting forms, and there has been a problem that a semiconductor manufacturer has to cope with a wide variety of semiconductor devices having the same function mounted with the same semiconductor element.

【0004】本発明の目的は、実装形態の相違による多
品種化が防止でき、自由に実装面を選択できる半導体装
置を提供することにある。
An object of the present invention is to provide a semiconductor device which can prevent a variety of products due to a difference in mounting form and can freely select a mounting surface.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置は、
半導体素子搭載部に搭載された半導体素子と、この半導
体素子の信号端子に金属細線を介してそれぞれの信号配
線毎に接続された第1の電気配線層の電気的配線パター
ンと、この電気的配線パターンに接続し四方向の側面に
設けられた外部端子と、前記電気的配線パターンにスル
ーホールを介して接続する第2の電気配線層の電気的配
線パターンと、この電気的配線パターンに接続する実装
側面に設けられた外部端子と、前記第2の電気配線層の
電気的配線パターンにスルーホールを介して接続する第
1の電気的配線層の独立した電気的配線パターンと、こ
の独立した電気的配線パターンに接続する前記実装側面
に設けられた外部端子とを有することを特徴とする。
According to the present invention, there is provided a semiconductor device comprising:
A semiconductor element mounted on the semiconductor element mounting portion, an electric wiring pattern of a first electric wiring layer connected to a signal terminal of the semiconductor element via a thin metal wire for each signal wiring, and the electric wiring External terminals connected to the pattern and provided on four side surfaces, an electric wiring pattern of a second electric wiring layer connected to the electric wiring pattern via through holes, and connection to the electric wiring pattern. An external terminal provided on a mounting side surface, an independent electric wiring pattern of a first electric wiring layer connected to an electric wiring pattern of the second electric wiring layer via a through hole, And an external terminal provided on the mounting side surface to be connected to the static wiring pattern.

【0006】[0006]

【実施例】次に、本発明の実施例について図面を参照し
て説明する。
Next, embodiments of the present invention will be described with reference to the drawings.

【0007】図1は本発明の一実施例の断面図である。
本発明の一実施例の半導体装置は、図1に示すように、
半導体素子搭載部に搭載された半導体素子1は、電気的
配線材料である金属細線2等を介して第1の電気配線層
(以下、A層と記す)3の電気的配線パターンに接続さ
れている。また、各信号は、A層3の独立した配線パタ
ーンに設けられたスルーホール4aによって、それぞれ
独立に第2の電気配線層(以下、B層と記す)5にも接
続されている。一方、B層5の電気的配線パターンはス
ルーホール4bを介してA層3のそれぞれ独立した電気
的配線パターンに接続している。
FIG. 1 is a sectional view of one embodiment of the present invention.
A semiconductor device according to an embodiment of the present invention includes, as shown in FIG.
The semiconductor element 1 mounted on the semiconductor element mounting portion is connected to an electric wiring pattern of a first electric wiring layer (hereinafter, referred to as an A layer) 3 via a thin metal wire 2 or the like as an electric wiring material. I have. Each signal is also independently connected to a second electric wiring layer (hereinafter, referred to as a B layer) 5 by a through hole 4 a provided in an independent wiring pattern of the A layer 3. On the other hand, the electrical wiring patterns of the B layer 5 are connected to the independent electrical wiring patterns of the A layer 3 via the through holes 4b.

【0008】図2(a),(b)はそれぞれ図1のA
層,B層の透視平面図である。図2(a),(b)に示
すように、A層3には各信号毎の独立した電気的配線パ
ターン3aが形成されており四方向の各側面に設けられ
た外部端子に接続している。一方、A層3の電気的配線
パターン3aはスルーホール4aを介してB層5の電気
的配線パターン5aに接続している。更に、電気的配線
パターン5aは、スルーホール4bを介してA層3の半
導体素子1の信号端子に接続する電気的配線パターン3
aと独立した電気的配線パターン3bに接続し、電気的
配線パターン3a,3bおよび5aは集約して所定の実
装側面6に設けられた外部端子に接続している。
FIGS. 2A and 2B respectively show A in FIG.
It is a perspective plan view of a layer and a B layer. As shown in FIGS. 2A and 2B, an independent electrical wiring pattern 3a for each signal is formed on the A layer 3 and connected to external terminals provided on each side surface in four directions. I have. On the other hand, the electric wiring pattern 3a of the A layer 3 is connected to the electric wiring pattern 5a of the B layer 5 via the through hole 4a. Further, the electric wiring pattern 5a is connected to the signal terminal of the semiconductor element 1 of the A layer 3 via the through hole 4b.
The electric wiring patterns 3a, 3b and 5a are connected to an external terminal provided on a predetermined mounting side surface 6 in an integrated manner.

【0009】図3(a),(b)はそれぞれ図2の実装
側面以外の側面と所定の実装側面の外部端子の配置を示
す側面図、図4(a),(b)は図3の外部端子を用い
た実装方法を説明する斜視図である。図3(a),
(b)に示すように、実装側面6以外の側面にはA層3
の電気的配線パターン3aに接続する外部端子7が設け
られている。一方、実装側面6の側面にはA層3の電気
的配線パターン3aと、B層5の電気的配線パターン5
aとA層3の電気的配線パターン3b間を接続するスル
ーホール4bを用いて所定の信号配線を二経路に分割し
た二系統の外部端子7を配置にすることで、図4
(a),(b)に示すように、一つの半導体装置で横型
の平面実装と縦型の垂直実装を可能とし、半導体装置実
装者側が用途により実装形態を自由に選択できるという
効果が得られ、在庫管理も容易になる。更に、電気配線
層や外部端子の追加等により信号配線層を細分化するこ
とで、実装側面を二面以上にすることも可能である。
FIGS. 3A and 3B are side views showing the arrangement of external terminals on a side surface other than the mounting side surface of FIG. 2 and a predetermined mounting side surface, respectively. FIGS. 4A and 4B are diagrams of FIG. It is a perspective view explaining the mounting method using an external terminal. FIG. 3 (a),
As shown in (b), the side other than the mounting side 6 has the A layer 3
An external terminal 7 connected to the electrical wiring pattern 3a is provided. On the other hand, the electrical wiring patterns 3a of the A layer 3 and the electrical wiring patterns 5 of the
By arranging two systems of external terminals 7 in which a predetermined signal wiring is divided into two paths using a through hole 4b connecting between the electrical wiring pattern 3b of the A layer 3 and the electrical wiring pattern 3b of FIG.
As shown in (a) and (b), it is possible to achieve horizontal planar mounting and vertical vertical mounting with one semiconductor device, and the semiconductor device mounter can freely select a mounting mode depending on the application. In addition, inventory management becomes easy. Further, by subdividing the signal wiring layer by adding an electric wiring layer or an external terminal or the like, the mounting side surface can be made two or more.

【0010】[0010]

【発明の効果】以上説明したように本発明は、容易に実
装形態を選択できる実装面を複数設けることにより、半
導体製造者側には実装形態の相違による多品種化が防止
でき、一方、半導体実装側にとっては自由に実装形態を
選択できるということから半導体装置部品の共用化がは
かれるという効果がある。これによって、在庫管理面で
大きな効果が期待できる。
As described above, according to the present invention, by providing a plurality of mounting surfaces from which a mounting form can be easily selected, a semiconductor manufacturer can be prevented from diversifying products due to differences in mounting forms. Since the mounting side can freely select the mounting mode, there is an effect that the semiconductor device components can be shared. As a result, a great effect can be expected in terms of inventory management.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1は本発明の一実施例の断面図である。FIG. 1 is a sectional view of one embodiment of the present invention.

【図2】(a),(b)はそれぞれ図1のA層,B層の
透視平面図である。
2 (a) and 2 (b) are perspective plan views of an A layer and a B layer of FIG. 1, respectively.

【図3】(a),(b)はそれぞれ図2の実装側面以外
の側面と所定の実装側面の外部端子の配置を示す側面図
である。
FIGS. 3A and 3B are side views showing the arrangement of external terminals on a side surface other than the mounting side surface of FIG. 2 and a predetermined mounting side surface, respectively.

【図4】(a),(b)は図3の外部端子を用いた実装
形態を説明する斜視図である。
FIGS. 4A and 4B are perspective views illustrating a mounting mode using the external terminals of FIG. 3;

【図5】従来の半導体装置の一例の断面図である。FIG. 5 is a sectional view of an example of a conventional semiconductor device.

【図6】図5の電気的配線パターンの一例の透視平面図
である。
FIG. 6 is a perspective plan view of an example of the electrical wiring pattern of FIG. 5;

【図7】図5の半導体装置の実装形態を説明する斜視図
である。
FIG. 7 is a perspective view illustrating a mounting mode of the semiconductor device of FIG. 5;

【図8】従来の電気的配線パターンの他の例の透視平面
図である。
FIG. 8 is a perspective plan view of another example of a conventional electric wiring pattern.

【図9】図8の半導体装置の実装形態を説明する斜視図
である。
FIG. 9 is a perspective view illustrating a mounting mode of the semiconductor device of FIG. 8;

【符号の説明】[Explanation of symbols]

1 半導体素子 2 金属細線 3 A層 3a,3b,5a,13a 電気的配線パターン 4a,4b スルーホール 5 B層 6 実装側面 7 外部端子 13 電気的配線層 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Fine metal wire 3 A layer 3a, 3b, 5a, 13a Electrical wiring pattern 4a, 4b Through hole 5 B layer 6 Mounting side surface 7 External terminal 13 Electrical wiring layer

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体素子搭載部に搭載された半導体素
子と、この半導体素子の信号端子に金属細線を介してそ
れぞれの信号配線毎に接続された第1の電気配線層の電
気的配線パターンと、この電気的配線パターンに接続し
四方向の側面に設けられた外部端子と、前記電気的配線
パターンにスルーホールを介して接続する第2の電気配
線層の電気的配線パターンと、この電気的配線パターン
に接続する実装側面に設けられた外部端子と、前記第2
の電気配線層の電気的配線パターンにスルーホールを介
して接続する第1の電気的配線層の独立した電気的配線
パターンと、この独立した電気的配線パターンに接続す
る前記実装側面に設けられた外部端子とを有することを
特徴とする半導体装置。
1. A semiconductor element mounted on a semiconductor element mounting portion, and an electric wiring pattern of a first electric wiring layer connected to a signal terminal of the semiconductor element via a thin metal wire for each signal wiring. An external terminal connected to the electric wiring pattern and provided on a side surface in four directions; an electric wiring pattern of a second electric wiring layer connected to the electric wiring pattern via a through-hole; An external terminal provided on a mounting side surface connected to the wiring pattern;
And an independent electrical wiring pattern of the first electrical wiring layer connected to the electrical wiring pattern of the first electrical wiring layer through the through-hole, and provided on the mounting side surface connected to the independent electrical wiring pattern. A semiconductor device having an external terminal.
【請求項2】 前記実装面を少くとも二面有することを
特徴とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein said semiconductor device has at least two mounting surfaces.
【請求項3】 前記半導体素子の信号端子に対応する外
部端子が少くとも一端子有することを特徴とする請求項
1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein an external terminal corresponding to a signal terminal of said semiconductor element has at least one terminal.
JP7133680A 1995-05-31 1995-05-31 Semiconductor device Expired - Lifetime JP2633505B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7133680A JP2633505B2 (en) 1995-05-31 1995-05-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7133680A JP2633505B2 (en) 1995-05-31 1995-05-31 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH08330492A JPH08330492A (en) 1996-12-13
JP2633505B2 true JP2633505B2 (en) 1997-07-23

Family

ID=15110376

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7133680A Expired - Lifetime JP2633505B2 (en) 1995-05-31 1995-05-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2633505B2 (en)

Also Published As

Publication number Publication date
JPH08330492A (en) 1996-12-13

Similar Documents

Publication Publication Date Title
US5545920A (en) Leadframe-over-chip having off-chip conducting leads for increased bond pad connectivity
US5309020A (en) Packaged semiconductor device assembly including two interconnected packaged semiconductor devices mounted on a common substrate
US5691569A (en) Integrated circuit package that has a plurality of staggered pins
JP2633505B2 (en) Semiconductor device
US20020141169A1 (en) Electronic apparatus having a plurality of printed board layers
JPH06326500A (en) Mounting method for board of package ic
JPH09186424A (en) Printed circuit board
JP2935356B2 (en) Semiconductor device and substrate, and mounting structure of semiconductor device
JP3701242B2 (en) Connection system
JP3589941B2 (en) Semiconductor device
JPH11177245A (en) 3-dimentional mounting method
US6218865B1 (en) Semiconductor device having function blocks with obliquely arranged signal terminals connected through two-dimensionally extensible signal lines
JPH0750476A (en) Multilayer printed wiring board
JP2857823B2 (en) Electronic component mounting structure on circuit board
JP2694804B2 (en) Pin grid array semiconductor package
JP2000138251A (en) Semiconductor device and wiring board
JPH03205859A (en) Semiconductor device
JP4229086B2 (en) Semiconductor device
JPH0955450A (en) Mounting board
JPH03265190A (en) Connection of printed wiring board
KR19980030136A (en) Printed Circuit Boards Can Increase Time-Wired Wiring Rates
JPH10189809A (en) Semiconductor package and semiconductor device using it
JPH0529746A (en) Semiconductor mounting board
JPH06268342A (en) Circuit board
JPH06333967A (en) Printed wiring board

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19970212