JP2633092B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to an improvement in a method for manufacturing a MOS transistor for high withstand voltage.

[0002]

2. Description of the Related Art Conventionally, a MOS transistor characterized by a high breakdown voltage operation has a gate electrode, a source and a drain, and a low-concentration impurity of the same conductivity type as the source and the drain for reducing an electric field between them. It is composed of layers. There are two types of high voltage MOS transistors, silicon gate MOS transistors and aluminum gate MOS transistors, depending on the material of the gate electrode.

[0003]

The silicon gate M
The OS transistor is suitable for miniaturization and high speed because of its self-aligned gate structure, but has a problem that the manufacturing method is complicated, the number of days required for the manufacturing is long, and the price is high. On the other hand, the aluminum gate MOS transistor is simpler and requires less production time and is less expensive than a silicon gate MOS transistor because the electrodes and wiring are formed in the same process, but the Al-based metal of the gate electrode has a lower melting point. Therefore, a low-concentration impurity layer is formed first, and then a gate electrode is formed. This requires a large overlapping margin between the gate electrode and the low-concentration diffusion layer.
There is a problem that it is not suitable for speeding up and its application is limited.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has been made in view of the MOS technology in which miniaturization and high speed have been achieved.
An object of the present invention is to provide a method for manufacturing a semiconductor device in which a transistor can be manufactured by a simple process to manufacture a semiconductor device.

[Means for Solving the Problems]

According to the present invention, (a) after a first ion implantation is performed in a first conductivity type silicon substrate using a first silicon oxide film patterned on the substrate surface as a mask,
Forming a source and a drain made of the second conductivity type high concentration impurity layer surrounded or not surrounded by the second conductivity type low concentration impurity layer by performing the heat treatment;
(B) The oxide film on the source and drain generated by the above process and the region between the source and drain of the first silicon oxide film are removed, and the second silicon oxide film and the first silicon nitride film are formed on the removed surface. Forming a gate insulating film by stacking in order, forming an Al-based metal gate electrode layer in a predetermined region on the gate insulating film, and (c) forming the Al-based metal gate electrode layer in the first conductivity type silicon substrate. A second ion implantation is performed using a mask, and the substrate is covered with an insulating film. Then, a second heat treatment is performed at a temperature at which the Al-based metal can be recrystallized. A method of manufacturing a semiconductor device, characterized by manufacturing a semiconductor device having a high breakdown voltage by a step of forming a second conductivity type low concentration impurity layer for achieving self-alignment with a gate electrode layer.

According to the present invention, (a) performing a first ion implantation into a first conductivity type silicon substrate using a first silicon oxide film patterned on the substrate surface as a mask and then performing a first heat treatment; Thereby, a source and a drain formed of the second conductive type high-concentration impurity layer surrounded or not surrounded by the second conductive type low-concentration impurity layer are formed.

As the first conductivity type silicon substrate, either a p-type or n-type silicon substrate can be used.

The first silicon oxide film is for masking the surface of the first conductivity type silicon substrate other than the source and drain formation regions against the first ion implantation.
A method of laminating silicon oxide on a substrate by a known method so as to have a thickness of usually 200 to 500 mm, and performing patterning for removing silicon oxide on a source / drain formation region by photolithography. Can be.

The first ion implantation is for doping the source and drain formation regions of the first conductivity type silicon substrate with a high concentration of impurities. It can be performed by implanting a high concentration of seed impurities.

In the first heat treatment, the impurity implanted at a high concentration into the source and drain formation regions is diffused into the silicon substrate and activated, and the second impurity is surrounded by the second conductive type low concentration impurity layer or not. This is for forming a source and a drain made of a conductive type high concentration impurity layer, and is usually carried out at 700 to 1000 ° C.

A source and a drain composed of a second-conductivity-type high-concentration impurity layer surrounded by a second-conductivity-type low-concentration impurity layer are obtained by subjecting a substrate into which two kinds of impurities having different diffusion rates are implanted to a first heat treatment. It is formed. The impurity concentrations are 10 ¹⁶ / cm ³ and 10 ¹⁸ / cm ³ , respectively.
The second-conductivity-type low-concentration impurity layer is preferably formed because an applied voltage can be reduced and a transistor included therein can have a high withstand voltage. The source and drain formed of the second conductive type high concentration impurity layer not surrounded by the second conductive type low concentration impurity are formed by subjecting the substrate into which one kind of impurity has been implanted to the first heat treatment. The second-conductivity-type high-concentration impurity layer can improve the ohmic property of the contact resistance with the metal electrode.

According to the present invention, (b) the oxide film on the source and the drain and the region between the source and the drain of the first silicon oxide film which are generated by the above process are removed, and the second oxide film is formed on the removed surface. A silicon film and a first silicon nitride film are sequentially stacked to form a gate insulating film, and an Al-based metal gate electrode layer is formed in a predetermined region on the gate insulating film.

The gate insulating film insulates the gate electrode layer from the silicon substrate, protects the silicon substrate from contamination, and stabilizes the state of the interface between the silicon substrate and the gate insulating film (silicon oxide). In addition, the second silicon oxide film and the first silicon nitride film can be sequentially stacked.

The second silicon oxide film preferably has excellent insulating properties, and can be formed by a known method so as to have a thickness of usually 300 to 700 mm. The first silicon nitride film is preferably one capable of protecting the underlying silicon substrate element from contamination, and can be formed by a known method so as to have a thickness of usually 300 to 500 °.

The Al-based metal gate electrode layer includes a source,
A gate insulating film is formed on a central region between the source and the drain at a predetermined distance from the drain. The formation of the Al-based metal gate electrode layer can be performed using a known method, for example, using an Al-based metal such as Al-Si or Al-Si-Ca.

According to the present invention, (c) a second ion implantation is performed in the first conductivity type silicon substrate using the Al-based metal gate electrode layer as a mask, the substrate is covered with an insulating film, and then the Al-based metal is reused. By performing the second heat treatment at a temperature that can crystallize, a second conductivity type low concentration impurity layer adjacent to the source and the drain at a predetermined depth and achieving self-alignment with the Al-based metal gate electrode layer is formed.

In the second ion implantation, the impurity is implanted into the first conductivity type silicon substrate so as to be disposed in a region adjacent to the source and the drain at a predetermined depth and achieving self-alignment with the Al-based metal gate electrode layer. This is performed in a region extending from below the end of the Al-based metal gate electrode layer of the first conductivity type silicon substrate to the source and the drain using the Al-based metal gate electrode layer as a mask.

Further, the second ion implantation is performed until the impurity reaching a predetermined depth of the first conductivity type silicon substrate has a predetermined concentration.

The above-mentioned depth is preferably a depth suitable for alleviating the electric field applied to the source and the drain, and the position where the impurity concentration becomes maximum is usually 1000 to 3000 °.

The impurity concentration at this depth is usually 10
It is preferable to the ^{17-10 18} Quai / cm ^3.

Further, after the second ion implantation, the ion implantation is preferably performed in the same manner as the second ion implantation except that the depth is shallow (1000 ° or less) because the withstand voltage can be further increased. .

The insulating film prevents the element from being contaminated by external contaminants such as alkali ions and promotes the recrystallization of the Al-based metal constituting the gate electrode layer.
Is used to suppress the protrusion of the silicon oxide film at the interface, and a silicon oxide film or a silicon nitride film can be stacked on the gate electrode formation surface so as to have a predetermined thickness.
It is effective to increase the thickness of the film within a range where cracks do not occur in the film due to thermal stress.

The insulating film is made of, for example, ³¹ P ⁺ ,
It is preferable that impurities such as are formed at a low concentration because the action of preventing contaminants is improved.

The second heat treatment activates the impurities implanted into the first conductivity type silicon substrate by the second ion implantation to form a second conductivity type low concentration impurity layer and to form an Al-based material forming a gate electrode. This is for recrystallizing the metal, and is preferably performed at a temperature of usually 480 to 500 ° C. using an apparatus such as a furnace (electric furnace).

The obtained second conductivity type low concentration impurity layer is adjacent to the source and the drain at a predetermined depth, and achieves self-alignment with the Al-based metal gate electrode layer. It is relaxed and electrically stable without depletion of the interface with respect to the high electric field of the gate electrode.

According to the present invention, it is possible to manufacture a semiconductor device having a high withstand voltage by further covering the insulating film with a cover glass as necessary to improve the reliability. This pressure resistance is usually 20 to 30V.

[0027]

The second ion implantation forms an impurity layer which achieves self-alignment with the Al-based metal gate electrode layer in the first conductivity type silicon substrate, and the second heat treatment does not thermally alter the Al-based metal gate electrode layer. The impurities implanted at a predetermined depth in the first conductivity type silicon substrate are activated by the second ion implantation to form a second conductivity type low concentration impurity layer, and the second conductivity type low concentration impurity layer is applied to the source and the drain. Relieve high electric fields.

[0028]

EXAMPLE 1 A specific manufacturing method will be described below. FIG. 1 shows a method of manufacturing an N-channel MOS transistor using a P-type conductor substrate.

As shown in FIG. 1A, a silicon oxide film 4 is formed on a P-type silicon substrate 1, a source / drain region is selectively etched, ³¹ P ⁺ ion implantation and ⁷⁵ AS are performed.
⁺ Perform ion implantation. Then, ³¹ P
⁺ Ions and ⁷⁵ AS ⁺ ions are diffused into the silicon substrate 1. At this time, the low-concentration impurity layer 2 and the high-concentration impurity layer 3 of the diffusion layers having different impurity concentrations are formed due to the difference in the diffusion rates of the ³¹ P ⁺ ions and the ⁷⁵ AS ⁺ ions (impurities). The low-concentration impurity layer 2 is effective for relaxing the voltage applied to the source and the drain and increasing the breakdown voltage. High concentration impurity layer 3
Has good ohmic contact resistance with the metal electrode.

Next, as shown in FIG. 1B, after removing the silicon oxide film on the source / drain regions and on the surface of the silicon substrate sandwiched between the source / drain regions, the silicon oxide film is formed again as an insulating film.
A silicon oxide film 5 of about 0 ° and a silicon nitride film 6 of about 200 ° are formed. The silicon nitride film 6 is effective for preventing contamination on the insulating film surface and stabilizing the state of the interface between silicon and SiO2.

Next, as shown in FIG. 1C, a gate electrode 7 made of an Al--Si alloy is selectively formed between the source and the drain.
To form

Next, as shown in FIG. 1D, ³¹ P ⁺ ions are implanted using the gate electrode 7 as a mask to form a low concentration layer. This ion implantation is divided into two times, and the first is performed so that the concentration peak is at a position about 3000 ° deeper than the surface of the silicon substrate to form a low concentration impurity layer 9.
In the second step, the low concentration impurity layer 8 is formed by implantation so that the concentration peak on the surface of the silicon substrate comes. The two low-concentration impurity layers thus formed reduce the high electric field applied between the drain and the source, and
This is effective for preventing the depletion of the interface of the low concentration layer and forming an electrically stable low concentration impurity layer.

Next, as shown in FIG.
Forming a Kabagurasu 10 made of SiO2 film containing a low concentration of ³¹ P ⁺ of 0 Å. Thereafter, a furnace treatment at 500 ° C. is performed to activate the low concentration impurity layers 8 and 9. The cover glass 10 not only prevents the characteristics of the semiconductor device from fluctuating due to external contamination, but also forms the gate electrode layer 7 by furnace treatment at 500 ° C.
The recrystallization of i is promoted, and Si becomes Al-Si and SiO2
This has the effect of suppressing the protrusion at the interface with the substrate. It is effective to increase the film thickness within a range that does not cause cracks in the film due to thermal stress due to the furnace treatment.

Finally, as shown in FIG. 1F, a cover glass 11 having a film thickness required for reliability is formed, and a semiconductor device comprising a MOS transistor with a high breakdown voltage is manufactured.

Embodiment 2 FIG. 2 shows a P-channel MOS using an N-type conductor substrate.
This is a method for manufacturing a transistor. In the first embodiment, the types of the conductors are all opposite, the source and the drain are formed once by ¹¹ B ⁺ ion implantation, and the low concentration impurity layers 8 and 9 are formed by ¹¹ B ⁺ ion implantation. Except for this, a semiconductor device including a high-voltage MOS transistor is manufactured in the same manner as in the first embodiment.

Here, 21 is an N-type silicon substrate, 23 is a high concentration impurity layer, 24 and 25 are silicon oxide films, 26
Is a silicon nitride film, 27 is a gate electrode layer, 28 and 29
Is a low concentration impurity layer, and 30 and 31 are cover glasses.

Each of the semiconductor devices obtained in Examples 1 and 2 has a high withstand voltage of 20 to 30 V and a high reliability.

[0038]

According to the present invention, there is provided a semiconductor device manufacturing method capable of manufacturing a semiconductor device by manufacturing a high-withstand-voltage MOS transistor having achieved miniaturization and high-speed processing in a simple process. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a manufacturing process of a semiconductor device manufactured according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process of the semiconductor device manufactured according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Low concentration impurity layer 3 High concentration impurity layer 4 Silicon oxide film 5 Silicon oxide film 6 Silicon nitride film 7 Gate electrode layer 8 Low concentration impurity layer 9 Low concentration impurity layer 10 Cover glass 11 Cover glass

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Katsuyama Katsu 22-22, Nagaikecho, Abeno-ku, Osaka City Inside Sharpe Corporation (72) Inventor Yusaku Kubo 22-22, Nagaikecho, Abeno-ku, Osaka City Inside Sharpe Corporation ( 72) Inventor Noriyuki Nagai 22-22 Nagaikecho, Abeno-ku, Osaka City Inside Sharpe Co., Ltd.

Claims (1)

(57) [Claims] (A) a first heat treatment is performed in a first conductivity type silicon substrate by performing a first ion implantation using a first silicon oxide film patterned on a substrate surface as a mask and performing a first heat treatment; Forming a source and a drain made of a second conductivity type high-concentration impurity layer that is surrounded or not surrounded by the two-conductivity type low-concentration impurity layer; A region between the source and the drain of the oxide film and the first silicon oxide film is removed, and a second silicon oxide film and a first silicon nitride film are sequentially stacked on the removed surface to form a gate insulating film. Forming an Al-based metal gate electrode layer in the region; and (c) performing second ion implantation into the first conductivity type silicon substrate using the Al-based metal gate electrode layer as a mask to cover the substrate with an insulating film. After Al-based gold A second heat treatment is performed at a temperature at which the metal can be recrystallized, thereby forming a second conductivity type low concentration impurity layer adjacent to the source and drain at a predetermined depth and achieving self-alignment with the Al-based metal gate electrode layer. A method of manufacturing a semiconductor device, comprising: manufacturing a semiconductor device having a high withstand voltage through the steps.