JP2631766B2 - Gate pulse generation circuit of ultrasonic measurement equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate pulse generation circuit of an ultrasonic measuring device, and more specifically, it is possible to accurately and easily set a gate pulse generation timing and its pulse width. The present invention relates to a gate pulse generating circuit of an ultrasonic measuring apparatus in which jitter is hardly generated.

[Related Art] An ultrasonic flaw detector, which is one of the ultrasonic measurement apparatuses, is configured such that a gate can be applied at an arbitrary position of an echo reception signal (or a video signal or an RF signal).
A gate is applied to the defect echo of the echo reception signal, a peak level or the like is obtained for the extracted echo reception signal, and the quality of the defect is determined based on the magnitude of the value.

In this case, in order to apply a gate to an arbitrary position of the echo reception signal, it is necessary to generate a gate pulse at an arbitrary timing. FIG. 3 is an explanatory diagram of the relationship between an A-scope image and the timing of gate pulse generation in defect measurement for explaining the principle of gate pulse generation.

In FIG. 3, reference numeral 30 denotes an A-scope image obtained by the water immersion reflection method, where T is a transmission wave, S is a surface echo, F is a defect echo, and B is a bottom echo. Reference numeral 33 denotes a synchronization signal generated in response to the periodic measurement, which drives a pulser at the trailing edge (rising edge) of the signal to output a transmission pulse. The transmission pulse signal is a transmission wave T in the echo reception signal 30. Appears as.

Reference numeral 34 denotes a delay trigger pulse having a pulse width corresponding to a predetermined set time, and is generated starting from the leading edge (falling edge) of the synchronization signal 33.

A front echo detection pulse 35 is a flip-flop output set at the leading edge of the synchronization signal 33, a comparator output receiving the echo reception signal 30, and a delay trigger pulse 34.
Is generated as a logical product output with the time when is lost.

A gate position pulse 36 is generated as a pulse having a pulse width corresponding to a set time, starting from the surface echo detection pulse 35.

Reference numeral 37 denotes a so-called gate pulse (gate width pulse) which is generated starting from the trailing edge (falling edge) of the gate position pulse 36 and has a pulse width corresponding to a set time.

As described above, the gate width pulse 37 is generated with a set width at a set time according to the generation of the synchronization signal 33 and in synchronization with the generation timing of the surface echo S.

Generation of a gate pulse by such a method is generally called a surface echo synchronous gate mode,
Since the gate is applied based on the surface echo S, there is a characteristic that the gate position from the surface echo S does not change even when the distance between the probe and the subject (referred to as a water distance) changes.

The delay trigger pulse 34 is a pulse used as a means for detecting the surface echo S, and this pulse is LOW.
During the period of the level (hereinafter “L”), the surface echo S is not detected. This suppresses the detection of unnecessary signals until the detection of the surface echo S.

On the other hand, there is another method called a main synchronous gate mode in which a gate signal is applied.
Is a method of generating a gate pulse on the basis of. That is, the gate position pulse 36 is generated starting from the leading edge (falling edge) of the synchronization signal 33, and the gate width pulse 37 is generated starting from the trailing edge of the gate position pulse 36 as described above.

The above two gate modes can be selected. The delay trigger pulse 34, the gate position pulse
36, the value of the gate width pulse 37 depends on the ultrasonic measurement device because it is not specified in the standard, etc., but as an example, the delay trigger pulse is 0.5 to 400 μs, and the gate position pulse is , 0.1-300μ
s, the gate width pulse is 0.1 to 800 μs.

[Problem to be Solved] In the generation of a gate pulse in the surface echo synchronization mode, normally, an echo reception signal is compared with a predetermined threshold voltage, and a signal exceeding the threshold is obtained as an output of a comparator. This output is synchronized with the clock pulse and generated in synchronization with the timing of the clock pulse. On the other hand, the surface echo S is input asynchronously to a clock pulse for counting time.

Therefore, the surface echo S is synchronized with the clock pulse.
Is generated, there is a problem that a jitter of one clock pulse period is generated corresponding to the measurement period. Also, the start timing of the gate pulse does not change even if the generation timing of the surface echo S changes within one cycle of one clock, so that the position of the gate pulse is generated corresponding to the position of the surface echo S. Therefore, a gate pulse cannot be generated at an accurate position.

In order to solve such a problem, the applicant has proposed a clock generation circuit for generating a reference clock for time measurement in accordance with surface echo detection, and a first circuit for counting the clock.
And the counters are simultaneously operated to measure the generation timing of the gate pulse.
A gate pulse generating circuit that does not cause jitter by simultaneously operating and measuring the counter of the present invention has been proposed and filed as Japanese Patent Application No. 2-63358.

When a gate pulse is generated by such a gate pulse generation circuit, the set time width and generation timing can be set for each cycle of the reference clock, and can be increased or decreased. But,
If the clock cycle is shortened to improve the time accuracy, there is a disadvantage that stable operation cannot be performed due to the operation speed of the counter and its control circuit. To make these circuits operate stably, it is not desirable to increase the clock speed.

On the other hand, to analyze the ultrasonic reception signal in ultrasonic measurement, 10
Since it is necessary to analyze RF signals of 0 MHz or more, it is required to generate a clock with a period of 10 msec or less, and in order to perform more accurate analysis, it is necessary to increase the time accuracy of the gate pulse, This requires the generation of a clock with a shorter period.

SUMMARY OF THE INVENTION The present invention addresses the above-mentioned demands and solves the above-mentioned problems of the prior art. The present invention suppresses the occurrence of jitter and achieves highly accurate timing and width without increasing the clock generation speed. It is an object of the present invention to provide a gate pulse generation circuit of an ultrasonic measurement device capable of generating a gate pulse by using the same.

[Means for Solving the Problems] To achieve the above object, a gate pulse generating circuit according to the present invention comprises a clock generating circuit for generating a clock at a constant cycle, and a surface echo based on the clock cycle. First data indicating a period from detection to generation of a gate pulse is set, and a first counter that counts a clock for the first data and a period corresponding to the pulse width of the gate pulse with reference to the clock cycle are indicated. A second counter for setting the second data and counting the clock for the second data; a second counter for setting the data from outside and determining the delay time according to the set data; A delay circuit for receiving at least one of the count end signals and delaying and outputting the signal; a first counter and a clock in response to detection of a surface echo; A control circuit that operates the lock generation circuit and operates the second counter and the clock generation circuit in response to the end of the count of the first counter or in response to the end signal of the first counter delayed by the delay circuit A gate pulse is generated according to the operation of the second counter, and the time until the operation of the second counter or the trailing edge of the gate pulse is set within the range of time shorter than the clock cycle. The adjustment is performed by delaying the count end signal of the first or second counter in accordance with the data set from (1) to (4).

[Operation] As described above, the counter for counting the period from the detection of the surface echo to the generation of the gate pulse and the counter for counting the period corresponding to the pulse width of the generated gate pulse are two.
Two counters are provided, and these counters and the clock generation circuit are operated at the same time in response to surface echo detection to control time counting. Be started. Further, the pulse width counter and the clock generation circuit are operated again when the count of the gate pulse generation for the gate width is completed. Freed from sex.

In addition, a delay circuit is inserted so that the timing or output width of the gate pulse can be adjusted with a time width equal to or less than the period of the reference clock for time measurement, so that it is generated with higher accuracy than the clock used as the reference for time measurement. Timing and pulse width can be selected. Therefore, it is possible to generate a gate pulse with high precision timing and pulse width by stable circuit operation with almost no jitter without increasing the clock cycle so much.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment to which a gate pulse generating circuit of an ultrasonic measuring apparatus according to the present invention is applied, and FIG.
FIG. 3 is a block diagram of the clock generation circuit.

In FIG. 1, latch circuits 1, 2, and 3 are
A circuit for latching digital value data for setting a time corresponding to each pulse width of the delay trigger pulse 34, the gate position pulse 36, and the gate width pulse 37 shown in the figure, and these data are input to the input terminals 1a and 2a, respectively. , 3a. The latched time count data of each pulse width is transmitted to the preset counters 4, 5, and 6 provided for the respective latch circuits in accordance with the output enable signal, in which the upper n bits (n is a positive integer) are provided. Is transmitted as input data of
The bit is sent to the data selector 9a, which will be described later, and determines a short time width equal to or shorter than the clock cycle. That is, the data selector 9a and the delay line 9b described later constitute a specific example of the delay circuit in the present invention. Further, a status counter 9 and a status decoder 10, which will be described later, constitute a control circuit according to the present invention.

Data loading of each pulse width set in the preset counters 4, 5, and 6 is performed by a load signal 19, and the load signal 19 is generated by an initial setting signal generating circuit 22.

The initial setting signal generating circuit 22 is constituted by a one-shot circuit, and outputs the gate width pulse of the immediately preceding measurement section to the output terminal 29.
Triggered simultaneously by this gate width pulse, each counter loads data, and the latch circuit 7 has a pulse width LOW corresponding to the period during which data is latched.
A level (hereinafter “L”) pulse signal is generated as the load signal 19. Then, this signal initializes each circuit in accordance with the next measurement cycle. Here, the gate width pulse generated at the output terminal 29 corresponds to the gate width pulse 37 (see FIG. 3), and is a pulse obtained by inverting the pulse (described later).

The status counter 9 is a preset counter that indicates the current control status, and is a four-digit value on the input side (the first, third, and fourth digits are set to “0” by the grounded signal lines 27 and 28). In this case, only the second digit is connected to the mode selection switch 24, and “0” or “1” can be selected. Therefore, this preset value is determined according to the mode selection. And
The status of which of the delay trigger pulse 34, the gate position pulse 36, and the gate width pulse 37 to count is determined based on the two bits of output information (QA, QB).

The status decoder 10 receives and decodes the 2-bit status data from "00" to "01", "10", and "11", and outputs 4-digit negative logic output "1110" to "110".
Either 1 "," 1011 ", or" 0111 "is generated. One of the preset counters 4, 5, and 6 is selected and operated according to the output value, or a negative logic AND gate is operated. Two
Control one. The status decoder 10 outputs an output enable signal to the latch circuit corresponding to the preset counter selected from any of the latch circuits 1, 2, and 3 simultaneously with the selection of any one of the preset counters 4, 5, and 6. , And the lower order m bits, for example, about 3 bits, are transmitted to the data selector 9a. Further, when the counter is selected, the clock generation circuit 11 is also operated at the same time, and the data for the preset time data is counted by the selected counter. Note that the upper-order n-bit data has already been loaded into the preset counter before this by the load signal 19.

The data selector 9a receives the output from the OR gate 20, delays the output by the delay line 9b, receives a plurality of outputs with different delay times from the delay line 9b, and latches one of the outputs. The data is selected according to the output data of one of the lower bits of the circuits 1, 2, and 3 and sent to the status counter 9. Here, the plurality of delay times given to the signal output by the delay line 9b are in a range of time shorter than the clock cycle of the clock generation circuit 11, and for example, a time in a range of about several nsec to about 35 nsec is substantially equal. This is a delay time obtained by dividing and sequentially adding each divided time.

Therefore, by selecting the input of the data selector 9a, the time when the status counter 9 shifts to the next status is delayed at the same time based on the output timing of the OR gate 20 or by the time corresponding to the delay output of the delay line 9b. Can be adjusted. The input of the data selector 9a in this case is selected based on the value of the lower digit stored in the latch circuits 1, 2, and 3.

The overall operation is as follows. First, the mode selection switch 24 is set at the second digit on the input side of the status counter 9.
Is supplied. Thus, the state of the surface echo periodic gate mode or the main synchronous gate mode is given as a preset value of the counter. That is, when the terminal 24a is selected by the mode selection switch 24 and the surface echo synchronous gate mode is set, the input value of the second digit of the status counter 9 becomes "0" and the other four inputs become "0". Since it is set to "0", the initial value of this counter is all "0". As a result, the input lines 27 and 28 of the status counter 9 all become "L", and the output QA of the first digit and the output QB of the second digit both become "L".

The second least significant digit of the status counter 9 is the initial value “0”.
The operation in the surface echo synchronization gate mode starting with "0" is synchronized with the transmission pulse drive signal of the pulser, and a synchronization signal (corresponding to the synchronization signal 33 in FIG. 3) indicating the start of the measurement period is input to the input terminal 7a of the latch circuit 7. The latch circuit 7 is activated by receiving the load signal 19 from the initial setting signal generating circuit 22. At this time, the input signal is changed to "L". The output of the latch circuit 7 is supplied to the status decoder 10 as an enable signal, thereby activating the status decoder 10. At this time, the outputs QA and QB of the status counter 9 become Both are “L” (or “0”
0 "), the output Y _{0 of the} status decoder 10
(Signal 16) becomes “L” (output is “1110”), which is applied to the preset counter 4 and the latch circuit 1, and the preset counter 4 becomes active. "L" output Y ₀ is applied to the NOR gate 23 simultaneously, the output signal 23a is "L"
As a result, the clock generation circuit 11 becomes active and generates a clock pulse 11a. As a result, the preset value of the upper n bits loaded in the preset counter 4 is decremented by the clock pulse 11a, and the clock pulse 11a is counted for the set delay time.
At the end of this time counting, the output of the preset counter 4 is applied to the OR gate 20 of negative logic. At this time, the preset counter 4 counts according to the set delay trigger pulse data, and the output 13 falls at the count of the last clock pulse 11a at the end of the count, which is the count of the status counter 9. It becomes a clock pulse that recommends the status.

That is, the output of the OR gate 20 is output to the data selector 9a via the delay line 9b or to the data selector 9a immediately after, and the signal selected by the data selector 9a is supplied to the clock terminal of the status counter 9 via the data selector 9a. CK). Therefore, the status counter 9 updates its status from "00" to "01" after the delay adjustment by the time according to the selection of the data selector 9a, and outputs QA and QB thereof become "H" and "L", respectively. " As a result, the output signal Y ₁ (signal 12) of the status decoder 10 changes to “L” (the output is “1101”). Whether the data selector 9a selects the delay time directly or which time is determined according to the contents of the lower three bits supplied from the latch circuit 1 at this time.

The “L” signal of the output signal Y ₁ of the status decoder 10 is
The gate signal is applied to the negative logic AND gate 21 and converted to a gate signal. Here, one of the inputs of the AND gate 21 is connected to the terminal 24a of the mode selection switch 24, to which an “L” signal is applied. Then, the AND gate 21 opens with the “L” of the output signal Y ₁ and receives the output of the comparator 8.

The comparator 8 is a detection circuit for the surface echo S. When the surface echo S is applied to the input terminal 8a of the comparator 8, the comparator 8 detects the surface echo reception signal based on the threshold and detects the detection signal " L "occurs. This is input as a clock pulse to the status counter 9 via the AND gate 21 and the OR gate 20 in negative logic.

As a result, the status counter 9 indicates “01” at this time.
To “10”, and the outputs QA, QB are “L”,
It becomes “H”. In response, the output of the status decoder 10
Y ₂ (signal 17) becomes “L”, which is added to the preset counter 5 and the latch circuit 2, and the upper digit n bits from the latch circuit 2 are set in the preset counter 5;
And this becomes active. At this time, at the same time, the lower three bits of the latch circuit 2 are sent to the data selector 9a, thereby selecting the next time for delay adjustment.

Then, similarly to the above, the output signal 23a of the NOR gate 23 becomes "H", the clock generation circuit 11 operates, and the value of the preset counter 5 is decremented by the clock pulse 11a in synchronization with the input of the surface echo S. The countdown is performed by the set value of the gate position pulse. At the count of the last clock pulse 11a at the end of this count, the output 14 of the preset count 5 falls,
In the same manner as above, the signal selected thereby is applied as a clock pulse to the status counter 9 via the delay line 9b and the data selector 9a (or the direct data selector 9a).

As a result, after the status update time of the status of the status counter 9 is adjusted according to the lower three bits of the latch circuit 2, the status counter 9 becomes "11". The outputs QA and QB become "H" and "H", respectively. In response, the output Y ₃ (signal 18) of the status decoder 10 becomes “L”
From the latch circuit 3 to the upper n bits and lower 3 bits.
The bit is output, and the preset counter 6 is activated. The output Y ₃ simultaneously, the a is an operation signal of the clock generating circuit 11 as well, added to further it output terminal 29. At the same time, the lower three bits of the latch circuit 3 are sent to the data selector 9a, and the time for the next delay adjustment (corresponding to the adjustment of the pulse width of the gate pulse) is selected.

The preset value of the upper n bits corresponding to the pulse width generated by the preset counter 6 is decremented by the clock pulse 11a, the count is performed according to the gate width pulse data, and the count of the last clock pulse 11a at the end of the count is performed. Output 1 of preset count 6
5 falls. As a result, the delay line 9b and the data selector 9a (or the direct data
The signal thus selected is applied to the input of the status decoder 10 via a).

As a result, after the status state update time of the status counter 9 is adjusted in accordance with the lower three bits of the latch circuit 3, the status counter 9 becomes "00" and its outputs QA and QB become "L". , “H”. The output Y ₃ (signal 18) returns from “L” to “H”. Therefore, the third
A gate width pulse obtained by inverting the gate width pulse 37 shown in the figure and having the time width set in the preset count 6 + the adjustment time (delay time or no delay time) selected by the data selector 9a is extracted from the output terminal 29.

In this case, the status counter 9 becomes "00" and this output is added to the status decoder 10.
Since the status decoder 10 will be Day disabled in response to operation of the initial setting signal generating circuit 22 as will be described later this time, the output of the Y ₀ is not generated.

That is, the initial setting signal generating circuit 22 in the change of "H" to "L" output Y ₃ is triggered, the load signal 19 which is a predetermined time width "L" is generated. This load signal 19 is applied to each load terminal of each of the preset counters 4, 5, 6 and the latch circuit 7, and the status counter 9, whereby an initial value is set in each counter. The status counter 9 is thereby set to the initial value "00" of the surface echo synchronization gate mode, and the same operation as described above is repeated. Further, the latch circuit 7 is cleared by the load signal 19, the output signal 7b returns to "H", and enters the next data load state. As a result, the status decoder 10 is disabled. As a result, the status decoder 10 does not operate until the next synchronization signal is applied to its input terminal 7a.

In the above operation, the delay trigger pulse is selected by selecting the time of the delay line 9b by the data selector 9a.
The pulse width of the pulse 34 and the pulse width of the gate position pulse 36 and the pulse width of the gate width pulse 37 from the point of time when the surface echo is detected can be extended by a unit equal to or less than the clock cycle, and finely adjusted.

FIG. 2 shows an example of the clock generation circuit 11. First, when the input of the input terminal 11b is "L", the output terminal 25a of the NAND gate 25 becomes "H", an output delayed by 20ns is applied to the input terminal 25b by the delay line 26, and after 20ns, the output becomes "H". "become. Inverter 26a
Generates the clock pulse 11a at the output terminal 11c by inverting the output of the output terminal 25a, and becomes "L" since the output terminal 25a is maintained at "H".

Next, when the output terminal 11b is set to “H”, since the input terminal 25b is “H”, the output 25a of the NAND gate 25 becomes “L”, and the input terminal 25b is set to “L” with a delay of 20 ns by the delay line 26. L ". Then, the output terminal 25a returns to "H". This 2
The “H” signal of 5a appears again at the input terminal 25b with a delay of 20 ns,
The output terminal 25a becomes "L". By this repetition, a clock pulse of about 40 ns is output to 11a.

Next, when the input terminal 11b becomes “L”, the input terminal 25a becomes “H”.
As a result, the output terminal 11c becomes "L", and the output of the clock pulse 11a stops. This periodic clock generation circuit 11
Thereby, the clock pulse 11a which starts in synchronization with the signal of the input terminal 11b can be obtained.

When the clock generation circuit 11 is configured by such an oscillation circuit, the cycle of the clock pulse is a relatively short cycle of 40 ns, but this cycle is longer than the switching operation period of the output of the status decoder 10. In this case, since the clock generation circuit 11 is continuously activated, clock pulses are continuously generated. However, if the cycle of the clock pulse is further shortened, the output switching operation period of the status decoder 10 becomes longer, so that the generation of the clock pulse is temporarily stopped and restarted accordingly. Therefore, in such a control circuit (control circuit including the status counter 9 and the status decoder 10), the more effective the shorter the cycle of the clock pulse, such as 5 ns or less.

Basically, the present invention stops the generation of the clock pulse in accordance with the end of the count of each of the preset counters 4, 5, and 6, and simultaneously starts the generation in response to the activation of these counters. When the cycle of the clock pulse 11a is long as described above, the clock pulse 11a is continuously output from the clock generation circuit 11 except for the time point at which the surface echo S is detected. Even with this, the effect of the present invention is achieved. However, even if the clock cycle is long, in order to stop the clock generation at the same time when the counter count ends, the outputs of the preset counters 4, 5, and 6 should be directly applied to the clock generation circuit 11 as an operation stop signal. do it.

Next, the main synchronous gate mode in which the mode selection switch 24 is selected on the terminal 24b side will be described.

The input terminal of the signal 27 among the input terminals of the status counter 9 becomes “H” by the above selection, and the input terminals of the grounded input signal 29 all become “L”. Therefore, the initial value set in the status counter 9 is "10",
The output QA of the first digit is "L" and the output QB of the second digit is "H".

When a synchronization signal is input to the input terminal 7a in this state, the output Y ₂ (signal 17) of the status decoder 10 becomes “L”,
First, the preset counter 5 operates to count the clock pulse 11a until the gate width pulse is generated. In this case, the period from the time of generation of the synchronization signal is set in the preset counter 5 as the initial value of the count data. Then, the subsequent generation of the gate width pulse is performed in the same manner as in the case of the operation in the surface echo synchronous mode, with the preset counter 6 being selected and operated.

As described above, in the embodiment, the setting data of the counter and the delay time selection data of the data selector are divided and assigned to the upper bit and the lower bit of the data set in the latch circuit. Alternatively, the latch circuit on the counter side and the latch circuit on the data selector side may be separated, and data may be set in different latch circuits. In this case, it is not necessary to adjust both the time until the gate pulse is generated and the gate pulse width.
Only the time until the generation of the gate pulse or only the generation timing of the gate pulse may be adjusted by the delay line.

In the embodiment, the control signal for operating the preset counter and the clock generation circuit by selecting the preset counter and the clock generation circuit by the combination of the status counter and the status decoder is generated. However, this is a control circuit composed of other circuits. Of course, it is possible.

[Effects of the Invention] As can be understood from the above description, according to the present invention, a counter that counts a period from detection of a surface echo to generation of a gate pulse and a counter that counts a period corresponding to the pulse width of a generated gate pulse. Are controlled so that the counter and the clock generation circuit are operated simultaneously to count the time in response to the detection of the surface echo. Time counting starts. Further, the pulse width counter and the clock generation circuit are operated again when the count of the gate pulse generation for the gate width is completed. Freed from sex.

In addition, since a delay circuit is inserted to adjust the generation timing or the output width of the gate pulse with a time width equal to or less than the period of the reference clock for time measurement, the accuracy is higher than the clock used as the reference for time measurement. Generation timing and pulse width can be selected. Therefore, it is possible to generate a gate pulse with high precision timing and pulse width by stable circuit operation with almost no jitter without increasing the clock cycle so much.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment to which a gate pulse generating circuit of an ultrasonic measuring apparatus according to the present invention is applied, FIG. 2 is a block diagram of a clock generating circuit thereof, and FIG. FIG. 4 is an explanatory diagram of typical gate pulse generation timing. 1,2,3,7 ... Latch circuit, 4,5,6 ... Preset counter, 7 ... Latch circuit, 8 ... Comparator, 9 ... Status counter, 10 ... Status decoder, 11 ...
Clock generation circuit, 22... Initial value setting signal generation circuit.

Claims (3)

(57) [Claims] 1. A clock generating circuit for generating a clock at a constant cycle, and first data indicating a period from detection of a surface echo to generation of a gate pulse based on the cycle of the clock are set, and the clock is set to a first data. And a second data indicating a period corresponding to the pulse width of the gate pulse with reference to the cycle of the clock, and a second counter for counting the clock by the second data. And a delay in which data is set from the outside and a delay time is determined according to the set data, and a count end signal of at least one of the first and second counters is received and delayed and output. Operating the first counter and the clock generation circuit in response to the detection of the surface echo, and counting the first counter. A control circuit for operating the second counter and the clock generation circuit in response to termination or in response to a termination signal of the first counter delayed by the delay circuit; The gate pulse is generated in accordance with an operation, and the time until the operation of the second counter or the trailing edge of the gate pulse is set in accordance with the data set from the outside in a range of time shorter than the cycle of the clock. A gate pulse generating circuit for an ultrasonic measuring device, wherein the adjustment is performed by delaying a count end signal of the first or second counter. 2. The externally set data is performed together with the first data or the second data,
2. The gate pulse generation circuit according to claim 1, wherein the first or second data is set to an upper digit, and the data set from the outside is set to a lower digit. 3. The control circuit according to claim 1, wherein a period of a clock is longer than a period after the count of the first counter is completed and a clock generator is operated next, and the control circuit responds to the detection of a surface echo by detecting the surface echo. Operating the first counter and the clock generation circuit, adjusting the time directly by the delay circuit in response to the end of the count of the first counter or adjusting the time by the delay circuit, operating the second counter, 3. The ultrasonic measurement apparatus according to claim 1, wherein when the second counter is directly operated in response to the end of the count, the count end signal of the second counter is delayed by the delay circuit. Gate pulse generation circuit.