JP2629465B2 - Chip type electric double layer capacitor - Google Patents
Chip type electric double layer capacitorInfo
- Publication number
- JP2629465B2 JP2629465B2 JP3040411A JP4041191A JP2629465B2 JP 2629465 B2 JP2629465 B2 JP 2629465B2 JP 3040411 A JP3040411 A JP 3040411A JP 4041191 A JP4041191 A JP 4041191A JP 2629465 B2 JP2629465 B2 JP 2629465B2
- Authority
- JP
- Japan
- Prior art keywords
- electric double
- layer capacitor
- electrode
- element laminate
- holding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/13—Energy storage using capacitors
Landscapes
- Electric Double-Layer Capacitors Or The Like (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明はチップ型電気二重層コン
デンサに関し、特に表面実装に対応する電気二重層コン
デンサのケーシング構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip-type electric double-layer capacitor, and more particularly to a casing structure of an electric double-layer capacitor for surface mounting.
【0002】[0002]
【従来の技術】近年、ヘッドホンステレオ,コードレス
電話等携帯用の電子機器の小形化,薄型化には著しいも
のがある。これらの電子機器に実装される電気二重層コ
ンデンサも他の電子部品と同様に小形化,薄形化、さら
には表面実装化への要求が頻繁化しつつある。従来、こ
の種の電気二重層コンデンサとしては、大容量のコンデ
ンサを得る手段の一つとして、米国特許第353696
3号明細書にて開示されているように、カーボン粉末と
電解液とを接触させて電気二重層を発生させることを利
用したものがある。図7は電気二重層コンデンサ素子
(以下素子と称す)の断面図である。図7において、9
は電子伝導性でかつイオン不浸透性の導電性セパレー
タ、10は粉末活性炭と電解質溶液からなるカーボンペ
ースト電極、11はカーボンペースト電極間の導通を防
止するために設けたイオン透過性で、かつ非電子伝導性
を有する多孔性セパレータ、9はカーボンペースト電極
を保持し、かつ外界から遮断するために設けた非導電性
ガスケットである。2. Description of the Related Art In recent years, there has been a remarkable reduction in the size and thickness of portable electronic devices such as headphone stereos and cordless telephones. Electric double-layer capacitors mounted on these electronic devices are also increasingly required to be smaller, thinner, and moreover surface-mounted, like other electronic components. Conventionally, as this type of electric double-layer capacitor, US Pat.
As disclosed in the specification of Japanese Patent No. 3, there is an apparatus utilizing contact between carbon powder and an electrolytic solution to generate an electric double layer. FIG. 7 is a sectional view of an electric double layer capacitor element (hereinafter, referred to as an element). In FIG. 7, 9
Is a conductive separator that is electron-conductive and ion-impermeable, 10 is a carbon paste electrode made of powdered activated carbon and an electrolyte solution, 11 is an ion-permeable and non-conductive, which is provided to prevent conduction between the carbon paste electrodes. The porous separator 9 having electron conductivity is a non-conductive gasket provided for holding the carbon paste electrode and shielding it from the outside.
【0003】図6は従来のチップ型電気二重層コンデン
サの断面図である。図6において、6aは素子6を積層
した素子積層体、4および5はそれぞれリード端子部4
aおよび5aを有する第1の電極板と第2の電極板、2
は素子積層体を加圧・保持するための保持部2aを有す
る挾持体、3は第1および第2の電極板と挾持体とを絶
縁するための絶縁層、1は外装のためのエポキシ樹脂等
の絶縁樹脂である。従来の電気二重層コンデンサは挾持
体2にて素子積層体6aを加圧・保持した後、素子積層
体6aの側面での電気的短絡を防ぐために、エポキシ樹
脂の溶液中に浸漬させ、その後恒温槽内で加熱硬化させ
て外装を行なっていた。FIG. 6 is a sectional view of a conventional chip type electric double layer capacitor. In FIG. 6, 6a is an element laminate in which the element 6 is laminated, and 4 and 5 are the lead terminal portions 4 respectively.
a and 5a having a first electrode plate and a second electrode plate,
Is a holding body having a holding portion 2a for pressing and holding the element laminate, 3 is an insulating layer for insulating the first and second electrode plates and the holding body, and 1 is an epoxy resin for exterior. And the like. In the conventional electric double layer capacitor, after the element laminate 6a is pressed and held by the holding body 2, it is immersed in an epoxy resin solution in order to prevent an electric short circuit on the side surface of the element laminate 6a, and then is kept at a constant temperature. It was heated and cured in the tank to provide the exterior.
【0004】[0004]
【発明が解決しようとする課題】この従来のチップ型電
気二重層コンデンサは、断面コの字型の挾持体に第1の
電極板,素子積層体,第2の電極板を所定の位置に配置
し、第1の電極板を介して素子積層体を加圧した状態で
挾持体の先端を内側に略直角に折り曲げて保持部を形成
するため、およびエポキシ樹脂の溶液中に浸漬した後、
加熱硬化させるという外装方法のため、下記の問題点が
あった。In this conventional chip type electric double layer capacitor, a first electrode plate, an element laminate, and a second electrode plate are arranged at predetermined positions on a holding member having a U-shaped cross section. Then, in order to form a holding portion by bending the tip of the holding body inward at a substantially right angle in a state where the element laminate is pressed through the first electrode plate, and immersing the holding body in an epoxy resin solution,
Due to the exterior method of heat curing, there are the following problems.
【0005】(1)挾持体の保持部は、成形後材料のス
プリングバックおよび素子積層体の圧縮応力により、図
6(a)に示す通り矢印方向に戻るため、素子積層体へ
の保持圧力の低下による電気二重層コンデンサの等価直
列抵抗の増大および外形寸法が増大する。(1) The holding portion of the holding body returns in the direction of the arrow as shown in FIG. 6 (a) due to the springback of the molded material and the compressive stress of the element laminate. Due to the decrease, the equivalent series resistance of the electric double layer capacitor increases and the external dimensions increase.
【0006】(2)付着樹脂量が多くなると外径寸法が
増大すると同時に寸法バラツキが増大する。(2) When the amount of the adhered resin increases, the outer diameter dimension increases, and at the same time, the dimensional variation increases.
【0007】(3)外装面が凸凹しているため、真空吸
着法によるプリント配線板への自動搭載が不可能であ
る。(3) Since the exterior surface is uneven, automatic mounting on a printed wiring board by a vacuum suction method is impossible.
【0008】(4)2つのリード端子部が同一方向から
突出しているため、固着安定性が悪く、プリント配線板
へのはんだ付け後に振動等が加わった場合、プリント配
線板から離脱するものがある。(4) Since the two lead terminal portions protrude from the same direction, the fixing stability is poor, and when vibration or the like is applied after soldering to the printed wiring board, there is a case where the lead terminal detaches from the printed wiring board. .
【0009】本発明の目的は、挾持体の保持部が成形
後、材料のスプリングバックおよび積層体の圧縮応力に
より戻りを生じることがなく、またコンデンサの等価直
列抵抗を小さくできかつ外形寸法も小さくなり、また樹
脂成形においては素子積層体への熱影響を小さくでき、
かつ外形寸法を小さく、寸法のバラツキも小さく、かつ
表面を平滑にでき自動搭載を可能とし、その上配線板へ
の固着を安定化できるチップ型電気二重層コンデンサを
提供することにある。SUMMARY OF THE INVENTION It is an object of the present invention to prevent the holding portion of the holding body from returning due to the springback of the material and the compressive stress of the laminated body after molding, to reduce the equivalent series resistance of the capacitor, and to reduce the external dimensions. In addition, in resin molding, the thermal effect on the element laminate can be reduced,
It is another object of the present invention to provide a chip-type electric double-layer capacitor capable of reducing external dimensions, minimizing dimensional variations, smoothing the surface, enabling automatic mounting, and stabilizing fixation to a wiring board.
【0010】[0010]
【課題を解決するための手段】本発明のチップ型電気二
重層コンデンサは、円筒形の電気二重層コンデンサの素
子積層体の積層方向の上面にリード端子部を突出させた
電極板、下面にリード端子部を突出させた電極部と素子
積層体を加圧保持する保持部とを一体化した挾持体の電
極部を配置し、挾持体が電極部と、該電極部と略直角
で、略平行に対向する中央に素子積層体との接触を回避
する透孔窓を形成し対向間隔が素子積層体の外径より小
さい2つの下垂部と、下垂部の先端を電極部と略平行に
成形した保持部より成り、保持部により絶縁層および前
記電極板を介して素子積層体を加圧保持し、周囲を絶縁
樹脂の注入によりモールド外装してなることを特徴とす
る。According to the present invention, there is provided a chip-type electric double-layer capacitor comprising an electrode plate having a lead terminal projecting from an upper surface of a cylindrical electric double-layer capacitor in a laminating direction of an element laminate, and a lead from a lower surface. An electrode portion of a holding body in which an electrode portion having a protruding terminal portion and a holding portion for holding the element stack under pressure are arranged, and the holding body is substantially perpendicular to the electrode portion and substantially parallel to the electrode portion A through-hole window for avoiding contact with the element stack is formed at the center opposite to, and two opposing gaps whose opposing intervals are smaller than the outer diameter of the element stack, and the tip of the droop are formed substantially parallel to the electrode section. The device is characterized by comprising a holding portion, the holding portion pressurizing and holding the element laminate through the insulating layer and the electrode plate, and molding the periphery by injection of an insulating resin.
【0011】また、本発明のチップ型電気二重層コンデ
ンサは挾持体の下垂部と保持部との断面方向の投影形状
をT字型,モールド外装する絶縁樹脂を熱可塑性、絶縁
樹脂の注入口を素子積層体の円筒端面側の略中央部とす
ることを特徴とする。The chip type electric double layer capacitor of the present invention has a T-shaped cross-sectional projection between the hanging portion and the holding portion of the holding member, thermoplastic resin for the insulating resin for molding, and injection port for the insulating resin. It is characterized in that it is located substantially at the center on the cylindrical end face side of the element laminate.
【0012】[0012]
【実施例】次に本発明について図面を参照して説明す
る。図1は本発明の第1の実施例の説明図で(a)は奥
側立面図、(b)は下面図、(c)は手前側立面図、
(d)は上面図、(e)は右側面図、(f)はA−A断
面図、(g)はB−B断面図であり、図2は本発明の第
1の実施例の外装前の説明図で(a)は奥側立面図、
(b)は下面図、(c)は手前側立面図、(d)は上面
図、(e)は右側面図である。また図3は本発明の第1
の実施例の外装直前の状態図で、モールド金型にセット
し、電極板を介して素子積層体を矢印方向に加圧した状
態を示す手前側立面図、図4は本発明の第1の実施例の
斜視図で(a)は外装前の組立状態での部品相互の上下
位置関係を示す部品構成図、(b)は外装前の組立状態
図、(c)は外装直前のモールド金型にセットし、電極
板を介して素子積層体を矢印方向に加圧した状態図、
(d)はモールド外装後の状態図、(e)は完成品の状
態図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A and 1B are explanatory views of a first embodiment of the present invention. FIG. 1A is a rear elevation view, FIG. 1B is a bottom view, and FIG. 1C is a front elevation view.
(D) is a top view, (e) is a right side view, (f) is a sectional view taken along line AA, (g) is a sectional view taken along line BB, and FIG. 2 is an exterior of the first embodiment of the present invention. (A) is a front elevational view in the front explanatory view,
(B) is a bottom view, (c) is a front elevation view, (d) is a top view, and (e) is a right side view. FIG. 3 shows the first embodiment of the present invention.
FIG. 4 is a front elevational view showing a state immediately before the exterior of the embodiment of FIG. 5, showing a state in which the element laminate is set in a molding die and an element laminate is pressed in the direction of an arrow via an electrode plate, and FIG. (A) is a component configuration diagram showing a vertical positional relationship between components in an assembled state before the exterior, (b) is an assembly state diagram before the exterior, and (c) is a mold metal just before the exterior. State diagram in which the element stack is pressed in the direction of the arrow through the electrode plate,
(D) is a state diagram after the mold exterior, and (e) is a state diagram of the finished product.
【0013】図1および図2において、まず外径8.4
mm,厚さ0.7mmの素子6を6枚積層し、素子積層
体6aを得る。図2および図4に示す通り、素子積層体
6aは幅2mm,厚さ0.4mm,長さ7mmのリード
端子部2bを突出させた対辺の間隔が9.8mmで6角
形の電極部2cと、電極部2cの対向する2辺から曲げ
点の間隔が8mm弱で電極部2cとが鈍角に成形し、中
央に端部を電極部2c寄りの該曲げ点近傍とする透孔窓
2eを形成した2つの下垂部2dと、下垂部2dの先端
の透孔窓2eの端部直前を下垂部2dより略90°内側
に成形した保持部2aを有する鉄・ニッケル合金にはん
だメッキを施した挾持体2の電極部2cの略中央に配置
する。In FIGS. 1 and 2, first, the outer diameter is 8.4.
Six elements 6 each having a thickness of 0.7 mm and a thickness of 0.7 mm are laminated to obtain an element laminate 6a. As shown in FIGS. 2 and 4, the element laminate 6a has a hexagonal electrode portion 2c having a width of 9.8 mm and a protruding lead terminal portion 2b having a width of 2 mm, a thickness of 0.4 mm and a length of 7 mm. The interval between the bending points from the two opposing sides of the electrode portion 2c is less than 8 mm, and the electrode portion 2c is formed at an obtuse angle, and a through-hole window 2e having an end near the bending point near the electrode portion 2c is formed in the center. An iron / nickel alloy solder-plated having two hanging parts 2d and a holding part 2a formed just inward of the end of the through-hole window 2e at the tip of the hanging part 2d by approximately 90 ° from the hanging part 2d. It is arranged substantially at the center of the electrode portion 2c of the body 2.
【0014】次に、素子積層体6aの上面に幅2mm,
厚さ0.4mm,長さ7mmのリード端子部7aを突出
させた対辺の間隔が9.8mmで6角形の鉄・ニッケル
合金にはんだメッキを施した電極板7をリード端子部7
aの突出方向が挾持体2のリード端子部2bと180°
反対方向となり、且つ挾持体2の電極部2cと電極板7
の6角形の端面とが同一面になるように配置する。その
後、素子積層体6aの上下方向に電極板7を介して約2
0kg/cm2 の圧力を加えた状態で2つの下垂部2d
を電極部2cと略直角に折り曲げ、素子積層体6aへの
圧力を取り除く。尚、素子積層体6aは約20kg/c
m2 の加圧により厚さ3.0mm最大外径9.4mm程
度に変形する。素子積層体6aを保持部2aで加圧保持
する状態において、保持部2aと下垂部2dとは断面方
向の投影形状がT字型となっており、リード端子2b,
7aと平行な中央部を除いては、挾持体2および電極板
7と略同一な形状をしているため、対処の間隔が9.8
mmの6角形で厚さ4.2mmの図5(b)に示す外装
前のチップ型電気二重層コンデンサ(以下半製品と称
す)が得られる。Next, a width of 2 mm,
A lead terminal portion 7a having a thickness of 0.4 mm, a length of 7 mm, and a protruding lead terminal portion 7a having a distance between opposite sides of 9.8 mm and a hexagonal iron-nickel alloy plated with solder is used.
The projection direction of a is 180 ° with the lead terminal portion 2b of the holding body 2.
In the opposite direction, the electrode portion 2c of the holding body 2 and the electrode plate 7
Are arranged so that the end faces of the hexagons are flush with each other. Then, about 2 上下 vertically through the element laminate 6 a via the electrode plate 7.
Two drooping parts 2d under a pressure of 0 kg / cm 2
Is bent substantially at right angles to the electrode portion 2c to remove the pressure on the element laminate 6a. In addition, the element laminate 6a is about 20 kg / c.
It is deformed to a thickness of 3.0 mm and a maximum outer diameter of about 9.4 mm by pressurization of m 2 . In a state in which the element stack 6a is pressed and held by the holding portion 2a, the holding portion 2a and the hanging portion 2d have a T-shaped projection shape in the cross-sectional direction, and the lead terminals 2b,
Except for the central portion parallel to 7a, the holding member 2 and the electrode plate 7 have substantially the same shape, so that the interval between them is 9.8.
A chip-type electric double-layer capacitor (hereinafter, referred to as a semi-finished product) having a hexagonal shape of 4.2 mm and a thickness of 4.2 mm as shown in FIG. 5B is obtained.
【0015】次に、前記半製品を縦10.5mm,横1
0.5mm,厚さ5mmの中空部を有するモールド型に
電極板7側を上にしてセットし、電極部2c,電極板7
を介して各々4個の金型ピン(図示省略)で図3および
図4(c)に示すように矢印方向に20kg/cm2 の
圧力を加えて素子積層体6aを圧縮させ、保持部2aと
電極板7との間に間隔を設け、PPS(ポリフェニレン
サルファド)等の熱可塑性で高耐熱性の絶縁樹脂1を金
型内の前記間隙部を含め全間隙へ電極板7上部中央の絶
縁樹脂注入ゲート1cより注入し成形する。絶縁樹脂注
入ゲート1cは通称ピンポイントゲートと呼ばれるもの
で、モールド成形完了時点の上下の金型が開く際に自動
的に製品側の根本より破断される。また、電極板側穴部
1aおよび挾持体側穴部1bは前記金型ピンの跡であ
り、電極板7を介して素子積層体6aを圧縮させてモー
ルド成形の際に半製品を固定し、前述の保持部2aと電
極板7との間に間隙を設けて絶縁樹脂1を注入し、両者
を絶縁化させると共に電気二重層コンデンサの等価直列
抵抗を低くさせる。以上により、本発明の第1の実施例
のチップ型電気二重コンデンサを得た。Next, the semi-finished product is 10.5 mm long and 1 mm wide.
The electrode plate 7 side is set in a mold having a hollow portion of 0.5 mm and a thickness of 5 mm with the electrode plate 7 side facing up.
As shown in FIGS. 3 and 4 (c), a pressure of 20 kg / cm 2 is applied to each of the four mold pins (not shown) to compress the element laminated body 6a through the holding member 2a. A gap is provided between the electrode plate 7 and a thermoplastic and high heat-resistant insulating resin 1 such as PPS (polyphenylene sulfide). It is injected and molded from the resin injection gate 1c. The insulating resin injection gate 1c is generally called a pin point gate, and is automatically broken from the root on the product side when the upper and lower molds at the time of completion of molding are opened. Further, the electrode plate side hole 1a and the holding body side hole 1b are traces of the mold pins, and the element laminate 6a is compressed via the electrode plate 7 to fix a semi-finished product during molding. A gap is provided between the holding portion 2a and the electrode plate 7 to inject the insulating resin 1 to insulate the two and to reduce the equivalent series resistance of the electric double layer capacitor. Thus, a chip type electric double capacitor according to the first embodiment of the present invention was obtained.
【0016】図5は本発明の第2の実施例を説明するた
めの図面で図1(b)に示す上面図のB−B相当断面図
であり、第1の実施例とはリード端子部7aを除く、保
持部2a側の電極板2全面にポリイミド等の絶縁層3を
予め被覆または載置している点のみ異なる。以上によ
り、保持部2aと電極板7との間隙に絶縁樹脂1が完全
に注入されなくとも、保持部2aと電極板7との絶縁化
を確実にはかることができる。FIG. 5 is a drawing for explaining a second embodiment of the present invention, and is a cross-sectional view corresponding to line BB in the top view shown in FIG. 1 (b). The only difference is that an insulating layer 3 made of polyimide or the like is previously coated or placed on the entire surface of the electrode plate 2 on the side of the holding portion 2a except for 7a. As described above, even if the insulating resin 1 is not completely injected into the gap between the holding portion 2a and the electrode plate 7, the insulation between the holding portion 2a and the electrode plate 7 can be reliably ensured.
【0017】次に本発明の実施例と従来例のチップ型電
気二重層コンデンサ各100個の製品寸法の平均値およ
びばらつきを表1に示す。Next, Table 1 shows the average value and the variation of the product dimensions of each of 100 chip-type electric double layer capacitors according to the embodiment of the present invention and the conventional example.
【0018】 [0018]
【0019】表1から明らかなように、本発明の実施例
の電気二重層コンデンサは寸法が小さく、かつばらつき
も約1/4と小さくすることができた。As is apparent from Table 1, the size of the electric double layer capacitor of the embodiment of the present invention was small, and the variation was reduced to about 1/4.
【0020】[0020]
【発明の効果】以上説明したように本発明は下記の効果
を有する。As described above, the present invention has the following effects.
【0021】(1)電極部と保持部とを一体化し対向す
る2つの下垂部の間隔を透孔窓の形成により、素子積層
体の外径より小さくし、且つ、保持部と下垂部とは断面
方向の投影形状がT字型となっているため、保持部は成
形後、材料のスプリングバックおよび素子積層体の圧縮
応力により、戻りを生じることがない。また、素子積層
体の外径の接線より下垂部が内側なので、電気二重層コ
ンデンサの等価直列抵抗を小さくし、且つ外形寸法を小
さくできる。(1) The electrode portion and the holding portion are integrated and the interval between two opposing hanging portions is made smaller than the outer diameter of the element laminate by forming a through-hole window. Since the projected shape in the cross-sectional direction is T-shaped, the holding portion does not return due to the springback of the material and the compressive stress of the element laminate after molding. Further, since the hanging portion is inside the tangent to the outer diameter of the element laminate, the equivalent series resistance of the electric double layer capacitor can be reduced, and the outer dimensions can be reduced.
【0022】(2)熱可塑性樹脂を素子積層体の円筒端
面側の中央部より注入するモールド成形による外装方法
のため、素子積層体への熱影響を小さく、半製品を金型
内の定位置に保持し、注入する絶縁樹脂の量も金型で制
御されるので、外形寸法を小さくすると同時に寸法バラ
ツキも小さくできる。また、外装面が平滑なため、真空
吸着法によるプリント配線への自動搭載が可能となる。
さらに、2つのリード端子部の突出方向を互いに180
°反対方向にできるので、プリント配線板への固着安定
性が良くなる。(2) Since the thermoplastic resin is injected from the central portion on the cylindrical end surface side of the element laminate by a molding process, the heat influence on the element laminate is small, and the semi-finished product is fixed in the mold. The amount of the insulating resin to be held and injected is also controlled by the mold, so that the external dimensions can be reduced and the dimensional variation can be reduced. In addition, since the exterior surface is smooth, it can be automatically mounted on printed wiring by a vacuum suction method.
Further, the projecting directions of the two lead terminal portions are set to 180
° Since it can be made in the opposite direction, the stability of fixing to the printed wiring board is improved.
【図1】本発明の第1の実施例の説明図で、(a)は奥
側立面図、(b)は下面図、(c)は手前側立面図、
(d)は上面図、(e)は右側面図、(f)はA−A断
面図、(g)はB−B断面図である。FIG. 1 is an explanatory view of a first embodiment of the present invention, wherein (a) is a rear elevational view, (b) is a bottom elevational view, (c) is a front elevational view,
(D) is a top view, (e) is a right side view, (f) is an AA sectional view, and (g) is a BB sectional view.
【図2】本発明の第1の実施例の外装前の説明図で
(a)は奥側立面図、(b)は下面図、(c)は手前側
立面図、(d)は上面図、(e)は右側面図である。FIGS. 2A and 2B are explanatory views of the first embodiment of the present invention before the exterior, where FIG. 2A is a rear elevation view, FIG. 2B is a bottom view, FIG. 2C is a front elevation view, and FIG. (E) is a right side view.
【図3】本発明の第1の実施例の外装直前の状態図で、
モールド金型にセットし電極板を介して素子積層体を矢
印方向に加圧した状態を示す手前側立面図である。FIG. 3 is a state diagram immediately before the exterior of the first embodiment of the present invention,
FIG. 4 is a front elevational view showing a state where the device is set in a mold and an element laminate is pressed in the direction of an arrow via an electrode plate.
【図4】本発明の第1の実施例の斜視図で(a)は外装
前の組立状態での部品相互の上下位置関係を示す部品構
成図、(b)は外装前の組立状態図、(c)は外装直前
のモールド金型にセットし、電極板を介して素子積層体
を矢印方向に加圧した状態図、(d)はモールド外装後
の状態図、(e)は完成品の状態図である。FIGS. 4A and 4B are perspective views of the first embodiment of the present invention, wherein FIG. 4A is a component configuration diagram showing a vertical positional relationship between components in an assembled state before exterior, FIG. (C) is a state diagram in which the device laminate is set in a mold just before the exterior and the element laminate is pressed in the direction of the arrow via an electrode plate, (d) is a state diagram after the exterior of the mold, and (e) is a completed product. It is a state diagram.
【図5】本発明の第2の実施例の図1(d)のB−B線
相当断面図である。FIG. 5 is a cross-sectional view corresponding to line BB of FIG. 1D of the second embodiment of the present invention.
【図6】従来のチップ型電気二重層コンデンサの一例の
説明図で(a)はA−A断面図、(b)は側面図であ
る。6A and 6B are explanatory diagrams of an example of a conventional chip-type electric double layer capacitor, in which FIG. 6A is a cross-sectional view taken along line AA, and FIG. 6B is a side view.
【図7】電気二重層コンデンサ素子の断面図である。FIG. 7 is a sectional view of an electric double layer capacitor element.
1 絶縁樹脂 1a 電極板側穴部 1b 挾持体側穴部 1c 絶縁樹脂注入ゲート 1d リード収納溝 2 挾持体 2a 保持部 2b 挾持体のリード端子部 2c 電極部 2d 下垂部 2e 透孔窓 3 絶縁層 4 第1の電極板 4a 第1の電極板のリード端子部 5 第2の電極板 5a 第2の電極板のリード端子部 6 素子 6a 素子積層体 7 電極板 7a 電極板のリード端子部 8 導電性セパレータ 9 非導電性ガスケット 10 カーボンペースト電極 11 多孔性セパレータ REFERENCE SIGNS LIST 1 insulating resin 1a electrode plate side hole 1b holding body side hole 1c insulating resin injection gate 1d lead housing groove 2 holding body 2a holding part 2b holding terminal 2c electrode part 2d hanging part 2e through-hole window 3 insulating layer 4 First electrode plate 4a Lead terminal portion of first electrode plate 5 Second electrode plate 5a Lead terminal portion of second electrode plate 6 Element 6a Element laminate 7 Electrode plate 7a Lead terminal portion of electrode plate 8 Conductivity Separator 9 Non-conductive gasket 10 Carbon paste electrode 11 Porous separator
Claims (4)
層体の積層方向の上面にリード端子部を突出させた電極
板,下面にリード端子部を突出させた電極部と素子積層
体を加圧保持する保持部とを一体化した挾持体の電極部
を配置し、前記挾持体が電極部と、該電極部と略直角
で、略平行に対向する中央に素子積層体との接触を回避
する透孔窓を形成し対向間隔が素子積層体の外径より小
さい2つの下垂部と、下垂部の先端を電極部と略平行に
成形した保持部より成り、前記保持部により絶縁層およ
び前記電極板を介して素子積層体を加圧保持し、周囲を
絶縁樹脂の注入よりモールド外装してなることを特徴と
するチップ型電気二重層コンデンサ。1. An electrode plate having a lead terminal protruding from the upper surface in the stacking direction of an element laminate of a cylindrical electric double layer capacitor, and an electrode and an element laminate having a lead terminal protruding from the lower surface are pressed. An electrode portion of a holding body in which a holding portion to be held is integrated is disposed, and the holding body avoids contact between the electrode portion and a central portion of the electrode portion substantially perpendicular to the electrode portion and substantially parallel to each other. It consists of two hanging parts which form a through-hole window and whose facing distance is smaller than the outer diameter of the element laminate, and a holding part whose tip is formed substantially in parallel with the electrode part. The insulating part and the electrode are formed by the holding part. A chip-type electric double-layer capacitor characterized in that an element laminate is pressurized and held via a plate, and the periphery of the element laminate is molded by injection of an insulating resin.
形状をT字型とすることを特徴とする請求項1記載のチ
ップ型電気二重層コンデンサ。2. The chip-type electric double-layer capacitor according to claim 1, wherein a projected shape of the hanging portion and the holding portion in a cross-sectional direction is T-shaped.
を特徴とする請求項1記載のチップ型電気二重層コンデ
ンサ。3. The chip-type electric double layer capacitor according to claim 1, wherein said insulating resin is a thermoplastic resin.
筒端面側の略中央部とすることを特徴とする請求項1記
載のチップ型電気二重層コンデンサ。4. The chip-type electric double-layer capacitor according to claim 1, wherein the injection port of the insulating resin is located substantially at the center on the cylindrical end face side of the element laminate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3040411A JP2629465B2 (en) | 1991-03-07 | 1991-03-07 | Chip type electric double layer capacitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3040411A JP2629465B2 (en) | 1991-03-07 | 1991-03-07 | Chip type electric double layer capacitor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04278510A JPH04278510A (en) | 1992-10-05 |
JP2629465B2 true JP2629465B2 (en) | 1997-07-09 |
Family
ID=12579924
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3040411A Expired - Lifetime JP2629465B2 (en) | 1991-03-07 | 1991-03-07 | Chip type electric double layer capacitor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2629465B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5665617B2 (en) * | 2011-03-17 | 2015-02-04 | 太陽誘電株式会社 | Capacitor configuration unit and capacitor |
JP2013171965A (en) * | 2012-02-21 | 2013-09-02 | Nissin Electric Co Ltd | Electrochemical element |
-
1991
- 1991-03-07 JP JP3040411A patent/JP2629465B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH04278510A (en) | 1992-10-05 |
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