JPH065469A - Chip type electric double layer capacitor - Google Patents

Chip type electric double layer capacitor

Info

Publication number
JPH065469A
JPH065469A JP4165756A JP16575692A JPH065469A JP H065469 A JPH065469 A JP H065469A JP 4165756 A JP4165756 A JP 4165756A JP 16575692 A JP16575692 A JP 16575692A JP H065469 A JPH065469 A JP H065469A
Authority
JP
Japan
Prior art keywords
electric double
double layer
electrode plate
layer capacitor
chip type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4165756A
Other languages
Japanese (ja)
Inventor
Masayuki Ikeda
雅之 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4165756A priority Critical patent/JPH065469A/en
Publication of JPH065469A publication Critical patent/JPH065469A/en
Pending legal-status Critical Current

Links

Classifications

    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/13Energy storage using capacitors

Landscapes

  • Electric Double-Layer Capacitors Or The Like (AREA)

Abstract

PURPOSE:To obtain a small-sized chip type electric double layer capacitor excellent in packaging stability wherein the equivalent series resistance is small and the automatic mounting on a printed wiring board is possible. CONSTITUTION:Two element laminates 10a of rectangular electric double layer capacitors are arranged in parallel. The element laminates 10a are pressed and retained via terminal electrode plates 7, 8 and an intermediate electrode plate 9. In this state, the periphery of the laminates is covered with insulating resin 1. Thereby the volume efficiency is improved, and the external size of the element can be reduced. Since the two element laminates 10a are arranged in parallel, the number of element lamination layers of one element laminate 10a can be reduced to 1/2 as compared with the conventional case, and the element laminate can be thinned. Further, since the molding is performed in the pressed state, the equivalent series resistance, the external size, and the dimensional irregularity can be reduced. The automatic mounting is enabled by vacuum suction.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は電気二重層コンデンサに
関し、特に表面実装に対応するチップ型電気二重層コン
デンサのケーシング構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electric double layer capacitor, and more particularly to a casing structure for a chip type electric double layer capacitor which is compatible with surface mounting.

【0002】[0002]

【従来の技術】近年、ヘッドホンステレオ,コードレス
電話等携帯用の電子機器の小形化・薄型化には著しいも
のがある。これらの電子機器に実装される電気二重層コ
ンデンサも他の電子部品と同様に小型化,薄形化し、さ
らには表面実装化への要求が頻繁化しつつある。従来、
この種の電気二重層コンデンサとしては、大容量のコン
デンサを得る手段の一つとして、米国特許第35369
63号明細書にて開示されているように、カーボン粉末
と電解液とを接触させて電気二重層を発生させることを
利用したもがある。図5は円筒形の電気二重層コンデン
サ素子(以下、素子と称す)の断面図である。図5にお
いて、11は電子伝導性でかつイオン不浸透性の導電性
セパレータ,13は粉末活性炭と電解質溶液からなるカ
ーボンペースト電極,14はカーボンペースト電極間の
導通を防止するために設けたイオン透過性で、かつ非電
子伝導性を有する多孔性セパレータ,12はカーボンペ
ースト電極を保持し、かつ外界から遮断するために設け
た非導電性ガスケットである。
2. Description of the Related Art In recent years, portable electronic devices such as headphone stereos and cordless phones have been remarkably reduced in size and thickness. Electric double-layer capacitors mounted on these electronic devices are becoming smaller and thinner like other electronic components, and there is a growing demand for surface mounting. Conventionally,
As this kind of electric double layer capacitor, one of means for obtaining a large capacity capacitor is disclosed in US Pat. No. 35369.
As disclosed in Japanese Patent No. 63, 63, there is a method in which a carbon powder and an electrolytic solution are brought into contact with each other to generate an electric double layer. FIG. 5 is a sectional view of a cylindrical electric double layer capacitor element (hereinafter referred to as an element). In FIG. 5, 11 is an electrically conductive and ion-impermeable conductive separator, 13 is a carbon paste electrode composed of powdered activated carbon and an electrolyte solution, and 14 is an ion permeation layer provided to prevent conduction between the carbon paste electrodes. The porous separator 12, which is electrically conductive and has non-electron conductivity, is a non-conductive gasket provided to hold the carbon paste electrode and to shield it from the outside.

【0003】図4は従来のチップ形電気二重層コンデン
サの断面図である。図4において、10aは素子10を
積層した素子積層体、4および5は夫々リード端子部4
aおよび5aを有する第1の電極板と第2の電極板、2
は素子積層体を加圧・保持するための保持部2aを有す
る挾持体、3は第1および第2の電極板と挾持体とを絶
縁するための絶縁層,1は外装のためのエポキシ樹脂等
の絶縁樹脂である。従来の電気二重層は挾持体2にて素
子積層体10aを加圧・保持した後、素子積層体10a
の側面での電気的短絡を防ぐために、エポキシ樹脂の溶
液中に浸漬させ、その後高温槽内で加圧硬化させて外装
を行なっていた。
FIG. 4 is a sectional view of a conventional chip type electric double layer capacitor. In FIG. 4, 10a is an element laminated body in which the elements 10 are laminated, and 4 and 5 are lead terminal portions 4 respectively.
a first electrode plate and a second electrode plate having a and 5a, 2
Is a holder having a holding portion 2a for pressing and holding the element stack, 3 is an insulating layer for insulating the first and second electrode plates from the holder, and 1 is an epoxy resin for exterior Is an insulating resin. In the conventional electric double layer, the element stack 10a is pressed and held by the holding body 2 and then the element stack 10a is pressed.
In order to prevent an electrical short circuit on the side surface of the device, it was dipped in a solution of an epoxy resin and then pressure-cured in a high temperature tank to carry out exterior packaging.

【0004】[0004]

【発明が解決しようとする課題】この従来のチップ型電
気二重層コンデンサは、断面コの字型の挾持体に第1の
電極板,素子積層体,第2の電極板を所定の位置に配置
し、第1の電極板を介して素子積層体を加圧した状態で
挾持体の先端を内側に略直角に折り曲げて保持部を形成
するため、およびエポキシ樹脂の溶液中に浸漬した後、
加熱硬化させるという外装方法のため、下記の問題点が
あった。 (1)挾持体の保持部は、成形後材料のスプリングバッ
クおよび素子積層体の圧縮応力により、図4(a)に示
す通り矢印方向に戻るため、素子積層体への保持圧力の
低下による電気二重層コンデンサの等価直列抵抗の増大
および外形寸法が増大する。 (2)付着樹脂量が多くなると外形寸法が増大すると同
時に寸法バラツキが増大する。 (3)外装面が凸凹しているため、真空吸着法によるプ
リント配線板への自動搭載が不可能である。 (4)2つのリード端子部が同一方向から突出している
ため、固着安定性が悪く、プリント配線板へのはんだ付
け後に振動等が加わった場合、プリント配線板から離脱
するものがある。
In this conventional chip-type electric double layer capacitor, the first electrode plate, the element stack, and the second electrode plate are arranged in a predetermined position on a holding body having a U-shaped cross section. Then, in order to form the holding portion by bending the tip of the holding body inwardly at a substantially right angle in a state in which the element laminated body is pressed through the first electrode plate, and after immersing in the epoxy resin solution,
Due to the exterior method of curing by heating, there were the following problems. (1) The holding portion of the holding body returns in the direction of the arrow as shown in FIG. 4 (a) due to the springback of the material after molding and the compressive stress of the element laminated body. The equivalent series resistance of the double-layer capacitor increases and the external dimensions increase. (2) When the amount of adhered resin increases, the external dimensions increase and the dimensional variations increase at the same time. (3) Since the exterior surface is uneven, automatic mounting on a printed wiring board by a vacuum suction method is impossible. (4) Since the two lead terminal portions project from the same direction, the fixation stability is poor, and when vibration or the like is applied after soldering to the printed wiring board, the lead terminal portion may be separated from the printed wiring board.

【0005】本発明の目的は、小型で等価直列抵抗が低
く、プリント配線板への自動搭載が可能で、実装安定性
の良いチップ型電気二重層コンデンサを提供することに
ある。
An object of the present invention is to provide a chip type electric double layer capacitor which is small in size, has a low equivalent series resistance, can be automatically mounted on a printed wiring board, and has good mounting stability.

【0006】[0006]

【課題を解決するための手段】本発明のチップ型電気二
重層コンデンサは、2個並列に配置された矩形の電気二
重層コンデンサ素子積層体と、その素子積層体の積層方
向の下面に接し2個の素子積層体を電気的に直列接続す
る中間電極板と、前記素子積層体の上面にそれぞれが電
気的に独立して接し外部へ電気的に引き出すリード端子
を連接した一対の終端電極板と、その終端電極板と前記
中間電極板を介して2個の素子積層体を加圧保持すべく
周囲を被覆した絶縁樹脂とを有して構成される。
A chip type electric double layer capacitor of the present invention comprises two rectangular electric double layer capacitor element laminated bodies arranged in parallel and a lower surface of the element laminated body in the laminating direction in contact with each other. An intermediate electrode plate that electrically connects the individual element laminates in series, and a pair of terminal electrode plates that are connected to the upper surface of the element laminate independently of each other and have lead terminals that are electrically drawn to the outside. , The terminal electrode plate and an insulating resin which covers the periphery of the two element laminated bodies via the intermediate electrode plate so as to pressurize and hold them.

【0007】なお、終端電極板の少なくとも片側のリー
ド端子を2分割することによりプリント配線板への実装
の安定性と逆実装の異常を防止できるという効果が得ら
れる。
By dividing at least one lead terminal of the terminal electrode plate into two, it is possible to obtain the effect of stabilizing the mounting on the printed wiring board and preventing abnormalities in the reverse mounting.

【0008】[0008]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例の(a)は上面図,(b)
は(d)のA−A断面図,(c)は下面図,図3は本発
明の電気二重層コンデンサ素子の(a)は(b)のA−
A断面図、(b)は右側面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1A is a top view of an embodiment of the present invention, and FIG.
Is a sectional view taken along the line A-A in (d), (c) is a bottom view, and FIG. 3 shows (a) of the electric double-layer capacitor element of the present invention taken along line A- of (b).
A sectional view, (b) is a right side view.

【0009】図1および図3において、まず幅3.8m
m,長さ8.0mm,厚さ1.1mmの素子10を3枚
積層し、素子積層体10aを得る。素子積層体10a
は、2個を1辺が8mmの正方形で厚さ0.4mmの鉄
・ニッケル合金にはんだメッキを施した中間電極板9に
配置する。次に、素子積層体10aの上面に幅3.0m
m,厚さ0.4mm,長さ5mmのリード端子7a,8
aを突出させた幅3.8mm,長さ8.0mmの鉄・ニ
ッケル合金にはんだメッキを施した1対の終端電極板
7,8を2個の素子積層体10aの上面に合致するよう
に配置する。終端電極板7,8,中間電極板9,素子積
層体10aの相対位置関係を維持するようにかしめ等の
公知の手段で固定した後、縦10mm,横10mm,厚
さ4.5mmの中空部を有するモールド型に中間電極板
9側を上にしてセットし、終端電極板7,8,中間電極
板9を介して、上下各4個の金型ピン(図示省略)で素
子積層体10aを無負荷時の約80%の厚さになるよう
に圧縮させ、PPS(ポリフェニレンサルファイド)等
の熱可塑性で高耐熱性の絶縁樹脂1を金型内の全間隙へ
中間電極板9上部中央の絶縁樹脂注入ゲート1cより注
入し成形する。絶縁樹脂注入ゲート1cは通称ピンポイ
ントゲートと呼ばれるもので、モールド成形完了時点の
金型が開く際に自動的に製品側の根元より切断される。
また、終端電極板側穴部1aおよび中間電極板側穴部1
bは前記金型ピンの跡である。素子積層体10aはモー
ルド成形完了後も無負荷時の約80%の厚さに圧縮され
ているため、等価直列抵抗が低い電気二重層コンデンサ
となる。以上により、本発明の第1の実施例の電気二重
層コンデンサを得た。
In FIGS. 1 and 3, first, the width is 3.8 m.
Three elements 10 each having m, a length of 8.0 mm, and a thickness of 1.1 mm are laminated to obtain an element laminated body 10a. Element stack 10a
Are placed on an intermediate electrode plate 9 which is a square having a side of 8 mm and a thickness of 0.4 mm and which is solder-plated on an iron-nickel alloy. Next, on the upper surface of the element laminate 10a, a width of 3.0 m
m, thickness 0.4 mm, length 5 mm lead terminals 7a, 8
A pair of terminal electrode plates 7, 8 obtained by solder-plating an iron-nickel alloy having a width of 3.8 mm and a length of 8.0 mm, in which a is projected, are fitted to the upper surfaces of the two element laminated bodies 10a. Deploy. After fixing the terminal electrode plates 7 and 8, the intermediate electrode plate 9, and the element laminated body 10a by a known means such as caulking so as to maintain the relative positional relationship, a hollow portion having a length of 10 mm, a width of 10 mm, and a thickness of 4.5 mm. The intermediate electrode plate 9 side is set up in a mold having the above, and the element laminated body 10a is inserted with the upper and lower four mold pins (not shown) through the terminal electrode plates 7 and 8 and the intermediate electrode plate 9. It is compressed to a thickness of about 80% of that when no load is applied, and thermoplastic and highly heat-resistant insulating resin 1 such as PPS (polyphenylene sulfide) is filled into the entire gap in the mold to insulate the upper center of the intermediate electrode plate 9. It is injected from the resin injection gate 1c and molded. The insulating resin injection gate 1c is commonly called a pin point gate, and is automatically cut from the root of the product side when the mold is opened at the time of completion of molding.
In addition, the terminal electrode plate side hole 1a and the intermediate electrode plate side hole 1
b is a mark of the mold pin. Since the element laminated body 10a is compressed to a thickness of about 80% after no molding is performed, the electric double layer capacitor has a low equivalent series resistance. As described above, the electric double layer capacitor of the first embodiment of the present invention was obtained.

【0010】図2は本発明の他の実施例を説明するため
の図面で図1(c)に相当する下面図である。第1の実
施例とは第2の終端電極板のリード端子8aを2分割し
ている点のみ異なる。本第2の実施例によればリード端
子が3端子となるため、3点支持によるプリント配線板
への実装安定性の改善と、リード端子7a,8aを逆に
実装した場合にはプリント配線板に構成される電極部と
合致しないため、はんだ付けが不可能となり、異常品の
排除が容易となる。
FIG. 2 is a drawing for explaining another embodiment of the present invention and is a bottom view corresponding to FIG. 1 (c). It differs from the first embodiment only in that the lead terminal 8a of the second terminal electrode plate is divided into two. According to the second embodiment, since the lead terminals are three terminals, the mounting stability on the printed wiring board is improved by supporting three points, and the printed wiring board is mounted when the lead terminals 7a and 8a are reversely mounted. Since it does not match the electrode portion configured in (3), soldering becomes impossible and abnormal products can be easily eliminated.

【0011】次に、定性的な効果の他に定量的な数値デ
ータとして、表1の(a),(b)に本発明の実施例と
従来例のチップ型電気二重層コンデンサ各100個の製
品寸法の平均値およびばらつきを示す。表1から明らか
なように本発明の電気二重層コンデンサは寸法が小さ
く、且つばらつきも約1/4と小さくすることができ
た。
Next, as quantitative numerical data in addition to the qualitative effect, as shown in Tables 1 (a) and 1 (b), 100 chips each of the chip type electric double layer capacitors of the embodiment of the present invention and the conventional example are shown. The average value and variation of product dimensions are shown. As is clear from Table 1, the electric double layer capacitor of the present invention has a small size and the variation can be reduced to about 1/4.

【0012】[0012]

【表1】 [Table 1]

【0013】[0013]

【発明の効果】以上説明したように本発明は下記の効果
を有する。 (1)非導電性ガスケットに設けるカーボンペースト電
極の充填部を含めて、電気二重層コンデンサ素子が矩形
のため、概略正四方形で構成される面積と前記正四方形
の内接円で構成される面積との比の分だけ、電気二重層
コンデンサ素子の体積効率が改善され、素子の外形寸法
を小さくできる。さらに、素子積層体を2個並列に配置
するため、1個の素子積層体の素子の積層枚数を従来の
1/2にできるため、素子積層体の厚さを薄くすること
ができる。
As described above, the present invention has the following effects. (1) Since the electric double layer capacitor element including the filling portion of the carbon paste electrode provided on the non-conductive gasket is rectangular, the area formed by the substantially regular square and the area formed by the inscribed circle of the regular square. The volumetric efficiency of the electric double layer capacitor element is improved by the ratio of the ratio to and the external dimension of the element can be reduced. Further, since the two element laminated bodies are arranged in parallel, the number of laminated elements of one element laminated body can be reduced to half that of the conventional one, so that the thickness of the element laminated body can be reduced.

【0014】また、素子積層体を加圧した状態でモール
ド成形を行ない、モールド成形完了後も絶縁樹脂によ
り、モールド成形時の加圧状態を維持しているため、電
気二重層コンデンサの等価直列抵抗も小さくし、且つ外
形寸法を小さくできる。 (2)熱可塑性樹脂を素子積層体を円筒端面側の中央部
より注入するモールド成形による外装方法のため、素子
積層体への熱影響を小さく、素子積層体および終端電極
板,中間電極板を金型内の所定位置に保持し、注入する
絶縁樹脂の量も金型で制御されるので、外形寸法を小さ
くすると同時に寸法バラツキも小さくできる。また、外
装面が平滑なため、真空吸着によるプリント配線板への
自動搭載が可能となる。さらに、2つの終端電極板と連
接するリード端子の突出方向を互いに180°反対方向
にできるので、プリント配線板への固着安定性が良くな
る。第2の実施例の場合は3端子による2点支持のた
め、プリント配線板への固着安定性はさらに良くなる。
Further, since the element laminated body is molded under pressure, and the insulating resin maintains the pressure during molding, the equivalent series resistance of the electric double layer capacitor is maintained. Can be made smaller and the external dimensions can be made smaller. (2) Due to the exterior method by molding in which the element laminate is injected with the thermoplastic resin from the central portion on the end face side of the cylinder, the heat influence on the element laminate is small, and the element laminate, the terminal electrode plate, and the intermediate electrode plate are formed. Since the amount of the insulating resin to be held at a predetermined position in the mold is also controlled by the mold, it is possible to reduce the outer dimension and the dimension variation. Further, since the exterior surface is smooth, it can be automatically mounted on the printed wiring board by vacuum suction. Further, since the lead terminals that are connected to the two terminal electrode plates can be projected in opposite directions to each other by 180 °, the fixing stability to the printed wiring board is improved. In the case of the second embodiment, since the two terminals are supported by the three terminals, the fixing stability to the printed wiring board is further improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のチップ型電気二重層コンデ
ンサの(a)は上面図,(b)はA−A断面図,(c)
は下面図,(d)は右側面図である。
FIG. 1A is a top view of a chip type electric double layer capacitor according to an embodiment of the present invention, FIG. 1B is a sectional view taken along line AA, and FIG.
Is a bottom view, and (d) is a right side view.

【図2】本発明の他の実施例の下面図である。FIG. 2 is a bottom view of another embodiment of the present invention.

【図3】図1に示す本発明の一実施例のチップ型電気二
重層コンデンサ素子の(a)A−A断面図,(b)は右
側面図である。
3 (a) is a sectional view taken along the line AA of the chip type electric double layer capacitor element of the embodiment of the present invention shown in FIG. 1, and FIG. 3 (b) is a right side view.

【図4】従来のチップ型電気二重層コンデンサの(a)
はA−A断面図,(b)は右側面図である。
FIG. 4 (a) of a conventional chip type electric double layer capacitor
Is a sectional view taken along the line AA, and (b) is a right side view.

【図5】従来の電気二重層コンデンサ素子の断面図であ
る。
FIG. 5 is a cross-sectional view of a conventional electric double layer capacitor element.

【符号の説明】[Explanation of symbols]

1 絶縁樹脂 1a 終端電極板側穴部 1b 中間電極板側穴部 1c 絶縁樹脂注入ゲート 2 挾持体 2a 保持部 3 絶縁層 4 第1の電極板 4a 第1の電極板のリード端子 5 第2の電極板 5a 第2の電極板のリード端子 7 第1の終端電極板 7a 第1の終端電極板のリード端子 8 第2の終端電極板 8a 第2の終端電極板のリード端子 9 中間電極板 10 素子 10a 素子積層体 11 導電性セパレータ 12 非導電性ガスケット 13 カーボンペースト電極 14 多孔性セパレータ DESCRIPTION OF SYMBOLS 1 Insulating resin 1a Termination electrode plate side hole 1b Intermediate electrode plate side hole 1c Insulating resin injection gate 2 Holding body 2a Holding part 3 Insulating layer 4 First electrode plate 4a First electrode plate lead terminal 5 Second Electrode plate 5a Lead terminal for second electrode plate 7 First terminal electrode plate 7a Lead terminal for first terminal electrode plate 8 Second terminal electrode plate 8a Lead terminal for second terminal electrode plate 9 Intermediate electrode plate 10 Element 10a Element laminate 11 Conductive separator 12 Non-conductive gasket 13 Carbon paste electrode 14 Porous separator

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 2個並列に配置された矩形の電気二重層
コンデンサ素子積層体と、該素子積層体の積層方向の下
面に接し2個の素子積層体を電気的に直列接続する中間
電極板と、前記素子積層体の上面にそれぞれが電気的に
独立して接し外部へ電気的に引き出すリード端子を連接
した一対の終端電極板と、該終端電極板と前記中間電極
板を介して2個の素子積層体を加圧保持すべく周囲を被
覆した絶縁樹脂とを有することを特徴とするチップ型電
気二重層コンデンサ。
1. A rectangular electric double layer capacitor element laminated body arranged in parallel, and an intermediate electrode plate which is in contact with the lower surface of the element laminated body in the laminating direction and electrically connects two element laminated bodies in series. And a pair of terminal electrode plates, each of which is electrically independently contacted with the upper surface of the element laminate and connected with a lead terminal that is electrically drawn to the outside, and two terminal electrode plates through the terminal electrode plate and the intermediate electrode plate. 2. An electric double layer capacitor of chip type, characterized in that it has an insulating resin whose periphery is covered so as to hold the element laminated body under pressure.
【請求項2】 少なくとも片側の終端電極板のリード端
子が2分割されていることを特徴とする請求項1記載の
チップ型電気二重層コンデンサ。
2. The chip type electric double layer capacitor according to claim 1, wherein at least one lead terminal of the terminal electrode plate on one side is divided into two.
JP4165756A 1992-06-24 1992-06-24 Chip type electric double layer capacitor Pending JPH065469A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4165756A JPH065469A (en) 1992-06-24 1992-06-24 Chip type electric double layer capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4165756A JPH065469A (en) 1992-06-24 1992-06-24 Chip type electric double layer capacitor

Publications (1)

Publication Number Publication Date
JPH065469A true JPH065469A (en) 1994-01-14

Family

ID=15818463

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4165756A Pending JPH065469A (en) 1992-06-24 1992-06-24 Chip type electric double layer capacitor

Country Status (1)

Country Link
JP (1) JPH065469A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008153266A (en) * 2006-12-14 2008-07-03 Matsushita Electric Ind Co Ltd Surface mounting square electric storage cell

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008153266A (en) * 2006-12-14 2008-07-03 Matsushita Electric Ind Co Ltd Surface mounting square electric storage cell

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