JP2625734B2 - Data recorder - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data recorder for recording a data signal and the like from a computer using a rotary head type digital audio tape recorder (DAT).

[Summary of the Invention]

The present invention relates to a data recorder, by using a so-called DAT recording device and providing means for determining the continuity of two tracks in a data signal of two tracks forming one frame of the DAT format. In addition, it is possible to easily detect the remaining erase of the data signal by the head clock or the like.

[Conventional technology]

For example, in a computer, in order to save data written on a hard disk or the like, such data is transferred to a so-called data recorder for recording.

In such a case, a so-called analog audio tape recorder has often been used as the above-mentioned data recorder. However, in such an analog tape recorder, the consumption of the recording medium becomes extremely large, and the data rate at the time of recording is low, so that much time is required for transfer and recording. Further, there is a problem that a desired recording portion cannot be easily located at the head.

By the way, DAT (Digital Audio Tape Recorder) has been developed ("ES Review" published by Shibaura Factory, Sony Corporation: ISSN 0389-7737: December 1985, Nos. 11-17)
Page). According to the DAT, since it is originally designed to record and reproduce a digital signal, it is suitable for recording data as described above.

However, in such a DAT, when another signal is recorded on a medium on which a signal is once recorded, generally, the previous signal is recorded by recording a new signal by so-called overwriting without using an erase head. I try to erase it. For this reason, if overwriting is not performed normally by, for example, the head clock, the previous signal may remain unerased.

Therefore, in the DAT format, an error detection code is added to each track to be recorded, and when an erasure remains in a part of the track, it is detected as an error. However, even if such a code is added, if the entirety of one track remains unerased, the error detection code in this track is normal and cannot be detected. I will.

If the signal to be recorded here is an audio signal, the signal from the remaining track can be eliminated due to compatibility between the front and rear tracks. However, when DAT is used as a data recorder, generally, data compatibility cannot be used.

By the way, when DAT is used as a data recorder, D
It is conceivable that an error correction code is generated for the data signals of a plurality of frames supplied to the AT, and the generated code is supplied to the DAT and recorded in the same manner as the data signal. According to this, since error correction is performed outside the DAT, a strong error correction capability can be provided.

However, in this case, in order to perform error correction, a frame in which an error has occurred must be detected in advance. However, if the entire track remains unerased as described above, this error cannot be detected. Therefore, even if an error correction code is generated outside the above-described DAT, the error is corrected. I couldn't do anything.

[Problems to be solved by the invention]

As described above, in the conventional technique, when the DAT is used as a data recorder, there is a problem that error correction cannot be performed if a track remaining to be erased occurs.

[Means for solving the problem]

The present invention has a rotating head (11), and two rotation tracks are formed on a recording medium (12) by one rotation of the rotation head. An apparatus in which a signal or a code signal is formatted (digital signal processing circuit (14)) for each frame and recorded and reproduced, and forms one frame of the data signal to be formatted. Means for generating a predetermined error detection code for the entire data signal contained in the track (EC
C generation circuit (25)), and the data signal of the one frame together with the generated error detection code (memory (24))
A data recorder comprising a recording unit (DAT (1)) for recording on the recording medium.

[Action]

According to this, in a data signal of two tracks forming one frame of the DAT format, a predetermined error detection code is used for the entire data signal contained in the two tracks forming these one frame. Is generated, it is possible to easily detect the unerased residue of the data signal due to the head clog or the like, whereby a good data recorder can be formed using this DAT.

〔Example〕

In FIG. 1, (1) shows the structure of the DAT.
(1) is provided with a rotary head drum (11), and the magnetic tape (12) is wound around and transported by a range of about 90 degrees around the drum (11). And this drum (11)
A and B recording / reproducing heads are provided at an angle interval of 180 degrees on the upper side, and two inclined tracks are recorded / reproduced by one rotation of the drum (11). .

On the other hand, digital data from the outside is input to the IO circuit (13), and is supplied from the IO circuit (13) to the digital signal processing circuit (14) to be converted into the DAT format described above. The formatted signal is supplied to the heads A and B through the recording amplifier (15) and the recording / reproducing switch (16) on the recording side, and is recorded on the tape (12). The signals recorded on the tape (12) are
The reproduced signal is supplied to the processing circuit (14) through the reproduction side contact of the recording / reproduction changeover switch (16) and the reproduction amplifier (17), and the digital data obtained by inverse conversion is taken out by the IO circuit ( Output to outside through 13).

Further, an external control signal is supplied to a system control circuit (18), and the signal from the control circuit (18) controls the rotation of the head drum (11), the transfer control of the tape (12), and the switching of the switch (16). Controls are performed, and a recording control circuit (18)
Is supplied to the processing circuit (14) to form a predetermined subcode signal. At the time of reproduction, a signal extracted by the processing circuit (14) is supplied to a control circuit (19) to perform control such as tracking, and a part of the signal is taken out.

DAT (1) is formed by the above configuration. In this device, a DA / AD conversion circuit is provided outside the IO circuit (13), and a predetermined control device is provided outside the control circuit (18), so that, for example, recording / reproducing of an audio (analog) signal is performed. be able to.

On the other hand, in the above-mentioned device, an arbitrary interface bus (3) is connected to the outside of the DAT (1) via the controller (2). Here, for example, the SCSI standard (“NIKKEI ELECTRONICS”) is used as the interface bus (3).
Nihon Keizai Shimbun, Inc .: see October 6, 1986, pp. 102-107). Further, a host computer (5), a hard disk device (6) and the like are connected to the bus (3) via an adapter (4).

A protocol control circuit (21) is provided between the controller (2) and the bus (3), and the microcomputer (22) controls the operation of the controller (2) via the control circuit (21). ) And a memory control (DMA) circuit (23), and data and control signals are exchanged between the bus (3). Further, state detection and operation control are performed between the microcomputer (23) and the DMA circuit (23), and data is transferred between the buffer memory (24) and the bus (3) through the DMA circuit (23). Input and output are performed.

In addition to this memory (24), this memory (24)
A circuit (25) for generating an error correction code (ECC) for the data written in the memory (24) is provided, and the error correction code generated by the circuit (25) is written to a predetermined portion of the memory (24). Data is input and output between the memory (24) and the processing circuit (14) of the DAT (1) via the IO circuits (26) and (13). Control signals are exchanged between the microcomputer (22) and the system control circuit (18).

Therefore, in this device, the hard disk device (6)
Is written to the controller (2) via the bus (3) in response to a transfer request from the controller (2) at the time of recording, and is written to the memory (2) via the DMA circuit (23).
Written in 4). An error correction code is generated by the generation circuit (25) for the data written in the memory (24), and the data including the error correction code is read out via the I / O circuit (26) and read out from the DAT (1). ). In this DAT (1), the data input to the IO circuit (13) is regarded as being equivalent to the data from the AD conversion circuit at the time of audio recording, and the digital signal processing circuit (14) performs the predetermined DAT (14).
Format and converted to a tape (1
Recorded in 2).

Then, at the time of this recording, the generation of the error correction code is performed as follows.

That is, for an arbitrary data string supplied to the DAT (1), the error correction code generation matrix is set as follows, for example.

Further, for this generation matrix, a syndrome generation circuit can be formed, for example, as shown in FIG. That is, in the drawing, the data signal supplied to the left terminal (31) is supplied to each of the adders (32a) to (32d), and the signals from the adders (32a) to (32d) are directly or α, alpha _2, is supplied to the syndrome register (34a) ~ (34d) through alpha ₃ of the coefficient circuit (33b) ~ (33d). The signals from the registers (34a) to (34d) are fed back to the adders (32a) to (32d), and the feedback is performed every time a data signal is supplied. A syndrome is generated.

Therefore, in this circuit, every time a data signal is supplied, the calculation is performed from the right side of the data portion of the matrix described above. Usually, when data of, for example, 251 symbols are supplied, syndromes are generated in the registers (34a) to (34d), and the syndromes are supplied to the arithmetic circuit (35) corresponding to the matrix of the above-mentioned parity section, and the data is stored in the register. An error correction code for the symbol is generated. On the other hand, if the data sequence ends while the above operation is in progress, a syndrome equivalent to all 0s being supplied to the left of the point where the operation on the matrix has progressed at that time is registered. (34a) to (34d) are generated. At this time, the registers (34a) to (34d) are fixed and the contents are supplied to the arithmetic circuit (35). An error correction code is generated for the data.

This makes it possible to smoothly add an error correction code to an arbitrary variable-length data string. In this case, the above-described syndrome generation circuit is actually formed by software such as a microcomputer, but the specific configuration required here is that of the syndrome registers (34a) to (34a).
Only a memory area corresponding to (34d) can be realized with a very simple configuration. Registers (34a) to (34
The memory capacity of d) is only the data amount for one track × 4, and the required memory capacity can be extremely reduced.

The generated error correction code is supplied to the DAT (1) continuously to the data signal, so that the recording of an arbitrary variable-length data signal can be performed smoothly, and a good data recorder using the DAT is provided. Can be formed.

When the error correction code is two symbols as a special case, for example, , Which eliminates the need for the arithmetic circuit (25).

Further, in the above-described apparatus, the error correction processing at the time of reproduction can be performed as follows.

That is, in FIG. 3, a data signal and an error correction code (ECC) are reproduced as shown in FIG. A, and error correction cannot be performed on this signal by, for example, DAT (1) as shown in FIG. When a frame is detected, the state where the data signal is directly output first is stopped as shown in FIG. However, at this time, the supply of data to the above-mentioned syndrome generation circuit is continued, and when the reproduction of the error correction code is completed, the above-mentioned data is supplied to the syndrome generation circuit.
Data for error correction for an error frame is generated from DAT (1). From this state, a rewind command is issued to DAT (1) as shown in FIG. D, and the data is reproduced again from the beginning, as shown in FIG. On the other hand, the correction data from the syndrome generation circuit is inserted, and the entire data signal is reproduced.

Therefore, when there is no normal error frame, the data signal is reproduced as it is and output to the interface bus (3). On the other hand, the above processing is performed only when there is an error frame. Is played. Further, when the above error correction is performed, by using a data signal reproduced again from the DAT (1), there is no need to provide a large-capacity buffer memory or the like corresponding to the entire data section, and the above-described syndrome is eliminated. Error correction can be performed only in a small-capacity memory area corresponding to a register.

In the above-mentioned device, the format of the DAT recorded on the tape (12) is as follows.

That is, in FIG.
One track is composed of the tracks Ta and Tb, and these tracks are formed from the lower side of the drawing, respectively, and the recorded signal is transmitted from the lower end side with respect to the total length 90 degrees.
5.051 degree margin part → 0.918 degree subcode PLL preamble part → 3.673 degree first subcode part → 0.459
Postamble part of the block → Gap between blocks at 1.378 degrees → Tracking (ATF) signal part at 2.296 degrees → Gap between blocks at 1.378 degrees → Preamble part for PLL of 0.918 degrees data → Data part at 58.776 degrees → 1.378-degree gap between blocks → 2.296-degree AFT signal section → 1.378-degree gap between blocks → 0.918-degree subcode PLL preamble section → 3.673 second subcode section → 0.459
Degree postamble part → 5.051 degree margin part. The scale of the figure is not accurate. In the above-described device, the data input from the IO circuit (13) is added with a predetermined error detection / correction code or the like by the processing circuit (14).
The data are sorted and inserted into the data portions of the tracks Ta and Tb in a predetermined interleave relationship.

In the data section, an 8-bit synchronization section is provided at the beginning of the data section, followed by a 16-bit ID section called W1 and W2. Therefore, this ID part is divided into eight ID areas of 2 bits each, and “01” is provided as the format ID of the first ID area (ID-0) in the case of data specification, for example. In the next ID area (ID-1), "00" is provided as a subcategory ID in the case of a computer peripheral device, for example. Further ID
-2 is a frame size ID, for example, “00” when the recording capacity of one frame is 5760 bytes, and “0” when the recording capacity of one frame is 5592 bytes.
1 "is provided. The next ID-5 is the track pitch ID.
For example, when the track pitch is 13.6 μm, “00”, 2
At the time of 0.4 μm, “01” is provided.

Similarly, IDs of W1 and W2 are provided for the subcode portion. In this ID portion, first, a code (VF) indicating valid (1) and invalid (0) of data is provided in the first bit of W1.
Are provided, and the area including the frame in the next three bits is the lead-in area (000) at the beginning of the tape, the data area (001), the lead-out area (010) at the end of data recording, and the end-of-media at the end of the tape. An area ID indicating (011) is provided, and the content of the frame is a normal frame (0 ** 0), an amble frame (0 ** 1) used for synchronization, etc., and a frame other than a file mark (000 *) in the next 4 bits. , First file mark (001 *), second file mark (010 *), third file mark (011
A frame ID indicating *) is provided. The first bit of W2 is set to "1", and the next three bits indicate that the following subcode is in a pack format described later. A format ID of “000” is provided, and a numerical value indicating a block address is provided in the last four bits. Note that the LSB of the block address is set to “0” in the first subcode and “1” in the second subcode.

As described above, various identifications and the like in the case where DAT (1) is used as a data recorder are performed.

Further, in the above-described apparatus, the data portion is provided with a recording capacity of, for example, 5760 bytes for one frame, and the data of one frame is subjected to the following formatting, for example.

That is, in FIG. 5, the above-mentioned 5760 bytes are formed into words (0 to 1439) of 4 bytes (32 bits), and each of these words is 16 bits (2 bytes) of L in accordance with the audio signal. It is divided into a channel and an R channel. And in this format,
First, a synchronizing part of 3 words (12) bytes is provided, the first 1 byte is all "0", the next 10 bytes are all "1", and the last 1 byte is all "0". You.

Next, an 8-word (32-byte) header section is provided. First, the 4 bits on the LSB side of the first half byte of the L channel of word 3, the second half byte, and the first half byte of the R channel are used as a logical frame number (LFNO) area. A binary value indicating the serial number of the effective frame from the leading end of is provided. Note that all invalid frames are set to “0”. Also L
The same frame ID as that provided in W1 of the above-described subcode part is provided in the four bits on the MSB side of the first half byte of the channel. Further, the latter half byte of the R channel is used as a mode area, for example, "0000" to "0011" for a CD-ROM.
Are assigned, and “1000” is provided for DAT.

The first half byte of the L channel of word 4 is used as an area for displaying a data state, and the recording format is streaming type 1 using the 4 bits on the MSB side of this byte.
(0000), type 2 (0001), and a code indicating start-stop type 1 (0010) are provided, and the data of the header portion is further supplied from the bus (3) to the next 1 bit. A flag (DH) indicating whether (1) or not (0) is also provided in the data signal is provided.
Number of frames of error correction code (PFL) in 3 bits on B side
Is provided as a binary value. Further, the latter half byte of the L channel of word 4 is an area of the total number of frames (ECFL) of the data signal and the error correction code, and this value is provided as a binary value. It is set to “0”.

The 7 bits on the LSB side of the first half byte of the R channel of word 4 are used as an overwrite count (OWNO) area, and the count is provided as a binary value. Further, one bit on the MSB side is used as a discrimination area between the data frame and the error correction code frame. When this bit is "0", it is a data signal frame, and when this bit is "1", it is an error correction code frame.

Further, the latter half byte of the R channel of word 4 is a frame number (EFNO) area to which an error correction code is added, and the serial number and error correction of the frame of the data signal within the range where one error correction code is generated The serial number of the code frame is “1” for the first frame.
As a binary value. When the error correction code is not added, all bits are set to “0”.

The two bytes of the L channel of word 5 are used as a byte number (EBL) area of valid data in the frame, and a binary value indicating the byte number is provided.

Further, the R channel of word 5 and word 6 are all "0" for the time being as extension bits.

Then, a data portion of a total of 5728 bytes is provided in the subsequent words 7 to 1438, and a data signal from the bus (3) is sequentially provided by 4 bytes in each word.

Further, the word 1439 is used as an error detection code (EDC) part, and an error detection code (EDC) is generated for each of the data signals in the header part and the data part described above for a data string in which each data bit is viewed in a vertical direction. Provided.

Here, in the DAT format, the data of the L channel and the data of the R channel are alternately distributed to two tracks by 2 bytes and recorded. For example, tracks are formed on both sides of the drawing. It is indicated by the azimuth (±) of the head. Therefore, as described above, an EDC is generated for a data sequence in which each data bit is viewed in the vertical direction, thereby forming one frame.
An EDC can be generated for a book track.

Therefore, according to this format, it is possible to determine the remaining data to be erased by performing the EDC operation. That is, in the above-mentioned format, if one track remains unerased, every other data for generating the EDC will be different, and the EDC calculation will not be performed correctly. Therefore, by detecting this value, the remaining unerased data can be determined, and by making this frame an error, the error correction outside the DAT (1) can be reliably performed.

According to the above-described format, the synchronization section is provided, so that the synchronization between the controller (2) and the DAT (1) can be made free, and is particularly good even when the data amount of one frame fluctuates. Can be handled. However, since the above-mentioned synchronization pattern may appear in the data signal, it is necessary to scramble the data in the header section, the data section, and the EDC section by adding an arbitrary M sequence or the like. That is, in the controller (2), the data of the header part is formed with respect to the data signal from the bus (3), an EDC is generated from the header part, scrambled, a synchronization part is added, and the DAT (1) is added. Will be supplied to

Further, in the above-described format, since the EDC of the data for each frame is added, an error in the data in the frame can be detected outside the DAT (1).

 Thus, the data signal is formatted.

In the above-described apparatus, 2048-bit data can be recorded in each of the first subcode section and the second subcode section. Here, in the recording format of the audio signal, the 2048 bits are divided into packs of 64 bits each,
Information such as the time code of the signal recorded for each pack and the recording date and time is recorded.

Therefore, a data recorder can be assigned to this pack, and various controls can be performed using the two packs.

That is, FIG. 6 shows the structure of the pack for that purpose. In the figure, 64 bits of each pack are divided into 8 words of 8 bits each. The 4 bits on the MSB side of the first (first) word in each pack are used as an ITEM area. This area is common to the recording format of the audio signal, and the contents of the pack are written in the 4-bit binary code. Is displayed. Nine of the 16 codes of 4 bits are already determined for recording an audio signal, and any of the remaining seven patterns are determined for a data recorder and used, for example. The first of the two packs is "001
0 ", the second is" 0001 ", and the fifth word of the first word
The bit is set to “0”, and the three bits on the LSB side are provided with the same format ID as W2 described above.

The second word of the first pack is an area for displaying the state of the frame, and the same VF, area ID, and frame ID as W1 and W2 are provided.

The third to fifth words are used as a file number (FNO) area, and a binary value indicating a serial number of a file in data (save set) backed up at one time is provided.

The sixth and seventh words are save set numbers (SSNO)
The area is defined as an area, and a binary value indicating the number of backups from the start of use of the apparatus is provided in the total of 16 bits.

The eighth word is a parity for the first to seventh words.

The second to fourth words of the second back are a logical frame number (LFNO) area, and are provided with a binary value indicating the serial number of an effective frame from the beginning of the tape.

The fifth to seventh words are absolute frame numbers (AFN
O) It is an area, and a binary value indicating the serial number of the frame from the leading end of the tape is provided in these 48 bits,
The eighth word is used as a variance for the first to seventh words.

Therefore, by performing reproduction by identifying these ID codes and the like, extremely smooth reproduction can be performed.

In the above-described apparatus, information that can be formed by the controller (2) is provided in the header of the data section,
Information that can be formed on the (1) side is provided in the subcode section.

In the generation of the error correction code by the controller (2), in the DAT format, two inclined tracks formed by one rotation of the drum (11) are defined as one frame as shown in FIG. In the first half of one (+ azimuth) track of the frame, the even-numbered data of the left channel is in the first half, the odd-numbered data of the right channel is in the second half, and the other (-
Data is interleaved and recorded such as even-numbered data of the right channel in the first half of the track (azimuth) and odd-numbered data of the left channel in the second half. Note that C at the center indicates an error correction code added by DAT (1). Therefore, when generating the above error correction code,
As shown by dashed arrows in the drawing, odd-numbered or even-numbered data of one channel and even-numbered or odd-numbered data of the other channel are alternately extracted for each frame to form a data string. As a result, it is possible to generate an error correction code for the data string interleaved on the tape (12). By this tape (12)
In this case, it is possible to divide the error correction ability in the case where a lateral damage or the like occurs.

As a result, it is possible to improve the error correction ability in the case where a lateral scratch or the like occurs on the tape (12).

Thus, according to the above-described device, the DAT can be used as a data recorder. In this case, according to the above-described configuration, the rotary head drum (11) is rotated at, for example, 2000 rpm,
Data recording is performed at a very high speed of 192,000 bytes per second, and the recording medium consumed thereby can be extremely reduced. Further, in this case, according to the above-described configuration, it is possible to perform recording with a smooth error correction code added thereto, and thus it is possible to perform good data recording using this.

〔The invention's effect〕

According to the present invention, in a data signal of two tracks forming one frame of the DAT format, a predetermined error detection is performed on the entire data signal included in the two tracks forming these one frame. By generating the code, it becomes possible to easily detect the remaining erase of the data signal due to the head clog, etc., and thereby, it becomes possible to form a good data recorder using this DAT. .

[Brief description of the drawings]

FIG. 1 is a block diagram of an example of the present invention, and FIGS. 2 to 7 are diagrams for explaining the same. (1) is DAT, (2) is controller, (3) is bus,
(4) is an adapter, (5) is a host computer,
(6) a hard disk drive, (11) a rotating head drum, (12) a tape, (14) a digital signal processing circuit,
(16) is a switch, (18) is a system control circuit, (22) is a microcomputer, (23) is a DMA, (2)
4) is a memory, (25) is an error correction code generation circuit, and A and B are recording and reproducing heads.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Katsumi Inazawa 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Hiroshi Ishibashi 6-35, Kita-Shinagawa, Shinagawa-ku, Tokyo No. Sony Corporation

Claims (1)

(57) [Claims] A rotary head is provided, and two rotation tracks are formed on a recording medium by one rotation of the rotation head, and a data signal or a code signal is formed using the two tilt tracks as one frame. An apparatus which is formatted and recorded / reproduced for each frame, wherein a predetermined number of data signals included in two tracks forming the one frame of the data signal to be formatted are predetermined. A data recorder, comprising: means for generating an error detection code according to any one of claims 1 to 4, and recording means for recording the one-frame data signal together with the generated error detection code on the recording medium.