JP2624225B2 - Head seek control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a head positioning head seek control circuit for a floppy disk drive.

[0002]

2. Description of the Related Art In a floppy disk drive having a tunnel erase type head, it is necessary to determine the ON / OFF timing of an erase current with a certain time delay from the ON / OFF timing of a write gate. However, the erase timing differs depending on the physical shape of the head and the format of the floppy disk, and is not recognized by the controller.

In a conventional floppy disk drive, transmission of a seek command to a controller that arrives within a delay time of an erase timing following the turning off of a write gate is prohibited, or a seek command during an erase operation is ignored.

[0004]

Such a conventional floppy disk drive requires a circuit for gating the seek command transmission during the erase timing, and the load on the control program is inevitable. Occurs. Furthermore, if a seek command is sent during an erase operation due to a malfunction or an erroneous operation, data recorded on the floppy disk will be destroyed, causing serious trouble. Alternatively, if the seek command during the erase operation is ignored, the intended seek operation is not executed.

The present invention eliminates such a drawback and provides a head seek control circuit for a floppy disk drive capable of reducing the load for realizing the guard function on the controller side and reliably preventing data destruction. It is characterized by the following.

[0006]

According to the present invention, there is provided a head seek control circuit for generating an internal seek command signal used for a floppy disk drive, which receives a write gate signal and a seek command signal each time a seek command signal arrives. Circuit means for latching the level of the write gate signal to generate a seek command latch signal,
When the seek command signal arrives, the seek command latch signal is set to the first logical level when the write gate signal is at the level instructing the write operation, and when the write gate signal is not at the level instructing the write operation, the seek command is set. Circuit means for setting a latch signal to a second logic level; delay means for delaying a write gate signal to generate a delay signal; and gate means for receiving a seek command latch signal and a delay signal to generate an internal seek command signal. When the seek command latch signal is at the second logic level and the delay signal is not at a level instructing the write operation, the internal seek command signal is set to a level at which the seek command operation is executed, and the seek command latch signal is at the first logic level. Level and the delay signal is at the level that commands the write operation. When the at least one state, characterized in that a gate means for level to prohibit a seek command operate the internal seek command signal.

Therefore, in the heed seek circuit of the present invention, when the level of the write gate signal is at the level instructing that the write operation is being performed when the seek command arrives, the seek command latch signal becomes the first logical level, and as a result, The gate means outputs an internal command signal having a level for inhibiting the internal seek command operation. That is, the seek command command that arrives during the write operation is ignored.
On the other hand, when the level of the write gate signal is at a level at which the write operation is not commanded when the seek command arrives, the seek command latch signal is at the second logical level, and the delay signal is not at the level at which the write operation is commanded.
A seek operation is performed. However, if the seek command signal arrives immediately after the read command signal is inverted to the level that commands the write operation, the level of the delay signal is the level that commands the write operation. Thereafter, the seek command signal is internally set to a level instructing the seek command.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit connection diagram showing a configuration of a head seek control circuit of an apparatus according to the present invention. Latch circuit 1
The seek direction selection signal A is latched at the arrival timing of the seek command signal D, and the seek direction latch signal I is output. The inverter circuit 2 outputs a write gate inverted signal C obtained by inverting the write gate signal B.
The seek command latch signal F is output from the latch circuit 3 when the seek command signal arrives only when the write gate inversion signal C is at the high level. The erase timing generation circuit 4 outputs an erase gate signal G delayed by a predetermined time from the write gate signal B. The AND gate signal 5 outputs an AND gate output signal H obtained by gating the seek command signal F while the erase gate signal G is at the high level. In the latch circuit 6, the AND gate output signal H is latched in synchronization with the clock E, and the internal seek command signal J is output. The internal seek command output signal J is also input to the reset terminal of the latch circuit 3, and when the internal seek command signal J goes high, the seek command latch signal F is reset to the roll level.
The up / down counter 7 performs an up-count or down-count operation in synchronization with the timing of the internal seek command signal J in accordance with the level of the seek direction latch signal I. The decoder / driver circuit 8 outputs a stepping motor drive signal L corresponding to the output signal K of the up / down counter 7. The stepping motor 9 rotates in the forward or reverse direction according to the stepping motor drive signal L to position the head on a predetermined track.

FIG. 2 is a waveform diagram showing signal waveforms at various parts in FIG. Area I shows a state in which a seek command signal D arrives during a write operation.

That is, when the seek command signal D arrives when the write gate signal B is at the high level as the second level, the latch circuit 3 latches the low level as the first level and outputs the low level seek command latch signal. F
Is output. The AND gate 5 as a gate means for inputting the low-level seek command latch signal F outputs a low-level AND gate output signal H. The latch circuit 6 receiving this signal outputs a low-level internal seek command signal J.

Therefore, no seek operation is performed at this time. That is, in a general floppy disk controller, a seek command is not transmitted at the time of executing a write operation. Therefore, a seek command signal received at the time of a write operation is treated as an erroneous signal such as noise. No action is taken.

Area II is a state where the seek command signal D arrives when the write operation is not instructed, and shows a state where the erase gate signal G indicates that the write operation is being performed. That is, when the seek command signal D arrives when the write gate signal B is at the low level, the latch circuit 3 sets the seek command latch signal F at the high level.
Is output. At this time, the erase gate signal G generated by delaying the write gate signal indicates that the write operation is being performed and is at a high level. Therefore, the AND gate 5 outputs a low-level AND gate output H, and the latch circuit 6 also outputs a similar low-level internal seek command signal J. Thereafter, when the erase gate signal G is switched to a low level, the AND gate 5 outputs a high-level AND gate output H. Therefore, when a seek command arrives when a write command is not being performed and the erase gate signal indicates a write state, the internal seek command is prohibited and the internal seek command is not output until the erase gate signal ends the write state. Is executed.

Region III is a state where the seek command signal D arrives during a non-write operation, and shows a state where the erase gate signal G does not indicate that the write operation is being performed. That is, the seek command latch signal F
Is high, the erase gate signal G is low, and the AND gate 5 outputs a high-level AND gate output signal H. Upon receiving the signal, the latch circuit 6 outputs a high-level internal seek command signal J. Therefore, even when a write command is not being issued, a seek command that arrives when the erase gate signal does not indicate a write state is immediately executed.

[0015]

As described above, according to the present invention, a head seek control circuit of a floppy disk drive holds a seek command arriving during an erase operation in a latch circuit, and responds to the above-described seek command after the end of the erase operation. By having a function of executing a seek operation, there is an effect that the burden of realizing the guard function on the controller side is released, and an accident such as data destruction due to erroneous operation or erroneous operation can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit connection diagram showing a configuration of an apparatus according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing waveforms of signals of respective parts of the circuit shown in FIG.

[Explanation of symbols]

 1, 3, 6 Latch circuit 2 Inverter gate 4 Erase timing generation circuit 5 AND gate 7 Up / down counter 8 Decoder / driver circuit 9 Stepping motor A Seek direction selection signal B Write gate signal C Write gate inversion signal D Seek command signal E Clock F Seek command latch signal G Erase gate signal H AND gate output signal I Seek direction latch signal J Internal seek command signal K Counter output signal L Stepping motor drive signal

Claims (1)

(57) [Claims] A head seek control circuit for generating an internal seek command signal used for a floppy disk drive, wherein a write gate signal and a seek command signal are received, and the level of the write gate signal is increased each time the seek command signal arrives. Circuit means for latching the seek command latch signal, and when the seek command signal arrives, the write gate signal is at a level instructing that a write operation is being performed. Circuit means for setting the seek command latch signal to a second logic level when the write gate signal is not at a level instructing the write operation, and generating a delay signal by delaying the write gate signal Delay means for receiving the seek command latch signal and the delay signal; Gate means for generating the internal seek command signal, wherein the internal seek command signal is output when the seek command latch signal is at the second logical level and the delay signal is not at a level instructing the write operation. A level at which a seek command operation is executed; and when at least one of a state in which the seek command latch signal is at the first logical level and a state in which the delay signal is at a level instructing a write operation, the internal seek command is executed. A gate means for setting a signal to a level for inhibiting a seek command operation.