JP2623973B2 - Video processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video processing apparatus for enlarging or reducing a video in a vertical direction, and more particularly, to a video processing apparatus for writing or reading a video memory for storing video data by controlling an address in a vertical direction. The present invention relates to a video processing device that performs enlargement / reduction.

BACKGROUND ART The present invention is based on the premise that a luminance signal in a composite video signal CS is once written as video data in a video memory, and then read out again and displayed on a monitor. And
By performing address control when writing and reading video data to and from the video memory,
Achieve reduction.

FIG. 1 is a block diagram showing a conventional video processing device. The PLL (phase lock loop) circuit 9 is a circuit for generating a line clock signal for incrementing a vertical address of the video memory 7. A vertical synchronizing signal separated and extracted from the composite video signal CS is input to a reference input terminal 1 (a) of the phase comparator 1 in the PLL circuit 9. The signal output from the phase comparator 1 is converted into a voltage value by a loop filter 2 and applied to a VCO (voltage controlled oscillator) 3. The VCO 3 generates a clock signal having a frequency corresponding to the input signal voltage.
Divided by M, phase comparison input terminal 1 of phase comparator 1
This is fed back to (b). With this configuration, the line clock signal LC having the period Tx synchronized with the vertical synchronization signal
K can be obtained (however, Tx = Tv / M; Tv is the period of the vertical synchronization signal).

In this conventional video processing apparatus, the dividing ratio M of the frequency divider 8 is set to a lock range (upper limit and lower limit frequency variable of the frequency of the lock state) from several tens to several thousands, so that the enlargement in the vertical direction can be achieved. The reduction has been achieved. But in general PL
When the L circuit is used, the lock range is at most 10
It is more stable to set the range to about twice, and it is desired in the current state of the art to construct a stable PLL circuit by narrowing the lock range as much as possible.

FIG. 2 is a diagram showing the image fluctuation phenomenon in the conventional device shown in FIG. An image display area 12 is displayed on the monitor 11, and a vertical image fluctuation state 13 that occurs when the lower portion of the image display area 12 is enlarged or reduced in the vertical direction.

FIG. 3 is a diagram showing a video flicker phenomenon in the conventional device. Due to the jitter (frequency noise that goes on a certain frequency) due to the phase fluctuation of the line clock signal applied to the video memory unit 7, a vertical line jump phenomenon occurs in the video memory 7 and a horizontal line appears on the monitor. The video flicker 14 appears.

FIGS. 4 and 5 are diagrams showing the relationship between the line data in the video memory, the horizontal synchronizing signal and the line clock signal, respectively. The arrow of the line clock signal 19 indicates the timing of increment of the vertical address of the video memory 7, and the arrow of the horizontal synchronization signal 18 indicates the line clock 19.
Indicates the timing for determining the incremented vertical address (line position). Here, the description will be made on the assumption that the lines 15, 16, 17 are output from the video memory 7. In FIG. 4, the vertical address is incremented by one line at the timing of the arrow of the line clock 19 after the arrow of the horizontal synchronization signal 18, and the address is determined by the arrow of the next horizontal synchronization signal 18.
15, 16, 17 are displayed sequentially. However, in FIG. 5, the arrow of the line clock signal 19 is inserted twice between the first arrow and the second arrow of the horizontal synchronization signal 18. Therefore, before the vertical address is determined by the second arrow of the horizontal synchronization signal 18, the vertical address is incremented twice. For this reason, the line 17 is read at the timing at which the reading of the line 16 shown in FIG. 4 should be performed, and the display of the line 16 is omitted. As described above, when there is a jitter in the line clock signal 19, the state shown in FIG. 4 and the state shown in FIG. 5 are repeatedly displayed, and an image flicker 14 as shown in FIG. 3 occurs.

In this conventional device, the reference input terminal 1 of the PLL circuit 9 is
(A) uses a vertical synchronizing signal having a frequency as slow as several tens of hertz (Hz).
Is set to several tens to several thousands, and the lock range of the frequency divider 8 is widened, so that the constant design of the loop filter 2 is not easy, and large jitter appears in the line clock signal. As a result, there are places where vertical addresses are skipped over the video memory or not, resulting in an ugly screen as a video flicker phenomenon due to horizontal lines. Since it is generally difficult to accurately determine the jitter from the calculation formula due to various complicated conditions, when the actual measurement value is obtained, a value of 5 to 10 [μS] was observed for the jitter.

Also, every time the frequency division ratio M for changing the image is enlarged or reduced, the expansion and contraction in the vertical direction are repeated by the vibration based on the damping factor ζ (braking coefficient) of the PLL circuit 9. In other words, during the acquisition time of the PLL circuit 9 (the time until the frequency difference locks), an image becomes ugly as the vertical image fluctuation decreases.

The following is a calculation formula for obtaining an acquisition time which causes a vertical image fluctuation phenomenon.

Assuming that the control voltage width of the VCO 3 is Vd [V], the gain constant kΦ of the phase comparator 1 is kΦ = (Vd / 2) / 2π [V / rad] (Equation 1) The control voltage width of the VCO 3 is Fd [ Hz], the conversion gain of VCO3
KV is represented by Kv = Fd · 2π / Vd [rad / V · s] (Equation 2) The loop gain K can be expressed by K = KΦ · KV (Equation 3), and in the case of an active filter, τ1 =
If C · R1, SQRT = SQUARE ROOT (√), the natural angular frequency ωn is as follows: ωn = SQRT (K / τ1) (Equation 4)

On the other hand, when a general ζ = 0.7 is selected, ωn · t = 4.5
About.

Therefore, the natural angular frequency ωn where the acquisition time is t is: ωn = 4.5 / t (Equation 5)

Therefore, when (Equation 5) is substituted into (Equation 4), the acquisition time t becomes t = SQRT (20 · τ1 / K) (Equation 6), and the acquisition time t is directly affected by the loop gain K. I understand. Therefore, when Vd in the loop gain K is constant, the acquisition time t is greatly affected by the output frequency width Fd of the VCO3.

DISCLOSURE OF THE INVENTION An object of the present invention is to minimize the jitter of a PLL circuit and the acquisition time of a PLL circuit, and to eliminate the image flicker and the image fluctuation phenomenon.

In order to achieve this object, the video processing device of the present invention comprises:
A video memory for storing a luminance signal in a composite video signal is provided.In a video processing device for vertically enlarging / reducing a video, a horizontal synchronization signal of the composite video signal is used as an input signal, and A PLL circuit that outputs a phase-synchronized signal and a frequency divider that divides the output signal of the PLL circuit by 1 / N2 are provided. The output signal of the frequency divider is a line that advances the vertical address to a video memory. It is input as a clock, and the dividing value N1 of the internal divider in the PLL circuit can be changed by an external command. The dividing value N2 of the divider is one cycle of the vertical synchronizing signal of the composite video signal. Is set to the number of horizontal synchronization signals in the PLL circuit, and the output signal of the PLL circuit which is the input signal of the frequency divider is 1 / N1 of the period of the horizontal synchronization signal.
Cycle.

Since a high frequency horizontal synchronizing signal is used instead of the vertical synchronizing signal of the video signal as the input signal of the PLL circuit, the jitter and the acquisition time t of the PLL circuit can be reduced. Therefore, the frequency of the line clock signal given to the video memory is changed by changing the frequency division value N1 of the internal divider in the PLL circuit, and this causes video flickering and image fluctuation even when the video is enlarged or reduced. Is unlikely to occur.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a conventional video processing device.

FIG. 2 is a diagram showing an image fluctuation phenomenon by the conventional device of FIG.

FIG. 3 is a diagram showing an image flickering phenomenon by the conventional device of FIG.

FIGS. 4 and 5 are diagrams showing the relationship between line data in a video memory, a horizontal synchronizing signal, and a line clock in a conventional device, respectively.

FIG. 6 is a block diagram showing a video processing apparatus according to one embodiment of the present invention.

7A, 7B and 7C are timing charts each showing the operation of the present embodiment.

 FIG. 8 is a view for explaining enlargement and reduction of an image.

BEST MODE FOR CARRYING OUT THE INVENTION In FIG. 6, a synchronizing signal separator 61
This is a circuit for separating the vertical synchronization signal VS and the horizontal synchronization signal HS from CS. The PLL circuit 62 includes a phase comparator 63, a low-pass filter (LPF) 64 as a loop filter, a voltage controlled oscillator (VCO) 65, and a frequency divider 66. The reference input terminal 63a of the phase comparator 63 receives the horizontal synchronizing signal HS from the synchronizing signal separator 61.
Signals from 6 are input. The output signal of the phase comparator 63 is passed through a low-pass filter 64 to a voltage-controlled oscillator 65.
Is input to The voltage control oscillator 65 outputs a clock signal CK having a frequency according to the input voltage. This clock signal
CK is an output signal from the PLL circuit 62 and is also supplied to an internal frequency divider 66, where the frequency is divided by 1 / N1 and fed back to the phase comparator 63. The divider 66 has a division value N1
Is provided with an N1 storage unit 66-1. The value of the frequency division value N1 is stored in the N1 storage unit according to a command from an external device such as a personal computer 74.
It can be set arbitrarily by changing the contents of 66-1.

The frequency divider 67 is a circuit that divides the output signal of the PLL circuit 62 into 1 / N2. This frequency divider 67 has a frequency division value N2 similarly to the frequency divider 66.
Is provided.

The video memory 70 includes a vertical address counter 71, a vertical address storage unit 72, and a video storage unit 73. The video storage unit 73 stores the luminance signal in the composite video signal CS as digital data, and here a so-called VRAM (video random access memory) is used. The vertical address counter 71 is a counter that counts a signal from the frequency divider 67 (hereinafter, this signal is referred to as a line clock signal LCK), and is reset by a vertical synchronization signal VS from the synchronization signal separator 61. The vertical address storage unit 72 receives the count value output from the vertical address counter 71 and holds the coefficient value at the input timing of the horizontal synchronization signal HS from the synchronization signal separator 61. The output value of the vertical address storage unit 72 becomes a vertical address signal for the video storage unit 73.

Next, the operation of the video processing circuit thus configured will be described.

First, the composite video signal CS is input to the synchronization signal separator 61, where the horizontally separated synchronization signal HS is separated by the PLL circuit 62.
Is input to the reference input terminal 63a of the phase comparator 63. At this time, the vertical synchronization signal VS also separated by the synchronization signal separator 61 resets the vertical address counter 71 and the vertical address storage unit 72 in the video memory 70.

In the PLL circuit 62, the clock signal CK output from the voltage controlled oscillator 65 is input to the frequency divider 66. The frequency divider 66 counts up the internal counter every time the clock signal CK is input. When the value reaches N1, a carry output signal is generated and sent to the phase comparison input terminal 63b of the phase comparator 63. .
The phase comparator 63 obtains a phase difference between two input signals input to the input terminals 63a and 63b, and the phase difference is sent to the low-pass filter 64 to be converted into a voltage. In the voltage controlled oscillator 65, the frequency of the clock signal CK to be output changes according to the converted voltage. This change proceeds so that the phase difference between the input signal of the reference input terminal 63a and the input signal of the phase comparison input unit 63b is minimized. When the phase difference becomes zero, a stable state, that is, a locked state is established. In this way, the clock signal CK output from the PLL circuit 62 in the locked state is divided by the frequency divider 67 into 1 / N2 to become a line clock signal LCK, and this line clock signal LCK is a horizontal synchronization signal. The vertical address counter 71 is incremented regardless of the HS. The count value of the vertical address count 71 is always given to the vertical address storage unit 72. The vertical address storage unit 72 holds this at the timing of the horizontal synchronization signal HS and gives it to the video storage unit 73 as a vertical address signal. Note that the value of N2 is set to the number of horizontal synchronization signals HS in one cycle of the vertical synchronization signal VS.

7A to 7C are timing charts for explaining the operation of the present embodiment in more detail. In FIG. 7A, (a), (b), and (c) are vertical synchronizing signals VS,
The horizontal synchronization signal HS and the line clock signal LCK are shown. 7B
FIG. 7A shows a horizontal synchronizing signal HS obtained by expanding FIG. 7A in time, and FIG. 7B shows a corresponding VCO output signal (clock signal CK). Fig. 7C (a) (b)
Fig. 7B is an expanded display of Figs. 7A and 7B. The period of the vertical synchronization signal VS, that is, the vertical synchronization period is Tv,
The cycle of the horizontal synchronization signal HS, that is, the horizontal synchronization period is Th, the cycle of the line clock signal LCK is Tx, and the cycle of the VCO output signal CK is Th.
Assuming Ti, Ti = Th / N1 (Equation 7), which is transformed into Th = Ti × N1 (Equation 8).

 The cycle Tx of the line clock signal LCK is Tx = Ti × N2 (Equation 9).

By the way, since the value of N2 is set to the number of horizontal synchronizing signals HS in one cycle of the vertical synchronizing signal VS, Tv = Th × N2 (Equation 10) holds. Therefore, when (Equation 8) is substituted into (Equation 10), Tv = Ti × N1 × N2 (Equation 11) is obtained. By substituting (Equation 9) into (Equation 11) and transforming Tx, Tx = Tv / N1 (Equation 12)

From this (Equation 12), the frequency dividing value M of the frequency divider in the PLL circuit of the conventional video processing device using the vertical synchronization signal VS as the reference input signal of the PLL circuit and the frequency dividing value of the frequency divider 66 of the present embodiment. It can be seen that N1 has the same significance in relation to the cycle of the line clock signal LCK. That is, the line clock signal LC
K can be changed independently of the horizontal synchronizing signal HS, so that the image can be enlarged or reduced.

FIG. 8 is a diagram for explaining enlargement and reduction of an image. First, a case where data written in the video storage unit 73 is read will be described. Here, FIG.
Indicates the content of the video data in the video storage unit 73. For example, if N1 is set so that the frequency of the line clock signal LCK is twice the frequency of the horizontal synchronization signal HS, the video data in the vertical direction of the video storage unit 73 is read out every other line. For this reason, as shown in FIG. 3B, video data thinned out line by line in the vertical direction is obtained, thereby obtaining a video reduced in half in the vertical direction.

In order to obtain a double-enlarged video, if the frequency of the line clock signal LCK is set to be half of the horizontal synchronization signal HS, the same video data is obtained adjacently in the vertical direction. As a result, an image enlarged twice in the vertical direction is obtained. In this case, contrary to the above, FIG. 13B shows the content of the video data in the video storage unit 73, and FIG. 14A shows the read video.

FIG. 9A shows the contents of the video signal. When the video is reduced to half in the vertical direction and written to the video storage unit 73, the frequency of the line clock signal LCK is set to the horizontal level. Set so as to be 1/2 times the synchronization signal HS. By writing the video signal at every other row in the vertical address of the video storage unit 73, the video data in the vertical direction is thinned out and reduced by a factor of 1/2 in the vertical direction, as shown in FIG. Such video data is written into the video storage unit 73.

As described above, the frequency of the line clock signal LCK that defines the vertical resolution of the video can be arbitrarily set by the N1 value stored in the storage unit 66-1, as described above. Arbitrary enlargement and reduction are possible.

INDUSTRIAL APPLICABILITY According to the present invention, an image can be arbitrarily enlarged or reduced. In addition, since the horizontal synchronizing signal HS having a higher frequency than the vertical synchronizing signal VS is used as the reference input signal of the PLL circuit that creates the line clock signal to be applied to the video memory, the loop gain K of the PLL circuit is increased. be able to. Accordingly, the acquisition time is reduced to 1 / SQRT (several hundreds) of the conventional art, and vertical image fluctuation during vertical enlargement / reduction is less likely to occur. Also,
Even if the lock range is extended as before, the jitter is 1
It is much smaller, up to 100 [nS]. Therefore, image flicker due to horizontal lines due to jitter can be removed.

Claims (3)

(57) [Claims] A video memory for storing a luminance signal in a composite video signal, wherein the video processing apparatus performs enlargement / reduction of a video in a vertical direction. A horizontal synchronization signal of the composite video signal is used as an input signal. A PLL circuit that outputs a signal that is phase-synchronized with the horizontal synchronization signal,
A frequency divider for dividing the output signal of the PLL circuit by 1 / N2, wherein the output signal of the frequency divider is input to the video memory as a line clock for increasing the vertical address thereof, and The dividing value N1 of the inner divider can be changed by an external command. The dividing value N2 of the divider is the number of horizontal synchronizing signals in one cycle of the vertical synchronizing signal of the composite video signal. Wherein the output signal of the PLL circuit, which is an input signal of the frequency divider, has a cycle of 1 / N1 of the cycle of the horizontal synchronization signal. 2. The video processing apparatus according to claim 1, wherein said internal divider includes a storage unit for storing a frequency division value based on an external command. 3. The video memory includes: a video storage unit for storing the luminance signal; a vertical address counter incremented by an output signal of the frequency divider; and a count value of the vertical address counter as the horizontal synchronization signal. The video processing device according to claim 1, further comprising: a vertical address storage unit that outputs the address of the video storage unit in synchronization with the vertical address storage unit.