JP2623011B2 - Multi-screen display device and memory control method - Google Patents

Description

The present invention relates to a memory control method. In particular, the present invention relates to a memory control method for an image memory circuit called an enlargement circuit used in a multi-vision (multi-screen display device).

(B) Conventional technology An image enlargement multi-screen display device is disclosed in Japanese Patent Publication No. 64-6592 (H04N
5/44) and JP-A-57-101481 (H04N5 / 68), etc., one example of which is well known with reference to FIG.

In FIG. 5, the description of the color signal processing is omitted for ease of explanation.

In FIG. 5, (10) is a video disk for outputting a video signal, and a video from this video disc (10) is shown on a color television receiver (12).

(14) is a video signal enlargement device. (16) is a display unit including a plurality of color television receivers (16a) to (16i).

The video signal enlargement device (14) is adapted to enlarge the video signal from the video disc (10) corresponding to the color television receivers (16a) to (16i).
4i). These expansion circuits (14a) to (14i)
The screen is enlarged by storing the input video signal and reading it at a speed lower than the writing speed. That is, as shown in FIG. 6, in the horizontal scanning direction of the video signal, the input video signal shown in FIG.
It is enlarged as shown in FIG. In the case of FIG. 5, since the system is a 3 × 3 system, the data is read out at 1/3 speed. In the vertical scanning direction, the same enlarged video signal is read out three times.

(17) is a switch matrix circuit provided in the multi-vision system, which selects and outputs a combination of a video signal from another video signal generator (not shown) and a video signal from a video signal enlarging device.

In the enlargement circuit (14a), (18) is the A / D conversion circuit,
(20) is a video memory for storing and outputting input video data. (22) is a memory control circuit. (22a) is a write control circuit, and (22b) is a read control circuit. (24) is a timing signal generation circuit for detecting horizontal and vertical synchronizing signal components of the input video signal and operating each circuit in synchronization. Note that the timing signal generation circuit (2
4) also outputs a clock signal. The timing signal generation circuit (24) also outputs a blanking period signal (BLNK) and a composite synchronization signal (C.SYNC) for a memory read signal. (26) is a pedestal level value output circuit.
A switch (28) switches to the pedestal level value output circuit (26) when the timing signal generation circuit (24) outputs a blanking period signal (BLNK).

(30) is a D / A conversion circuit. (32) is an adder for adding a synchronization signal.

Reference numeral (34) denotes an enlargement switching control circuit which controls the read control circuit (22b) of each of the enlargement circuits (14a) to (14i) to change the enlargement portion and enlargement ratio, for example, as shown in FIG. Display is also performed.

 The above operation will be briefly described.

The video signal from the video disk (10) is input to the enlargement device. Each enlargement circuit (14a) to (14
In i), a video signal is input, and a synchronization timing is detected by a timing signal generation circuit (24). The input video signal is converted into digital video data by an A / D conversion circuit (18).

The write control circuit (22a) specifies a write address to write this video data in a predetermined memory area of the video memory (20) in synchronization with the synchronization component of the input video signal by the timing signal generation circuit (24). FIG. 8 shows a video memory area. (B) is a write memory area in which the input video signal is written.

Then, the read control circuit (22b) sets a read speed and a read start address according to the enlargement switching control circuit (34) enlargement ratio and enlarged portion. At the same time, the read timing is adjusted by the blanking period signal (BLNK) of the timing generation circuit (24) and the composite synchronization signal (C.SYN).
Synchronize with C). The read memory area (C) by the read control circuit (22b) is as shown in FIG. 8 (C), for example.

By the way, when projecting the screen enlarged in this way,
Due to the variation of the synchronization circuit system and the deflection circuit system of each television receiver, an enlarged image as shown by the solid line in FIG. 9 is obtained.

For this reason, as shown by the broken line in FIG.
Correction is needed. Since this correction corrects the positions of the images on both sides of the joint (frame) of the television receiver, it is temporarily referred to as “joint correction”.

This joint correction may be performed by adjusting all of the television receivers, but is usually corrected by the video signal enlargement device (14). When the joint correction is performed by the video signal enlarging device (14), it is performed by slightly changing the start address of reading from the video memory (20).

By slightly changing the read start address in the V and H directions shown in FIG. 8, the read area is minutely changed to change the vertical and horizontal positions of the enlarged image projected on the television receiver.

That is, the user adjusts the read control circuit in each enlargement circuit while watching the enlarged images projected on the plurality of television receivers, changes the data read start address, and performs the joint correction. .

(C) Problems to be Solved by the Invention However, if a memory area where data is not written (corresponding to FIG. 8 (a) ') is read by this joint correction, naturally, indefinite data is output. You. If the value of the indefinite data is equal to or less than the pedestal level value as shown in FIG. And so on.

The present invention has been made in view of the above points, and provides a video enlarging circuit that does not generate a synchronous flow in a television receiver (16) even when reading outside a video writing area of a memory (20). Things.

That is, claim 1 of the present invention provides a multi-screen display device that removes a signal of an erroneous synchronization signal level so as to prevent loss of synchronization when video data outside the write memory area (a) ′ is read. Things.

A second aspect of the present invention is that the outside of the write memory area (a) '
The present invention provides a method for controlling an image memory circuit such as an enlargement circuit for removing data of an erroneous synchronization signal level so that synchronization is not lost when the video data is read out.

A third aspect of the present invention is an image memory circuit such as an enlargement circuit for writing predetermined level data outside the write memory area (a) in advance so as to prevent loss of synchronization when video data outside the write memory area is read. Is provided.

(D) Means for Solving the Problems The present invention provides an A / D conversion means (18) for A / D converting an input video signal, and a plurality of image memory circuits ( Video data bus (4
2), a memory (20) provided in the image memory circuit (14a) and storing the video data; and a memory (20) provided in the image memory circuit (14a) to control writing and reading of the memory (20). A memory control means (22), which is provided in the image memory circuit (14a), and DA-converts video data read from the memory (20) to form an output signal of the image memory circuit (14a) In a multi-screen display device comprising: a DA conversion means (30); and a plurality of television receivers (16a)... (16i) for displaying outputs of the plurality of image memory circuits (14a). Comparing means (36) provided in a memory circuit (14a) for comparing a value of the video data read from the memory with a predetermined level value; and provided in the image memory circuit (14a); Controlled by the output of the comparing means (36), The DA conversion circuit (30)
And a replacing means (28) for setting the value of the video data output to the predetermined level value.

Also, the present invention provides a video signal memory in which a write memory area (b) specified by a write address for writing an input video signal to a memory and a read memory area (c) 'specified by a read address are different. In the control method, at the time of reading the read memory area (a) ′ which is out of the write memory area (b), at least the minimum data value of the read video signal is limited.

Also, the present invention provides a video signal memory in which a write memory area (b) specified by a write address for writing an input video signal to a memory and a read memory area (c) 'specified by a read address are different. The control method is characterized in that the read memory area (a) 'which is out of the write memory area (b) is initialized to a predetermined value in advance.

(E) Operation According to claim 1, data of a synchronization signal level in the read video data is detected by the comparing means (36), and this data is detected by the switch (replacement means) (28). Has been replaced with

In claim 2, the minimum level of the read video data is limited.

According to the third aspect, the predetermined data value is written in advance in the write memory area.

(F) Embodiment A first embodiment of the present invention will be described with reference to FIG.
The same parts as those in FIGS. 5 to 10 are denoted by the same reference numerals.

In the first embodiment, the output of undefined data is prohibited.

In FIG. 1, (36) is a comparison circuit. The comparison circuit (36) compares the video data with the pedestal level, and outputs a signal when the video data value is lower than the pedestal level value.

(38) is an OR gate. This or gate (38)
Is the output of the comparison circuit (36) and the blanking period signal (BL
NK) or is output.

(40) is joint adjustment means. The joint correcting means (40) is provided with the read control circuit (22) as described above.
b) is controlled to vary the read start address.

According to this circuit, when the unfixed data is generated in the video data read from the memory (20) due to the joint correction and the value of the unfixed data is lower than the pedestal level value, the comparison circuit (36) is set to the high level. Output a signal.
With this high level signal, the output of the OR gate (38) also becomes high level. As a result, the switch (28) switches to the pedestal level value output circuit (26). Thus, output of indefinite data equal to or less than the petistal level value is prevented.

2 and 3 show a second embodiment of the present invention. In the second embodiment, an input A / D converter and a timing signal generation circuit are shared, and addition of a synchronization signal is performed in a digital stage.

In FIG. 2, (42) is a common bus for video data,
(44) is a common bus for synchronous data. (46)
This is a sync level value output circuit. (48) is a switch for creating a sync level. The switch (48) is switched to the sync level value output circuit (46) by the composite synchronizing signal (C.SYNC) input from the timing signal generating circuit (24) via the synchronizing data common bus (44). Can be

 (14a) to (14i) are enlargement circuits.

 FIG. 3 shows a waveform diagram of each part.

FIG. 4 shows a third embodiment of the present invention. The third embodiment is to prevent the occurrence of indefinite data itself. That is, this is a technique of writing the clamp level value data in the conventional indefinite data area (corresponding to A in FIG. 8) when the power is turned on.

In FIG. 4, reference numeral (50) denotes an initialization control circuit.
(52) is a changeover switch.

The initialization control circuit (50) detects power-on and the like, and switches the changeover switch (5) for a certain period from this detection period.
2) Switch to the clamp level value output circuit (26). At the same time, the write control circuit (22a) is controlled to write the data of the clamp level value to all the memory areas. Thereafter, the initialization control circuit (50) stops operating, the changeover switch (52) switches to the AD conversion circuit (18) side, and the write control circuit (22a) operates normally as before. .

In the third embodiment, the write control circuit (22a)
Must be provided with a function of changing the write address area by the output of the initialization setting circuit (50). In addition, in order to simplify the control of the memory, it is better to configure the memory with an SRAM. Therefore, the cost of the third embodiment is high. In the third embodiment, the memory area to be initialized only needs to cover the variable read area, and it is not necessary to initialize the entire memory area.

In the first and second embodiments, both the reference level for the comparison circuit (36) and the predetermined level for replacement use the output of the pedestal level value output circuit (26), and the circuit is also used. This may be provided individually.

(G) Effects of the Invention According to the first aspect, in the multi-screen display device, the synchronization flow at the time of joint correction can be prevented, so that joint correction is facilitated.

According to the second aspect, it is possible to prevent an erroneous synchronization signal from being output in an image memory circuit such as an enlargement circuit.

According to the third aspect, even if data outside the write memory area is read, no inconvenience occurs because the data in this area is at a predetermined level in advance.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention. FIG. 2 is a view showing a second embodiment of the present invention. FIG. 3 is a diagram showing waveforms at various parts in FIG. FIG. 4 is a view showing a third embodiment of the present invention. FIG. 5 is a diagram showing a conventional example. FIG. 6 is a diagram for explaining the principle. FIG. 7 is a diagram for explaining a conventional example. FIG. 8 is a diagram showing a memory area. Ninth
The figure is a diagram for explaining joint correction. FIG. 10 is a diagram for explaining a synchronization flow. (18) A / D conversion circuit (A / D conversion means), (14a) to (14i) ... Enlargement circuit (image memory circuit), (42) Video data bus, (20) Video Memory (memory), (22) Memory control circuit (memory control means), (30) D / A conversion circuit (D / A conversion means), (16a) to (16i) TV receiver , (36)... Comparison circuit (comparison means), (28)... Switch (replacement means), (b)... Write memory area, (c) (c) '... read memory area, (a)' ... A read memory area outside the write memory area.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Jun Niwa 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Motoaki Asao 2--18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Mitsunobu Enomoto 2--18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Kiyoshi Matsumoto 2-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Inside Electric Co., Ltd. (72) Inventor Tamiko Hirose 2-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (3)

(57) [Claims] An A / D converter for A / D-converting an input video signal, and video data from the A / D converter are distributed to a plurality of image memory circuits (14a) to (14i). Video data bus (42)
A memory (20) provided in the image memory circuit (14a) and storing the video data; and a memory control means (22) provided in the image memory circuit and controlling writing and reading of the memory (20). )
Provided in the image memory circuit (14a), and the memory (2
0) DA conversion means (30) for DA-converting the video data read out from the image data to form an output signal of the image memory circuit (14a); and outputs the outputs of the plurality of image memory circuits (14a). A multi-screen display device comprising a plurality of television receivers (16a)... (16i), wherein the video data is provided in the image memory circuit (14a) and read from the memory. A comparison means (36) for comparing the value of the video data with a predetermined level value to output that the video data is equal to or less than the predetermined level value; and a comparison means (36) provided in the image memory circuit (14a). ) A replacement means (28) which is controlled by an output and sets the predetermined level value when the value of video data output to the DA conversion circuit (30) is equal to or less than the predetermined level value. Screen display device. 2. A read memory area for writing an input video signal into a write memory area (b) narrower than the entire memory area of the memory, wherein the read memory area covers a smaller area than the write memory area (b). In the memory control method for a video signal to be read from the read area (c) ', which is variable in the range, the read memory area (b)' which is outside the write memory area (b) is read. A memory control method, wherein when a data value of a video signal is lower than a predetermined value, the video signal is replaced with the predetermined value and output. 3. A read memory area for writing an input video signal into a write memory area (b) narrower than the entire memory area of the memory, wherein the read memory area covers a smaller area than the write memory area (b). In a memory control method for a video signal to be read from a read area (c) 'which is variable in a range of an area, at least a part of the entire memory area of the memory outside the range of the write memory area (b) is determined in advance. A memory control method characterized by initializing to a predetermined value.