JP2613960B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit.

[Conventional technology]

A conventional semiconductor integrated circuit includes a variable capacitance diode having a PN junction formed by P-type and N-type impurity diffusion layers.

Generally, the reverse applied voltage applied to the PN junction
Since the width of the depletion layer at the junction changes, the capacitance changes.
By utilizing such properties, different capacitances can be obtained by applying voltages in the opposite direction.

[Problems to be solved by the invention]

A conventional semiconductor integrated circuit has an N-type substrate on a P-type silicon substrate.
Type epitaxial layer is formed, and then, after a photolithography step and a step of introducing a P-type impurity such as boron, thermal diffusion is performed to determine the concentration profile of the introduced P-type impurity. It is created through a wiring process.

As described above, in a variable capacitance diode using a PN junction, the expected change in capacitance with respect to the reverse
It is determined by the concentration profiles of the P-type impurity diffusion layer forming the junction and the N-type epitaxial layer.

At present, in the impurity introduction process, the variation of the impurity introduction amount within the wafer surface is as large as about 7%, and mass production of a 5-inch or 6-inch wafer is particularly impossible.

In the thermal diffusion step after the introduction of the P-type impurity, the diffusion state of the P-type impurity varies due to the difference in the concentration profile of the thermal diffusion furnace, so that the final P-type impurity concentration profile varies.

As described above, there is a disadvantage that the capacitance of the formed capacitor varies greatly between products in the wafer surface and between the rods due to variations in the concentration profiles of the epitaxial layer and the P-type impurity diffusion layer.

[Means for solving the problem]

A semiconductor integrated circuit according to the present invention includes a first MOS capacitor, a plurality of MOS transistors connected in parallel to one end of the first MOS capacitor and having threshold voltages sequentially set to different values, and each of the MOS transistors. It comprises a plurality of second MOS capacitors connected in series and connected to the other end of the first MOS capacitor.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

As shown in FIG. 1, a series connection of the MOS transistors Q _1, MOS capacitor 2 across the MOS capacitor 1, the series connection of the MOS transistor Q ₂ and the MOS capacitor 3, the series connection of the MOS transistors Q ₃ and MOS capacitor 4 Each is connected in parallel.

Here, the threshold voltage of the MOS transistors Q ₁ , Q ₂ , Q ₃ is V
_TQ1, and V _TQ2, V _TQ3, C ₁ to capacitance of the MOS capacitor 1,2,3,4,
Assuming that C ₂ , C ₃ and C ₄ , the circuit capacity changes as follows in the next four sections of the input voltage V.

When _{0 ≦ V ≦ V TQ1 C 1} V TQ1 ≦ V < When _{C 1 + C 2 + C 3} V ≧ V TQ3 when _{C 1 + C 2 V TQ2 ≦} V <V TQ3 when _{V TQ2 C 1 + C 2 +} C 3 + C ₄ Therefore, in the circuit, the capacitance of the entire circuit fluctuates in four steps in the four sections of the input voltage V.

FIG. 2 is a sectional view of a semiconductor chip shown in the order of steps for explaining a method of manufacturing a semiconductor integrated circuit according to a first embodiment of the present invention.

First, as shown in FIG. 2 (a), LOCOS (local oxi
A field oxide film 12 having a thickness of about 60 nm to 100 nm is formed on the surface of a P-type silicon substrate 11 by using a dation of silicon method to partition an element formation region. Next, the surface of the element formation region is thermally oxidized to form a gate oxide film 13. Gate oxide film 13 has a thickness of 30 nm to 50 nm. Then, an impurity diffusion layer 14 for determining the threshold voltage of the MOS transistor is formed in the MOS transistor formation region by using lithography technology and ion implantation technology. Further, an N-type impurity such as phosphorus is introduced into a region where a MOS capacitor is formed by using a lithography technique and an ion implantation technique. The dose is about 1 × 10 ¹³ cm ^-2 and the acceleration energy is
Drive in at about 100keV.

Next, as shown in FIG. 2B, a polycrystalline silicon film is deposited on the entire surface of the wafer to a thickness of about 0.4 μm by a low pressure CVD method, and then selectively etched to form a gate electrode 16 of the MOS transistor. Then, the upper electrode 17 of the MOS capacitor is formed.

Next, as shown in FIG. 2 (c), an N-type impurity is ion-implanted using the gate electrode 16 and the upper electrode 17 as a mask.
Contact area corresponding to the outlet for the source / drain region 18 of the MOS transistor and the lower electrode of the MOS capacitor
Form 19. As for the introduction of N-type impurities, arsenic ions are implanted at an acceleration energy of 70 keV and a dose of about 1 × 10 ¹⁶ cm ⁻² . On the other hand, P ⁺ -type diffusion layer 20 is formed by introducing boron as an electrode for suppressing the potential of the substrate. Regarding the introduction of impurities, the acceleration energy is 50 keV and the dose is 1 × 10
¹⁶ cm ^-2

Next, as shown in FIG. 2 (d), a silicon oxide film 21 is deposited on the entire surface by a normal pressure CVD method, a predetermined impurity diffusion layer region is opened by a lithography process, and an aluminum wiring 22 is formed by a sputtering method. It is formed using a lithography technique.

By forming a combination of a MOS transistor and a MOS capacitor in which only the impurity concentration of the impurity diffusion layer 14 is changed in the same process as the method for manufacturing the MOS transistor and the MOS capacitor described with reference to FIGS. Thus, a series connection circuit of MOS transistors and MOS capacitors having different threshold voltages can be formed.

 FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In this case, seven of the MOS transistors Q _1, Q _2, ..., and Q _7, 8
.., 8. First
In the embodiment, the lithography process and the impurity introduction process for determining the same number of threshold voltages as the number of MOS transistors were necessary.
As shown in the figure, a relationship in which the amount of impurity introduction and the threshold voltage are proportional is obtained, and by utilizing this property, the lithography step and the impurity introduction step can be reduced. That is,
The amount of impurity introduction is selected from the reference amount, the reference amount × 2, and the reference amount × 4. After that, eight kinds of impurity introduction amounts can be obtained by combining the impurity introduction amounts. Can be obtained. Thereby, the lithography step and the impurity introduction step can be reduced.

〔The invention's effect〕

As described above, by forming the capacitance circuit by the combination of the MOS transistor and the MOS capacitor, the variation of the capacitance can be changed from the variation of the impurity concentration profile to the thickness of the insulator of the MIS structure. Therefore, the average value of the current variation can be reduced from about 7% to about 3%.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIGS. 2 (a) to (d) show a method of manufacturing a semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing a second embodiment of the present invention, and FIG. 4 is a diagram showing a relationship between an impurity introduction amount and a threshold voltage. . 1,2,3,4,7,8 ... MOS capacitor, 11 ... P-type silicon substrate, 12 ... Field oxide film, 13 ... Gate oxide film, 14
... Impurity diffusion layer, 15 N-type diffusion layer, 16 gate electrode, 17 upper electrode, 18 source / drain region, 19
...... contact region, 20 ...... P ⁺ -type diffusion layer, 21 ...... silicon oxide film, 22 ...... aluminum _{wiring, Q 1, Q 2, Q} 3, Q 6, Q 7 ...
... MOS transistor, V ... Input voltage.

Claims (1)

(57) [Claims] A first MOS capacitor to which an input voltage is applied to both ends, a plurality of MOS transistors having threshold voltages set to different values, and a plurality of second MOS capacitors; A semiconductor integrated circuit, wherein a plurality of series members formed by connecting each of the MOS transistors and the second MOS capacitor in series are connected in parallel to the first MOS capacitor, respectively.