JPH0498865A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To lessen the variation of capacitance of a semiconductor device by a method wherein MOS transistors set different from each other in threshold voltage are connected in parallel to one end of a first MOS capacitor, and second MOS capacitors connected in series to the MOS transistors respectively are also connected to the other end of the first MOS capacitor. CONSTITUTION:A polycrystalline silicon film 8 is deposited on all the surface of a wafer, and a selective etching is performed to form a gate electrode 16 of a MOS transistor and an upper electrode 17 of a MOS capacitor. Then, N-type impurity ions are implanted using the gate electrode 16 and the upper electrode 17 as a mask to form a source and a drain region 18 and a contact region 19 which serves as the lead-out opening of the lower electrode of the MOS capacitor. On the other hand, boron is introduced to form a P<+>-type diffusion layer 20 which is made to serve as an electrode that keeps a substrate at a certain potential. A hole is bored in the region 19 concerned, and an aluminum wiring 22 is provided. By this setup, the average value of 7% of variation of a conventional semiconductor integrated circuit in capacitance can be reduced to around 3%.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor integrated circuits.

[Conventional technology]

A conventional semiconductor integrated circuit includes a variable capacitance diode having a PN junction formed by P-type and N-type impurity diffusion layers.

Generally, the reverse applied voltage applied to the PN junction causes P
Since the width of the depletion layer at the N junction changes, the capacitance changes. Utilizing this property, different capacitances can be obtained by applying voltage in the opposite direction.

[Problem to be solved by the invention]

In conventional semiconductor integrated circuits, an N-type epitaxial layer is formed on a P-type silicon substrate, and then a photolithography process and a process of introducing P-type impurities such as boron are performed.
It is fabricated through the steps of performing thermal diffusion to determine the concentration profile of the introduced P-type impurity, and finally performing appropriate metal wiring.

As mentioned above, in a variable capacitance diode using a PN junction, the expected change in capacitance with respect to reverse voltage is P
It is determined by the concentration profile of the P-type impurity diffusion layer forming the N-junction and the N-type epitaxial layer.

In the process of introducing impurities, the variation in the amount of impurities introduced within the wafer surface is as large as about 7%, making mass production of 5-inch and 6-inch wafers particularly impossible.

Further, regarding the thermal diffusion step after introducing the P-type impurity, the diffusion state of the P-type impurity changes due to the difference in the concentration profile of the thermal diffusion furnace, so that variations occur in the final concentration profile of the P-type impurity.

As described above, due to variations in the concentration profile of the epitaxial layer and the P-type impurity diffusion layer, there is a drawback that the capacitance of the formed capacitor varies greatly within the wafer surface and between lots.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention includes a first MOS capacitor and a plurality of MOSs connected in parallel to one end of the first MOS capacitor and having threshold voltages sequentially set to specific values.
A transistor, and a plurality of second MOS capacitors connected in series to each of the MOS transistors and connected to the other end of the first MOS capacitor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

As shown in FIG.
Series connection of S transistor Ql and MOS capacitor 2,
The series connection of the MOS transistor C2 and the MOS capacitor 3, and the series connection of the MOS transistor Q and the MOS capacitor 4 are connected in parallel.

Here, the voltage of MOS transistors Qt, C2, and Q3 is set as VTQI + "?Q2,"TQi, and
The capacitance of MOS capacitor 1, 2.3.4 is C1C2, C
s and C4, the circuit capacity changes as follows in the next four sections of the input voltage V.

C1 when 0 ≦V<VTQI C1+C when VTQI ≦V < VTQ2 (7)
2VTQ2≦V<V When TQ3, c1+C2+C
.

When V≧VTQS, CH+C2+C3+C4 Therefore, on the circuit, the capacitance of the entire circuit changes stepwise into four types in the four sections of the input voltage (■).

FIG. 2 is a cross-sectional view of a semiconductor chip shown in order of steps for explaining a method of manufacturing a semiconductor integrated circuit according to a first embodiment of the present invention.

First, as shown in FIG. 2(a), LOGO3(loc
A film with a thickness of 60 nm to 11
A field oxide film 12 having a thickness of about 00 nm is formed to define an element formation region. Next, a gate oxide film 13 is formed by thermally oxidizing the surface of the element formation region. Gate oxidation 11
The thickness of 13 is 30 nm to 50 nm. After that, M.O.
An impurity diffusion layer 14 for determining the threshold voltage of the S transistor is formed in the MOS transistor formation region using lithography technology and ion implantation technology. Furthermore, MOS
An N-type impurity such as phosphorus is introduced into the region where the capacitor is to be formed using lithography technology and ion implantation technology.

Regarding the amount of introduction, the dose is about I x 10''cs-2, and the acceleration energy is about 100 keV.

Next, as shown in FIG. 2(b), a polycrystalline silicon film is deposited on the entire surface of the wafer to a thickness of about 0.4 μm by low-pressure CVD, and then selectively etched to form the gate electrode 16 of the MOS transistor. and the upper voltage of the MOS capacitor 4
117 is formed.

Next, as shown in FIG. 2(c), using the gate electrode 16 and the upper electrode 17 as masks, N-type impurity ions are implanted into the source/drain regions 18 of the MOS transistor and the extraction opening of the lower electrode of the MOS capacitor. A contact region 19 is formed. Regarding the introduction of N-type impurities, arsenic ions are implanted at an acceleration energy of 70 keV and a dose of about 1X10"C11-". On the other hand, boron is introduced as an electrode to support the potential of the substrate and P+
A mold diffusion layer 20 is formed. Regarding impurity introduction, the acceleration energy is 50 keV and the dose is about 1×IQ "cs-".

Next, as shown in FIG. 2(d), a silicon oxide film 21 is deposited on the entire surface by atmospheric pressure CVD, holes are made in predetermined impurity diffusion layer regions by a lithography process, and aluminum interconnections 22 are formed by sputtering. and formed using lithography technology.

By forming a combination of a MOS transistor and a MOS capacitor in which only the impurity concentration of the impurity diffusion layer 14 is changed in the same process as the manufacturing method of the MOS transistor and MOS capacitor explained with reference to FIGS. 2(a) to (d), respectively. , MOS with different threshold voltages)-Radistor and MO
A series connection circuit of S capacitors can be constructed.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In this case, seven MOS transistors Q+Q2. ...
, Q7, and eight MOS capacitors 12, . . . , 8. In the first embodiment, the same number of lithography steps and impurity introduction steps as the number of MOS transistors were required to determine the threshold voltage, but if the concentration of the P-type substrate is appropriately selected, the process shown in FIG. Since a relationship is obtained in which the amount of impurity introduced is proportional to the threshold voltage, it is possible to use this property to reduce the lithography process and the impurity introduction process. That is, the amount of impurity introduced is the standard amount, the standard amount x 2. By selecting three of the reference amount x 4, eight different amounts of impurities can be obtained by combining the amounts of introduced impurities, and therefore eight different threshold voltages can be obtained. This makes it possible to reduce the lithography process and the impurity introduction process.

〔Effect of the invention〕

As explained above, by configuring a capacitive circuit using a combination of MOS transistors and MOS capacitors,
Since the variation in capacitance can be changed from the variation in the impurity concentration profile to the thickness of the insulator in the MIS structure, the current average variation of 7% can be reduced to about 3%.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, and FIG. 2 (
a) to (d) are cross-sectional views of a semiconductor chip shown in the order of steps to explain the method for manufacturing a semiconductor integrated circuit according to the first embodiment of the present invention, and FIG. The circuit diagram shown in FIG. 4 is a diagram showing the relationship between the amount of impurity introduced and the threshold voltage. 1.2, 3.4.7.8-MOS Konidenser, 11.
...P-type silicon substrate, 12...field oxide film,
13... Gate oxide film, 14... Impurity diffusion layer, 1
5... N type diffusion layer, 16... Gate electrode, 17...
- Upper electrode, 18... source/drain region, 19.
...Contact region, 20...P+ type diffusion layer, 21.
...Silicon oxide film, 22...Aluminum wiring, Q
IQ2, Qs, Q6, QF...MOS transistor, ■...Input voltage. ,y11 figure

Claims (1)

[Claims] a first MOS capacitor; a plurality of MOS transistors connected in parallel to one end of the first MOS capacitor and having threshold voltages successively set to different values;
connected in series to each of the first M transistors;
A plurality of second MOSs connected to the other end of the OS capacitor
A semiconductor integrated circuit characterized by being equipped with a capacitor.