JP2612858B2 - Multi-layer circuit board with inspection structure for interlayer misalignment - Google Patents
Multi-layer circuit board with inspection structure for interlayer misalignmentInfo
- Publication number
- JP2612858B2 JP2612858B2 JP62152230A JP15223087A JP2612858B2 JP 2612858 B2 JP2612858 B2 JP 2612858B2 JP 62152230 A JP62152230 A JP 62152230A JP 15223087 A JP15223087 A JP 15223087A JP 2612858 B2 JP2612858 B2 JP 2612858B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- inspection
- notch
- interlayer
- substrates
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
Description
【発明の詳細な説明】 技術分野 本発明は、層間ずれの検査構造を有する多層回路基板
に関する。Description: TECHNICAL FIELD The present invention relates to a multi-layer circuit board having a structure for detecting misalignment.
背景技術 典型的な先行技術では、多層回路基板の層間ずれを検
査するために軟Ｘ線透視装置が用いられ、各層ごとに形
成された回路パターンが透視されて、層間ずれの検査が
行なわれていた。したがつて、このような先行技術は非
破壊検査であるため、製品の全数検査を行なうことが可
能であるが、Ｘ線の漏洩防止のためにＸ線の確実な遮蔽
を行なう必要があり、このため検査を行なうべき製品の
装脱に時間がかかり、コスト高となつて全数検査には不
利である。2. Description of the Related Art In a typical prior art, a soft X-ray fluoroscope is used to inspect the interlayer shift of a multilayer circuit board, and a circuit pattern formed for each layer is seen through to inspect the interlayer shift. Was. Therefore, since such prior art is a nondestructive inspection, it is possible to perform a 100% inspection of the product, but it is necessary to reliably shield X-rays in order to prevent leakage of X-rays. For this reason, it takes time to load and unload a product to be inspected, and the cost is high, which is disadvantageous for 100% inspection.
また他の先行技術では製作ロツトごとにサンプル品を
抜取り、破壊検査によつて層間ずれの検査が行なわれて
いた。したがつて、このような先行技術は抜取検査であ
り、全数検査を行なうことができない。In other prior arts, a sample product is extracted for each production lot, and an inspection for interlayer misalignment is performed by a destructive inspection. Therefore, such prior art is a sampling inspection and cannot perform a 100% inspection.
発明が解決すべき問題点 本発明の目的は、安価に全数検査を行なうことができ
るようにした層間ずれの検査構造を有する多層回路基板
を提供することである。Problems to be Solved by the Invention It is an object of the present invention to provide a multilayer circuit board having an interlayer misalignment inspection structure capable of performing a 100% inspection at a low cost.
問題点を解決するための手段 本発明は、電子部品が実装される回路基板領域と、該
回路基板領域の周縁部に形成される非回路基板領域とを
有し、 該非回路基板領域には、対向する２つの断面を有する
切欠きが少なくとも１つ形成され、該切欠きの２つの断
面に臨む層間ずれ検査用パターンが各層ごとに形成され
ていることを特徴とする層間ずれの検査構造を有する多
層回路基板である。Means for Solving the Problems The present invention has a circuit board area on which electronic components are mounted, and a non-circuit board area formed on the periphery of the circuit board area. At least one notch having two opposing cross sections is formed, and a delamination inspection pattern facing the two cross sections of the notch is formed for each layer. It is a multilayer circuit board.
また本発明は、切欠きは、相互に間隔をあけて２つ形
成されることを特徴とする。Further, the present invention is characterized in that two notches are formed at an interval from each other.
作 用 本発明に従えば、多層回路基板を構成する各層ごとの
基板には、電子部品が実装される回路基板領域と、この
回路基板領域の周縁部に形成される非回路基板領域とが
形成される。前記非回路基板領域には、予め定めた位置
に予め定めた大きさの検査用パターンが少なくとも１つ
形成されており、この検査用パターンの一部を含んで、
対向する２つの断面を有する切欠きを形成し、該切欠き
の２つの断面に臨む層間ずれ検査用パターンが各層ごと
に形成された基板を積層して多層回路基板を構成する。
したがつてこのように各基板が積層された状態で、各基
板ごとに形成された切欠き内に露出した検査用パターン
を比較することによつて、層間ずれを検査することがで
きる。According to the present invention, a circuit board area on which electronic components are mounted and a non-circuit board area formed on the periphery of the circuit board area are formed on the board for each layer constituting the multilayer circuit board. Is done. In the non-circuit board area, at least one inspection pattern of a predetermined size is formed at a predetermined position, and includes a part of the inspection pattern,
A notch having two cross sections opposed to each other is formed, and a substrate in which patterns for interlayer misalignment inspection facing the two cross sections of the notch are formed for each layer is laminated to form a multilayer circuit board.
Accordingly, in a state where the respective substrates are stacked in this way, the interlayer displacement can be inspected by comparing the inspection patterns exposed in the cutouts formed for the respective substrates.
実施例 第１図は、本発明の一実施例の多層回路基板１の斜視
図である。この多層回路基板１は、複数の基板２〜５が
積層されて構成される。基板２〜５は第２図に示される
ように、電子部品が実装される回路基板領域６と、この
回路基板領域６の周縁部に形成される非回路基板領域７
とから成る。各基板２〜５の非回路基板領域７の予め定
めた位置に、少なくとも１つ（この実施例では２つ）の
予め定めた大きさの検査用パターン12〜15;22〜25が、
基板２〜５の対角線上に形成される。このような検査用
パターン12〜15;22〜25が形成された基板２〜５を積層
した状態で、検査用パターン12〜15;22〜25の一部を含
んで基板２〜５の端部には、切欠き16,26が形成され
る。切欠き16,26は、対向する切断面が90度を成すよう
に形成される。Embodiment FIG. 1 is a perspective view of a multilayer circuit board 1 according to one embodiment of the present invention. The multilayer circuit board 1 is configured by stacking a plurality of boards 2 to 5. As shown in FIG. 2, the substrates 2 to 5 include a circuit board area 6 on which electronic components are mounted, and a non-circuit board area 7 formed on the periphery of the circuit board area 6.
Consisting of At predetermined positions of the non-circuit substrate area 7 of each of the substrates 2 to 5, at least one (two in this embodiment) inspection patterns 12 to 15;
It is formed on a diagonal line of the substrates 2 to 5. In a state where the substrates 2 to 5 on which the inspection patterns 12 to 15 and 22 to 25 are formed are stacked, the end portions of the substrates 2 to 5 including a part of the inspection patterns 12 to 15; Are formed with notches 16,26. The notches 16, 26 are formed so that the cut surfaces facing each other form 90 degrees.
このようにして形成された切欠き16,26を顕微鏡等の
拡大鏡で検査し、各検査用パターン12〜15;22〜25を比
較することによつて、第３図および第４図に示されるよ
うに、基板２〜５相互間のずれを確認することができ
る。The cutouts 16, 26 formed in this way are inspected with a magnifying glass such as a microscope, and the respective inspection patterns 12 to 15; 22 to 25 are compared, as shown in FIGS. 3 and 4. As can be seen, the displacement between the substrates 2 to 5 can be confirmed.
第３図は基板３にずれが生じたときの多層回路基板１
の斜視図であり、第４図はその平面図である。第３図お
よび第４図では、基板３が矢符27方向にねじれている状
態を示す。このようにねじれが生じている基板３に形成
された検査用パターン13,23は、一方の切断面16a,26aに
おいては、他の検査用パターン12,14,15;22,24,25より
長く露出し、他方の切断面16b,26bにおいては、他の検
査用パターン12,14,15;22,24,25より短く露出する。本
件多層回路基板１では、検査用パターン12〜15と検査用
パターン22〜25とは、最大の間隔を得るために対角線上
に形成されており、したがつてわずかなずれでも検出す
ることができる。FIG. 3 shows the multilayer circuit board 1 when the board 3 is displaced.
FIG. 4 is a plan view of FIG. 3 and 4 show a state in which the substrate 3 is twisted in the direction of the arrow 27. The inspection patterns 13 and 23 formed on the substrate 3 having the twist as described above are longer on one cut surface 16a and 26a than on the other inspection patterns 12, 14, 15; 22, 24, and 25. It is exposed, and is exposed shorter than the other inspection patterns 12, 14, 15; 22, 24, 25 on the other cut surfaces 16b, 26b. In the present multilayer circuit board 1, the test patterns 12 to 15 and the test patterns 22 to 25 are formed diagonally in order to obtain the maximum interval, so that even a slight displacement can be detected. .
このように各基板２〜５ごとにそれぞれ予め定めた位
置に、予め定めた大きさの検査用パターン12〜15;22〜2
5を形成しておき、基板２〜５を積層した状態で前記検
査用パターン12〜15;22〜25の一部を含むように切欠き1
6,26を形成し、この切欠き16,26の切断面16a,26a;16b,2
6bを検査することによつて、各基板２〜５相互間の直交
するＸ−Ｙ方向のずれを検出することができる。In this way, the inspection patterns 12 to 15; 22 to 2 having a predetermined size are set at predetermined positions for each of the substrates 2 to 5 respectively.
The notch 1 is formed so as to include a part of the inspection patterns 12 to 15; 22 to 25 in a state where the substrates 2 to 5 are laminated.
6, 26, the cut surfaces 16a, 26a of these notches 16, 26; 16b, 2
By inspecting 6b, it is possible to detect a shift in the orthogonal X-Y direction between each of the substrates 2-5.
検査用パターン12〜15;22〜25は、各基板２〜５ごと
に１個だけ設けられてもよく、また上述の実施例のよう
に各基板２〜５ごとに複数個設けられて、各層を成す各
基板のねじれが容易に検出されるようにしてもよい。Only one inspection pattern 12 to 15; 22 to 25 may be provided for each of the substrates 2 to 5, or a plurality of inspection patterns are provided for each of the substrates 2 to 5 as in the above-described embodiment. May be easily detected.
さらにまた切欠き16,26の切断面16a,26a;16b,26bは90
度以外の角度で対向するように、形成されてもよい。Furthermore, the cut surfaces 16a and 26a of the notches 16 and 26;
It may be formed so as to face at an angle other than degrees.
このような検査用パターン12〜15;22〜25は、基板２
〜５に回路パターンを形成する工程において同時に形成
することができ、したがつて本件多層回路基板１では、
各基板２〜５相互間の層間ずれの全数検査を安価に行な
うことができるようになる。Such inspection patterns 12 to 15;
5 can be formed simultaneously in the step of forming a circuit pattern. Therefore, in the multilayer circuit board 1 of the present invention,
Inspection of the total number of interlayer shifts between the substrates 2 to 5 can be performed at low cost.
効 果 以上のように本発明によれば、多層回路基板を構成す
る各層ごとの基板の非回路基板領域の予め定めた位置に
予め定めた大きさの検査用パターンが少なくとも１つ形
成されており、この検査用パターンの一部を含んで切欠
きを形成したので、切欠き内に露出した検査用パターン
を比較することによつて層間ずれを検査することがで
き、多層回路基板を安価に全数検査することができる。Effects As described above, according to the present invention, at least one test pattern having a predetermined size is formed at a predetermined position in a non-circuit board region of a substrate for each layer constituting a multilayer circuit board. Since the notch is formed so as to include a part of the inspection pattern, interlayer displacement can be inspected by comparing the inspection pattern exposed in the notch. Can be inspected.
さらに本発明によれば、非回路基板領域には、対向す
る２つの断面を有する切欠きを形成し、該切欠きの２つ
の断面に臨むように層間ずれ検査用パターンを形成する
ようにしたので、２次元平面に沿う層間ずれを１つの検
査用パターンで検査可能であり、そのため２次元平面内
のたとえば直交する２つの各方向毎に検査用パターンの
形成および層間ずれ検査に要する工程を約半分に削減す
ることができる。Furthermore, according to the present invention, a notch having two opposing cross sections is formed in the non-circuit board area, and a pattern for interlayer misalignment inspection is formed so as to face the two cross sections of the notch. It is possible to inspect the interlayer displacement along the two-dimensional plane with one inspection pattern. Therefore, the steps required for forming the inspection pattern and inspecting the interlayer misalignment in each of two orthogonal directions in the two-dimensional plane are reduced to about half. Can be reduced.
また本発明によれば、切欠きは、相互に間隔をあけて
２つ形成してもよく、また１つであつてもよく、本発明
の切欠きによつて、各層のねじれを、前述のように検出
することも、可能である。According to the present invention, two notches may be formed at an interval from each other, or may be one. The notch of the present invention reduces the twist of each layer. It is also possible to detect as follows.
【図面の簡単な説明】 第１図は本発明の一実施例の多層回路基板１の斜視図、
第２図は第１図に示された多層回路基板１の平面図、第
３図は基板３にずれが生じたときの多層回路基板１の斜
視図、第４図は第３図に示されるように基板３にずれが
生じたときの多層回路基板１の平面図である。 １……多層回路基板、２〜５……基板、６……回路基板
領域、７……非回路基板領域、12〜15;22〜25……検査
用パターン、16,26……切欠きBRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a multilayer circuit board 1 according to one embodiment of the present invention,
2 is a plan view of the multilayer circuit board 1 shown in FIG. 1, FIG. 3 is a perspective view of the multilayer circuit board 1 when the board 3 is displaced, and FIG. 4 is shown in FIG. FIG. 4 is a plan view of the multilayer circuit board 1 when the board 3 is displaced as described above. 1 multilayer circuit board, 2-5 board, 6 circuit board area, 7 non-circuit board area, 12-15; 22-25 inspection pattern, 16, 26 notch
Claims (2)
回路基板領域の周縁部に形成される非回路基板領域とを
有し、 該非回路基板領域には、対向する２つの断面を有する切
欠きが少なくとも１つ形成され、該切欠きの２つの断面
に臨む層間ずれ検査用パターンが各層ごとに形成されて
いることを特徴とする層間ずれの検査構造を有する多層
回路基板。1. A circuit board region on which an electronic component is mounted, and a non-circuit board region formed on a peripheral portion of the circuit board region. The non-circuit board region has two opposing cross sections. A multilayer circuit board having an interlayer misalignment inspection structure, wherein at least one notch is formed, and an interlayer misalignment inspection pattern facing two cross sections of the notch is formed for each layer.
れることを特徴とする特許請求の範囲第１項記載の多層
回路基板。2. The multilayer circuit board according to claim 1, wherein two notches are formed at an interval from each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62152230A JP2612858B2 (en) | 1987-06-17 | 1987-06-17 | Multi-layer circuit board with inspection structure for interlayer misalignment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62152230A JP2612858B2 (en) | 1987-06-17 | 1987-06-17 | Multi-layer circuit board with inspection structure for interlayer misalignment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63314892A JPS63314892A (en) | 1988-12-22 |
| JP2612858B2 true JP2612858B2 (en) | 1997-05-21 |
Family
ID=15535932
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62152230A Expired - Fee Related JP2612858B2 (en) | 1987-06-17 | 1987-06-17 | Multi-layer circuit board with inspection structure for interlayer misalignment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2612858B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009239165A (en) * | 2008-03-28 | 2009-10-15 | Ngk Spark Plug Co Ltd | Method of manufacturing multilayered wiring board, and multilayered wiring board |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59182977U (en) * | 1983-05-23 | 1984-12-06 | 沖電気工業株式会社 | multilayer printed wiring board |
| JPS61290800A (en) * | 1985-06-19 | 1986-12-20 | 株式会社日立製作所 | Interlamellar deviation detection for multilayer wiring board |
| JPS6237971U (en) * | 1985-08-26 | 1987-03-06 |
-
1987
- 1987-06-17 JP JP62152230A patent/JP2612858B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63314892A (en) | 1988-12-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |