JP2611644B2 - Write / read control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write / read control device, and more particularly to a write / read control device for writing data to a two-port RAM and reading the written data.

[0002]

2. Description of the Related Art A two-port RAM is a RAM having an input port and an output port and capable of independently writing write data and reading read data.

In a conventional method of using a two-port RAM, a write address generator for generating a write address signal based on a write frame pulse, and a read address generator for generating a read address signal based on a read frame pulse include: It is operated with the same clock signal to keep a certain phase difference (address difference) between a write address and a read address, and sequentially read data to be written to a two-port RAM.

[0004]

An error occurs in the write data when the write data to be written to the two-port RAM includes an error due to noise or an error occurred in the game device. Under some circumstances (when an alarm occurs), an error may have occurred in the write frame pulse. Based on the write frame pulse in which such an error has occurred,
When the write address section generates a write address signal, the write address signal becomes an unstable signal.

In the conventional method of using a two-port RAM, the write address section and the read address section are independent of each other. Therefore, when the write address signal becomes unstable, the phase difference between the write address and the read address becomes inconsistent. Thus, there is a problem that the read data read at this time is not reliable.

An object of the present invention is to improve the reliability of read data in a situation where an error occurs in write data.

[0007]

According to the present invention, a clock generator for outputting a clock signal; a write address generator for generating a write address signal based on a write frame pulse and the clock signal; A read address generating unit for generating a read address signal based on a read signal and a read frame pulse.
In a write / read control device for writing write data to M and outputting read data from the two-port RAM based on the read address signal, the write data is monitored to detect alarm information and generate a detection signal to generate the read address. An alarm information detecting device that outputs the write address signal to the read address generating unit, and the read address generating unit outputs the write address signal while the detection signal is being input. The read / write control device is characterized in that the read address signal is generated based on the following.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of the present invention.
As shown in FIG. 1, the two-port RAM control device according to the present embodiment detects the alarm information from the write data 4 and the write address generation unit 2 and the read address generation unit 3 connected to the two-port RAM 1 and generates the call address. Alarm information detection unit 5 that outputs a detection signal to the unit
And a clock generator 6 for supplying a clock signal to the write address generator 2 and the read address generator 3. Further, the two-port RAM control device has a signal line 7 for supplying a write address signal output from the write address generator 2 to the read address generator 3.

Next, the operation of the two-port RAM control device will be described. In the normal operation state, the write address generator 2 generates a write address signal based on a write frame pulse (WFP) indicating the head of the write address, triggered by the clock signal from the clock generator 6. Similarly, the read address generation unit 3 also uses the clock signal from the clock generation unit 6 as a trigger to set a read frame pulse (RF
A read address signal is generated based on P). Note that the read address generation unit 3 generates a read address signal such that the read address has a certain phase relationship with the write address.

The write address signal output from the write address generator 2 is input to the two-port RAM 1 and the write data 4 is written in accordance with the write address.
Is written to the two-port RAM 1. On the other hand, the read address signal output from the read address generation unit 3 is also input to the two-port RAM 1, and the read data 8 is read from the two-port RAM 1 according to the read address.

When the write data contains an error (alarm information) due to noise or the like, the alarm information detecting section 5 detects the alarm information and outputs a detection signal to the address generating section 3. This detection signal is continuously output while the alarm information is being detected.

When the alarm detection signal is input, the read address generator 3 generates a read signal having a predetermined phase difference from the write address based on the write address signal from the write address generator 2.

As described above, in the two-port RAM control device of this embodiment, when the phase difference between the write address and the read address is likely to be unstable, the read address signal is generated based on the write address signal. By doing so, the phase difference can be stabilized, and the reliability of read data can be improved.

When the alarm information is no longer detected from the write data, the alarm information detector 5 stops outputting the detection signal. Thereby, the read address generation unit 3
Generates a read address signal based on a read frame pulse indicating the beginning of a read address, triggered by a clock signal from the clock generator 6 as usual.

[0015]

According to the present invention, when alarm information is detected from write data, the read address signal is generated based on the write address signal, thereby improving the reliability of the read data.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 2-port RAM 2 Write address generator 3 Read address generator 4 Write data 5 Alarm information detector 6 Clock generator 7 Signal line 8 Read data

Claims (2)

(57) [Claims] 1. A clock generator for outputting a clock signal, a write address generator for generating a write address signal based on a write frame pulse and the clock signal, and a read operation based on the clock signal and a read frame pulse. A read address generation unit for generating an address signal; writing / reading the write data to the 2-port RAM based on the write address signal; and outputting the read data from the 2-port RAM based on the read address signal. In the control device, an alarm information detection device that monitors the write data, detects alarm information, and outputs a detection signal to the read address generation unit, and a supply unit that supplies the write address signal to the read address generation unit Provided, said A read / write control device, wherein the read address generation unit generates the read address signal based on the write address signal while the detection signal is being input. 2. The read address generation unit generates a read address signal indicating a read address having a predetermined phase difference from a write address indicated by the write address signal while the detection signal is being input. 2. The write / read control device according to claim 1, wherein: