JP2608447B2 - Complementary MIS field-effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a complementary MIS field-effect semiconductor device having improved performance, and further has a shorter channel and a transconductance g _m
A drain region and a source region, which are formed in self-alignment with an n-type silicon gate electrode in an n-channel transistor and form an n-type low impurity concentration region of an LDD structure, and the n-type silicon A metal or silicide thereof formed on both sides of the gate electrode and electrically connected and extending electrically on both sides of the p-type silicon gate electrode in the p-channel transistor; And self-aligned with the sidewall film on both sides of the n-type silicon gate electrode and formed continuously with the n-type low impurity concentration region and having a sufficiently high impurity concentration in comparison with the n-type silicon gate electrode. The n-type drain region and the n-type source region are formed in self-alignment with sidewall films on both sides of the p-type silicon gate electrode, and have the high impurity concentration. It is configured to include a p-type drain region and a p-type source region having a sufficiently high impurity concentration enough to function similarly to the n-type drain region and the n-type source region.

[Industrial applications]

The present invention provides a complementary MIS (complementary MIS) having improved performance.
The present invention relates to a field effect semiconductor device.

[Conventional technology]

FIG. 3 is a cutaway side view of a main part for describing a conventional example of a CMIS field-effect semiconductor device.

In the figure, 1 is a p ⁻ type silicon semiconductor substrate, 2 is n ⁻
Type well, 3 is a p ^- type well, 4 is an n-type channel cut region, 5 is a p-type channel cut region, 6 is a field insulating film made of silicon dioxide, 7 is a gate insulating film made of silicon dioxide, and 8P is a gate electrode made of p in polycrystalline silicon channel transistors, 8N gate electrode consisting in polycrystalline silicon n-channel transistors, 10 _PD is in the p-channel transistor p ^-
-Type drain region, 10 _PS is in the p-channel transistor p ^- type source region, 10 _ND is in the n-channel transistor n ^- -type drain region, 10 _NS is in the n-channel transistor n ^- -type source Region, 12 is an insulating film made of silicon dioxide, 13 _NC is an n ⁺ -type contact region for the n ⁻ -type well 2, and 13 _PD is p ^{+ in the} p-channel transistor.
Type drain region, 13 _PS is a p ⁺ type source region in a p-channel transistor, 13 _ND is an n ⁺ type drain region in an n-channel transistor, 13 _NS is an n ⁺ type source in an n-channel transistor Region, 13 _PC is a p ⁺ -type contact region for the p ⁻ -type well 3, 14 is an interlayer insulating film made of, for example, phosphosilicate glass (PSG),
15 _NC is a contact electrode for n ^- type well 2 and 15 _PD is p
The drain electrode in the channel transistor, 15 _PS is the source electrode in the p-channel transistor, 15 _PG is the gate electrode in the p-channel transistor, and 15 _ND is n
The drain electrode of the channel transistor, 15 _NS is the source electrode of the p-channel transistor, and 15 _PC is
A contact electrode for the p ^- type well 3, 16P is a side wall film made of silicon dioxide formed on both sides of the gate electrode 8P via an insulating film 12, and 16N is an insulating film 1 on both sides of the gate electrode 8N.
2 shows a side wall film made of silicon dioxide formed through the gate electrode 2.

Usually, in the CMIS field-effect semiconductor device, it is sufficient to form one well of the opposite conductivity type to the substrate, but in the illustrated CMIS field-effect semiconductor device, both the n ^- type well 2 and the p ^- type well 3 are used. have.

The reason for this is that the channel of the transistor is shortened in order to improve the characteristics of the CMIS field-effect semiconductor device and achieve high integration. That is, in the illustrated example, for example, n channels
If the well on the transistor side is replaced with a p ^- type silicon semiconductor substrate 1 having a low impurity concentration, punch-through easily occurs between the source and the drain. Therefore, a well 3 having an appropriate impurity concentration is separately provided. Trying to avoid the punch through.

In addition, this CMIS field-effect semiconductor device employs a so-called lightly doped drain (LDD) structure in addition to the above-described countermeasures for avoiding the problem caused by shortening the channel.

The reason is that, especially in an n-channel transistor, apparently the threshold voltage rises due to the hot electron effect, a large current cannot be taken out, and the transconductance g _m In order to avoid problems such as reduction in size, the concentration of the electric field is reduced by expanding the depletion layer from the n ^- type drain region 10 _ND having a low impurity concentration, and the mutual conductance g is thereby reduced. _{The company} says that the decrease in _m can be improved.

[Problems to be solved by the invention]

In the CMIS field-effect semiconductor device described with reference to FIG. 3, both the polysilicon gate electrodes 8P and 8N
n ⁺ type doping.

The reason for this is that it is advantageous to apply a voltage to the polysilicon gate electrodes 8P and 8N.

FIG. 4 is a plan view of a main part of a conventional CMIS field-effect semiconductor device.

In FIG, S _P is the p ⁺ -type source region of the p-channel transistors, S _PL is p the p-channel transistor ^- type source region, D _P is p ⁺ -type drain region of the p-channel transistors, D _PL is p of the p-channel transistor ^- -type drain region, n ⁺ -type source region of the S _n are n-channel transistors, S _NL is the n-channel transistor n ^- -type source region, n ⁺ -type D _n are n-channel transistor A drain region, _DNL indicates an n ^- type drain region of an n-channel transistor, _GPY indicates an n ⁺ type polycrystalline silicon gate electrode, and L indicates a wiring.

As can be seen from the figure, the polysilicon gate electrode
G _PY is also used in the p-channel transistor section.
Since the portion of the n-channel transistor is also of the n ⁺ type, it can be integrally formed, and therefore, it is possible to adopt a configuration in which a voltage is applied by taking contact with the wiring L at one place. it can.

However, the conductivity type of the polycrystalline silicon gate electrode is preferably n ⁺ type for an n-channel transistor and p ⁺ type for a p-channel transistor.

That is, the work function differs depending on whether silicon is of the n ⁺ type or the p ⁺ type, and the threshold voltage of the transistor is determined by the work function and the substrate potential. , P ⁺ -type silicon gate is on the positive side, and n ⁺ -type is on the negative side, and the difference between them is about 1.1 [V].

When the voltage applied to the gate electrode is negative and the conductivity type of the polycrystalline silicon gate electrode in the p-channel transistor is p ⁺ type, the threshold voltage is compared with the case where the conductivity type is n ⁺ type. Then, it becomes the positive side and enters the state of depletion. This is equivalent to a low impurity concentration of the substrate.

Therefore, it is necessary to further increase the impurity concentration in the n ⁻ -type well 2 for enhancement, which is a favorable condition for preventing punch-through, and can further shorten the channel. .

However, for example, in the case of the CMIS field-effect semiconductor device shown in FIG. 4, the conductivity type of the polycrystalline silicon gate electrode in the p-channel transistor and that of the n-channel transistor are different from each other. ,
For example, the polycrystalline silicon gate electrode in the n-channel transistor also needs to make contact with another wiring and apply a different voltage to each of the p-channel transistor and the n-channel transistor. Such a configuration goes against the high integration that has been consistently required for semiconductor devices up to the present.

Now, apart from the above-mentioned problem relating to the conductivity type of the polycrystalline silicon gate electrode, as described above, the CMIS field-effect semiconductor device shown in FIG. Although contemplate that increasing the transconductance g _m Te, in fact, not been obtained so much effect.

The reason for this is that, in the low impurity concentration drain region 10 _ND or the like which is a feature of the LDD structure, the resistance value is naturally high, so that the current does not easily flow. In addition, the p-channel transistor, which is not related to the hot electron effect, also has a p ^- type drain region 10.
Although such _PD is formed, which, originally and should not require, by taking such a configuration, the rather transconductance g _m is reduced.

As described above, the In conventional CMIS field effect semiconductor device, in spite of various there's a twist not improved transconductance g _m and switching speed.

The present invention is further short channel, and attempts to provide a CMIS field effect semiconductor device having an improved transconductance g _m.

[Means for solving the problem]

In the CMIS field-effect semiconductor device according to the present invention, n
A drain region and a source region (for example, an n-type low impurity concentration region of an LDD structure formed in self-alignment with an n-type silicon gate electrode (for example, an n ⁺ -type polycrystalline silicon gate electrode 8N) in a channel transistor. n ⁻ type drain region 10 _ND and n ⁻ type source region 10 _NS ), which are formed on both sides of the n type silicon gate electrode, are electrically connected to each other, and are p type silicon regions in the p channel transistor. Sidewall film (eg, sidewall film W _S ) made of metal or silicide thereof extending to both sides of gate electrode (eg, p ⁺ -type polycrystalline silicon gate electrode 8P) and electrically connected thereto
An n-type drain which is self-aligned with the sidewall film on both sides of the n-type silicon gate electrode and is formed continuously with the n-type low impurity concentration region and has a sufficiently high impurity concentration as compared with the n-type drain electrode Region and n-type source region (eg,
The n ⁺ -type drain region 13 _ND and the n ⁺ -type source region 13 _NS ) are formed in self-alignment with sidewall films (for example, sidewall films W _S ) on both sides of the p-type silicon gate electrode. An n-type drain region having an impurity concentration and p having a sufficiently high impurity concentration to function similarly to the n-type source region.
And a p-type source region (for example, p ⁺ -type drain region 13 _PD and p ⁺ -type source region 13 _PS ).

[Action]

By adopting the above-described means, it becomes possible to appropriately increase the impurity concentration of the well corresponding to the substrate in the transistor, and hence punch-through is more unlikely to occur, thereby further shortening the channel. It is possible,
In particular, the channel of the p-channel transistor can be made shorter as compared with the prior art. Further, when the n-channel transistor is turned on, the resistance value of the low impurity concentration region forming the LDD structure for improving the hot carrier effect is significantly reduced, and therefore, a large current can flow. Transconductance g _m
The p-channel transistor is not provided with a low-impurity-concentration region having an LDD structure, which was originally useless, so that the on-state resistance is reduced by that much, and a large current because can flow, the transconductance g _m Again the higher. Furthermore, polysilicon gate electrode, the n ⁺ -type a n-channel transistor, the p ⁺ -type in the p-channel transistor,
Despite the preferred conductivity types, the presence of the conductive sidewall film allows only one contact with the wiring, so that the integration is not impaired.

〔Example〕

FIG. 1 is a cutaway side view of an essential part of one embodiment of the present invention, and the same symbols as those used in FIG. 3 indicate the same parts or have the same meanings.

The present embodiment differs from the conventional example shown in FIG. 3 in that (1) a p-channel transistor The polycrystalline silicon gate electrode 8P is doped with p ⁺ type, and the polycrystalline silicon・ Gate electrode
The side wall film 11P for 8P is made of metal or its silicide, and is conductively connected, and the drain region and the source region are not provided with a low impurity concentration region. (2) N channel transistor Polycrystalline silicon The sidewall film 11N for the gate electrode 8N is made of metal or its silicide, and is conductively connected.

In such a CMIS field-effect semiconductor device, when a voltage is applied to the gate electrodes 8N and 15 _NG in the n-channel transistor as a component thereof, the n ^- type drain regions _10ND and n ^- type Source region 10 _NS has conductive sidewall film 11
N voltage is applied via the gate insulating film 7, as if so acts as a depletion-type MIS field effect transistor, the resistance value is significantly reduced, it is possible to flow a large current, the transconductance g _m is improved I do. Further, in the p-channel transistor, since the gate electrode 8P is doped with p ⁺ type, the channel can be further shortened, and the drain region and the source region with low impurity concentration are present. does not, here the transconductance g _m is also increased, overall switching speed becomes faster.

Now, the polycrystalline silicon of the n-channel transistor
Although the advantage of making the side wall film 11N conductive relative to the gate electrode 8N is as described above, it will be explained that it is also significant for a p-channel transistor.

FIG. 2 is a plan view of a main part of one embodiment of the present invention, and the same symbols as those used in FIG. 4 indicate the same parts or have the same meanings.

The point that the illustrated CMIS field-effect semiconductor device differs from that shown in FIG. 4 is that the polycrystalline silicon gate electrode in the p-channel transistor is of p ⁺ type, and of course, the polycrystalline silicon in the n-channel transistor. silicon gate electrode have been respectively doped n ⁺ -type, the whole is to have contact with the wiring L through the side wall film W _S made of a metal or a silicide. Thus, even if the polysilicon gate electrode G _PY is not different from the conductivity type in the portion and the n-channel transistor portion of the p-channel transistors, since the sidewall film W _S of conductivity is present, It is not necessary to take separate contacts for each, so there is no risk that the integration will be compromised.

To produce a CMIS field effect semiconductor device according to the present invention is very easy, for example, (1) depending on the applying ordinary techniques, p ^- n -type silicon semiconductor substrate ^- -type well 2, p ^- Type well 3, n-type channel cut region 4, p-type channel cut region 5,
A field insulating film 6 and a gate insulating film 7 are formed.

(2) Chemical vapor deposition:
An etching stopper film made of a polycrystalline silicon film and silicon dioxide is formed by applying a CVD) method and a thermal oxidation method.

(3) Using a mask, pattern the etching stopper film and the polycrystalline silicon film to obtain patterned etching stopper films 9P and 9N and polycrystalline silicon gate electrodes 8P and 8N.

(4) By applying the ion implantation method, the n ⁻ type source region 10 _NS and the n ⁻ type drain region 10 _ND in the n-channel transistor are formed.

(5) A conductive film made of a metal or a silicide thereof is formed by applying a sputtering method, and the conductive film is etched by applying an anisotropic dry etching method to form the side wall film 11P and Form 11N.

(6) By applying the ion implantation method, the n ⁺ -type drain region 13 _{ND and the} n ⁺ -type source region 13 _NS are formed on the n-channel transistor side, and the polysilicon gate electrode 8N is made conductive. Sexualize.

(7) By applying the ion implantation method, on the p-channel transistor side, the p ⁺ -type drain region 13 _{PD and the} p ⁺ -type source region 13 _PS are formed, and the polysilicon gate electrode 8P is made conductive. Sexualize.

(8) By applying a normal technique, the PSG film 14 is formed, and various electrodes and wiring such as the contact electrode 15 _NC for the n ⁻ -type well 2 are formed and completed.

After the polycrystalline silicon film is formed in the step (2), an n-type impurity is added to a portion where the gate electrode of the n-channel transistor is to be formed, and a p-type impurity is added to the portion where the gate electrode of the p-channel transistor is to be formed. By introducing each type impurity, an impurity-containing polycrystalline silicon gate electrode may be obtained.

〔The invention's effect〕

In the CMIS field-effect semiconductor device according to the present invention, n
And source regions, which are formed in self-alignment with the n-type silicon gate electrode and form n-type low impurity concentration regions of the LDD structure, are formed on both sides of the n-type silicon gate electrode and are electrically connected. A side wall film made of a metal or a silicide thereof extending to both sides of the p-type silicon gate electrode and electrically connected thereto, being self-aligned with the side wall film and connected to the n-type low impurity concentration region. The n-type drain region and the n-type source region having a sufficiently high impurity concentration as compared with the n-type drain region and the sidewall film on both sides of the p-type silicon gate electrode; A p-type drain region and a p-type source region having a sufficiently high impurity concentration enough to function similarly to the n-type drain region and the n-type source region having a high impurity concentration; There.

By adopting the above configuration, it becomes possible to appropriately increase the impurity concentration of the well corresponding to the substrate in the transistor, and therefore, punch-through is more unlikely to occur, thereby further shortening the channel. It is possible,
In particular, the channel of the p-channel transistor can be made shorter as compared with the prior art. Further, when the n-channel transistor is turned on, the resistance value of the low impurity concentration region forming the LDD structure for improving the hot carrier effect is significantly reduced, and therefore, a large current can flow. transconductance g _m is had improved, and, in the p-channel transistors, originally because no low impurity concentration region is provided which forms an LDD structure was useless present, the resistance value of the oN state by that amount is low Become
Since it is possible to supply a large current, the transconductance g _m Again the higher. Furthermore, polysilicon gate electrode, the n ⁺ -type a n-channel transistor, the p ⁺ -type in the p-channel transistors, even though become suitable conductive type respectively, the conductive side wall film In this case, only one contact with the wiring is required, so that the integration is not impaired.

[Brief description of the drawings]

1 is a cutaway side view of a main part of one embodiment of the present invention, FIG. 2 is a plan view of a main part of one embodiment of the present invention, FIG. 3 is a cutaway side view of a main part of a conventional example, and FIG. Are respectively a plan view of a main part of FIG. In the figure, 1 is a p ^- type silicon semiconductor substrate, 2 is an n ^- type well, 3 is a p ^- type well, 4 is an n-type channel cut region, 5 is a p-type channel cut region, and 6 is a dioxide. A field insulating film made of silicon, 7 is a gate insulating film made of silicon dioxide, 8P is a gate electrode made of polycrystalline silicon in a p-channel transistor, and 8N is a gate electrode made of polycrystalline silicon in an n-channel transistor. , 10 _PD is in the p-channel transistor p ^- type drain region 10 _PS is in the p-channel transistor p ^- type source region 10 _ND is in the n-channel transistor n ^- -type drain region, 10 _NS is in the n-channel transistor n ^- -type source region, 11P and 11N is metal or sidewall film made of the silicide, 13 _NC is n ^- n ⁺ -type contact region for type well 2 13 _PD is p-channel transistors in the p ⁺ -type drain region, 13 _PS is p-channel
The p ⁺ type source region in the transistor, 13 _ND is the n ⁺ type drain region in the n-channel transistor, and 13 _NS is n
N ⁺ type source region in channel transistor, 13 _pcs
Is a p ⁺ -type contact region for the p ⁻ -type well 3, 14 is an interlayer insulating film made of, for example, PSG, 15 _NC is a contact electrode for the n ⁻ -type well 2, 15 _PD is a drain electrode in a p-channel transistor, 15 _PS Is a source electrode in a p-channel transistor, 15 _PG is a gate electrode in a p-channel transistor, 15 _ND is a drain electrode in an n-channel transistor, 15 _NS is a source electrode in a p-channel transistor, 15 _PC is p ^- type well contact electrode with respect to 3, 16P sidewall film made of silicon dioxide that is formed via the insulating film 12 on both sides of the gate electrode 8P, 16N
Indicates side wall films made of silicon dioxide formed on both sides of the gate electrode 8N via the insulating film 12, respectively.

Claims (1)

(57) [Claims] 1. A drain region and a source region which are formed in self-alignment with an n-type silicon gate electrode of an n-channel transistor to form an n-type low impurity concentration region of an LDD structure, and the n-type silicon gate electrode And a side wall film made of a metal or a silicide thereof which is electrically connected and extends on both sides of the p-type silicon gate electrode in the p-channel transistor and is electrically connected. An n-type drain which is self-aligned with the side wall film on both sides of the n-type silicon gate electrode and is formed continuously with the n-type low impurity concentration region and has a sufficiently high impurity concentration as compared with the n-type drain. And an n-type source region, and an n-type drain region formed in self-alignment with sidewall films on both sides of the p-type silicon gate electrode and having the high impurity concentration. And complementary MIS field effect semiconductor device characterized by comprising an n-type drain region and the p-type source region having a high impurity concentration degree sufficient to function in the same manner as the n-type source region.