JP2606548B2 - Cu wiring and method for forming the same - Google Patents
Cu wiring and method for forming the sameInfo
- Publication number
- JP2606548B2 JP2606548B2 JP5099963A JP9996393A JP2606548B2 JP 2606548 B2 JP2606548 B2 JP 2606548B2 JP 5099963 A JP5099963 A JP 5099963A JP 9996393 A JP9996393 A JP 9996393A JP 2606548 B2 JP2606548 B2 JP 2606548B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- forming
- wiring
- gas
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体素子作成プロセス
の一つであるCu配線およびその形成方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Cu wiring which is one of semiconductor device fabrication processes and a method of forming the same.
【0002】[0002]
【従来の技術】従来LSIの配線材料にはAlあるいは
Al合金が用いられていたが、今後の微細化にはAlあ
るいはAl合金では抵抗値の高さによる信号伝達速度の
遅れ、マイグレーション耐性の低さによる信頼性の低下
が問題となる。Cuは低抵抗、高マイグレーション耐性
からAlに代わる配線材料として期待されている。Cu
配線を実用化するにあたっては加工、拡散、パッシベー
ション、密着性などが問題となる。2. Description of the Related Art Conventionally, Al or an Al alloy has been used as a wiring material of an LSI. However, in the future miniaturization, Al or an Al alloy causes a delay in signal transmission speed due to a high resistance value and a low migration resistance. This causes a problem that the reliability is lowered. Cu is expected as a wiring material to replace Al because of its low resistance and high migration resistance. Cu
In practical use of wiring, processing, diffusion, passivation, adhesion and the like become problems.
【0003】密着性の向上には、加熱により界面に下地
との合金層を作る、あるいはイオン注入により界面での
結合の強化等の方法が考えられているが、これらは基板
中へのCuの拡散、ダメージ層形成等の点で問題が残
る。そこで現在は、Cuの下地に合金層を用い拡散防止
と密着性向上を図る方法が主流となっている。In order to improve the adhesion, a method of forming an alloy layer with an underlayer at the interface by heating or strengthening the bonding at the interface by ion implantation has been considered. Problems remain in terms of diffusion, formation of a damaged layer, and the like. Therefore, at present, a method of preventing diffusion and improving adhesion by using an alloy layer as an underlayer of Cu is mainly used.
【0004】またCuの堆積方法は、下地をスパッタ法
あるいはCVD法で堆積した後にCuをスパッタ法ある
いはCVD法で堆積する。このとき下地とCuのミキシ
ングによる配線の高抵抗化を防ぐため、下地の堆積とC
uの堆積を別の装置で行うことが多い。[0004] In the method of depositing Cu, Cu is deposited by a sputtering method or a CVD method after depositing an underlayer by a sputtering method or a CVD method. At this time, in order to prevent the wiring from having a high resistance due to the mixing of the underlayer and Cu, the underlayer deposition and C
The deposition of u is often performed in a separate apparatus.
【0005】[0005]
【発明が解決しようとする課題】Cu配線の作成法は下
地絶縁膜上あるいは下地合金層を形成した後、下地層形
成とは異なる装置で下地膜上にスパッタ法によりCu配
線を形成している。その場合、Cu配線と下地層との密
着性が弱いこと、別の装置に移動する際に下地層表面に
不純物が吸着し密着性を更に低下させるために剥がれが
生じ、LSIの信頼性を低下させることが問題となって
いる。A method for forming a Cu wiring is to form a Cu wiring on a base insulating film or a base alloy layer by sputtering after forming the base alloy layer on the base film using an apparatus different from that for forming the base layer. . In this case, the adhesion between the Cu wiring and the underlying layer is weak, and impurities are adsorbed on the surface of the underlying layer when moving to another device, and peeling occurs to further reduce the adhesiveness, thereby reducing the reliability of the LSI. Is a problem.
【0006】本発明の目的は上記の問題を克服し密着性
の良いCu配線およびその形成方法を提供することにあ
る。An object of the present invention is to provide a Cu wiring which overcomes the above problems and has good adhesion and a method for forming the same.
【0007】[0007]
【課題を解決するための手段】本発明のCu配線は、半
導体基板上に形成された下地膜と、この下地膜上に形成
されたCuX N1-X 膜と、このCuX N1-X 膜上に形成
されたCu膜と、を有することを特徴とする。Cu wiring of the present invention, in order to solve the problems] includes a base film formed on a semiconductor substrate, a Cu X N 1-X film formed on the underlying film, the Cu X N 1- It characterized by having a a Cu film formed on the X film.
【0008】本発明のCu配線の形成方法は、半導体基
板上に形成された下地膜上に、ArガスとN2 ガスを同
時に導入し反応性スパッタ法によりCux N1-x 層を形
成する工程と、Cux N1-x 形成後、N2 ガスを導入し
スパッタ法によりCu層を形成する工程と、を含むこと
を特徴とする。In the method of forming a Cu wiring according to the present invention, an Ar gas and a N 2 gas are simultaneously introduced on a base film formed on a semiconductor substrate to form a Cu x N 1 -x layer by a reactive sputtering method. A step of forming a Cu layer by a sputtering method by introducing N 2 gas after forming Cu x N 1 -x .
【0009】[0009]
【作用】本発明においては、Cu層と下地層との間にC
ux N1-x 層が存在する構造が形成される。下地層の成
分元素とCuがNを介して結合することが可能となる。
その結果、界面での結合力が強くなり密着性が向上す
る。また真空を維持したままの連続堆積が可能であり、
密着性,抵抗率に影響を及ぼすO等の不純物の混入を防
ぐことが出来る。According to the present invention, a C layer is provided between the Cu layer and the underlayer.
A structure is formed in which the u x N 1-x layer is present. The elemental element of the underlayer and Cu can be bonded via N.
As a result, the bonding force at the interface is increased, and the adhesion is improved. In addition, continuous deposition while maintaining vacuum is possible,
It is possible to prevent impurities such as O from affecting the adhesion and the resistivity.
【0010】[0010]
【実施例】次に本発明の実施例について図面を参照して
説明する。Next, an embodiment of the present invention will be described with reference to the drawings.
【0011】(実施例1)図1は、本発明の一実施例を
説明するための工程順に示した半導体チップの断面図で
ある。(Embodiment 1) FIG. 1 is a sectional view of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
【0012】まず図1(a)に示すように、Arガスと
N2 ガスをそれぞれ0.1〜6mTorr同時に供給
し、Si基板10上に形成されたSiO2 膜20上に反
応性スパッタ法によりCux N1-x 膜を1〜50nm堆
積する。First, as shown in FIG. 1A, an Ar gas and an N 2 gas are simultaneously supplied at 0.1 to 6 mTorr respectively, and the SiO 2 film 20 formed on the Si substrate 10 is reactively sputtered on the SiO 2 film 20. A Cu x N 1 -x film is deposited to a thickness of 1 to 50 nm.
【0013】次に図1(b)に示すように、N2 ガスの
供給を停止し、Arガスのみを0.1〜6mTorr供
給し、Cux N1-x 膜30上にCu膜40をスパッタ法
により50〜400nm堆積する。Next, as shown in FIG. 1B, the supply of the N 2 gas is stopped, only the Ar gas is supplied at 0.1 to 6 mTorr, and the Cu film 40 is formed on the Cu x N 1 -x film 30. Deposit 50 to 400 nm by sputtering.
【0014】Cux N1-x 膜堆積時のArガス圧を1.
5mTorr、N2 ガス圧を1.5mTorrとし、C
u膜堆積時のArガス圧3mTorrとしたとき、Cu
x N1-x 膜30の有無による密着度の差をスクラッチテ
スタにより評価した結果を表1に示す。The Ar gas pressure during the deposition of the Cu x N 1 -x film is set at 1.
5 mTorr, N 2 gas pressure is 1.5 mTorr, and C
When the Ar gas pressure at the time of depositing the u film is 3 mTorr, Cu
The result of the difference in adhesion between the presence or absence of x N 1-x film 30 was evaluated by a scratch tester shown in Table 1.
【0015】[0015]
【表1】 [Table 1]
【0016】SiO2 膜上にCu膜を直接堆積した場合
に比べ、Cux N1-x 膜を挿入した場合に密着力の向上
がみられている。[0016] Compared to the case where a Cu film is directly deposited on the SiO 2 film, the adhesion is improved when the Cu x N 1-x film is inserted.
【0017】以上の結果は、SiO2 膜でなくSiNx
膜でも得られ全ての絶縁体に適用可能である。またSi
基板でなく、GaAs基板、InP基板等あらゆる半導
体基板で同様の結果が得られる。The above results indicate that SiN x was used instead of the SiO 2 film.
It can also be obtained as a film and is applicable to all insulators. Also Si
Similar results can be obtained with any semiconductor substrate such as a GaAs substrate and an InP substrate instead of the substrate.
【0018】(実施例2)図2は、本発明の他の実施例
を説明するための工程順に示した半導体チップの断面図
である。(Embodiment 2) FIG. 2 is a sectional view of a semiconductor chip shown in the order of steps for explaining another embodiment of the present invention.
【0019】まず図2(a)に示すSi基板10上のS
iO2 膜20上に1〜10nm堆積されたTi膜50上
に、図2(b)に示すように、ArガスとN2 ガスをそ
れぞれ0.1〜6mTorr同時に供給し、基板温度1
00〜400℃で反応性スパッタ法によりCux N1-x
膜30を1〜50nm堆積する。このときTi膜50は
窒化されTiN膜60が1〜10nm形成される。First, S on the Si substrate 10 shown in FIG.
As shown in FIG. 2B, an Ar gas and an N 2 gas are simultaneously supplied at 0.1 to 6 mTorr respectively on the Ti film 50 deposited on the iO 2 film 20 at 1 to 10 nm, and the substrate temperature is set to 1
Cu x N 1-x by reactive sputtering at 00 to 400 ° C.
A film 30 is deposited with a thickness of 1 to 50 nm. At this time, the Ti film 50 is nitrided to form a TiN film 60 having a thickness of 1 to 10 nm.
【0020】次に図2(c)に示すように、N2 ガスの
供給を停止し、Arガスのみを0.1〜6mTorr供
給し、Cux N1-x 膜30上にCu膜40をスパッタ法
により50〜400nm堆積する。Next, as shown in FIG. 2C, the supply of N 2 gas is stopped, only Ar gas is supplied at 0.1 to 6 mTorr, and a Cu film 40 is formed on the Cu x N 1 -x film 30. Deposit 50 to 400 nm by sputtering.
【0021】以上の結果は、SiO2 膜でなくSiNx
膜でも得られ全ての絶縁体に適用可能である。[0021] As a result of the above is, SiN x instead of the SiO 2 film
It can also be obtained as a film and is applicable to all insulators.
【0022】またTi膜でなく他の金属あるいは合金で
も同様の結果が得られる。さらにSi基板でなくGaA
s基板、InP基板等全ての半導体基板で同様の結果が
得られる。Similar results can be obtained with other metals or alloys instead of the Ti film. GaAs instead of Si substrate
Similar results can be obtained for all semiconductor substrates such as s substrate and InP substrate.
【0023】(実施例3)図3は本発明の他の実施例を
説明するための工程順に示した半導体チップの断面図で
ある。(Embodiment 3) FIG. 3 is a sectional view of a semiconductor chip shown in the order of steps for explaining another embodiment of the present invention.
【0024】まず図3(a)に示すSi基板10上に1
〜10nm堆積されたTi膜50上に、図3(b)に示
すように、ArガスとN2 ガスをそれぞれ0.1〜6m
Torr同時に供給し、基板温度100〜400℃で反
応性スパッタ法によりCuxN1-x 膜30を1〜50n
m堆積する。このときTi膜の表面は窒化されTiN膜
60が0.5〜10nm形成され、Ti膜の基板側表面
はシリサイド化しTiSi2 層70が0.5〜10nm
形成される。First, 1 is placed on the Si substrate 10 shown in FIG.
As shown in FIG. 3B, an Ar gas and a N 2 gas are respectively applied to the Ti film 50 having a thickness of 0.1 to 6 nm.
Torr at the same time, and the Cu x N 1 -x film 30 is formed by a reactive sputtering method at a substrate temperature of 100 to 400 ° C. for 1 to 50 n.
m. At this time, the surface of the Ti film is nitrided to form a TiN film 60 of 0.5 to 10 nm, and the surface of the Ti film on the substrate side is silicided to form a TiSi 2 layer 70 of 0.5 to 10 nm.
It is formed.
【0025】次に図3(c)に示すように、N2 ガスの
供給を停止し、Arガスのみを0.1〜6mTorr供
給し、Cux N1-x 膜30上にCu膜40をスパッタ法
により50〜400nm堆積する。Next, as shown in FIG. 3C, the supply of the N 2 gas is stopped, only the Ar gas is supplied at 0.1 to 6 mTorr, and the Cu film 40 is formed on the Cu x N 1 -x film 30. Deposit 50 to 400 nm by sputtering.
【0026】以上の結果は、Ti膜に限らず他の金属で
も同様の結果が得られる。The above results are not limited to the Ti film, and similar results can be obtained with other metals.
【0027】[0027]
【発明の効果】以上説明したように本発明によれば、下
地膜との良好な密着性を持つCu配線およびその形成方
法を提供することができる。As described above, according to the present invention, it is possible to provide a Cu wiring having good adhesion to a base film and a method for forming the same.
【図1】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図2】SiO2 膜上にTiを形成した基板を用いた場
合の例を示す断面図である。FIG. 2 is a cross-sectional view showing an example in which a substrate in which Ti is formed on a SiO 2 film is used.
【図3】Si膜上にTiを形成した基板を用いた場合の
例を示す断面図である。FIG. 3 is a cross-sectional view showing an example in which a substrate in which Ti is formed on a Si film is used.
10 Si基板 20 SiO2 30 Cux N1-x 40 Cu 50 Ti 60 TiN 70 TiSi2 10 Si substrate 20 SiO 2 30 Cu x N 1 -x 40 Cu 50 Ti 60 TiN 70 TiSi 2
Claims (4)
rガスとN2 ガスを同時に導入し反応性スパッタ法によ
りCux N1-x 層を形成する工程と、 Cux N1-x 形成後、N2 ガスを導入しスパッタ法によ
りCu層を形成する工程と、 を含むことを特徴とするCu配線の形成方法。2. The method according to claim 1, wherein an A film is formed on the underlayer formed on the semiconductor substrate.
a step of forming a Cu x N 1 -x layer by reactive sputtering by simultaneously introducing r gas and N 2 gas, and forming a Cu layer by sputtering by introducing N 2 gas after forming Cu x N 1 -x And c. Forming a Cu wiring.
あるいはTiであることを特徴とする請求項2記載のC
u配線の形成方法。3. The method according to claim 1, wherein the under film is made of SiO 2 or SiN x
3. The C according to claim 2, wherein the C is Ti.
Method for forming u wiring.
x N1-x 堆積時の基板温度を100〜400℃とするこ
とを特徴とする請求項3記載のCu配線の形成方法。4. When the underlying film is Ti, the Cu
method of forming a Cu wiring according to claim 3, characterized in that the substrate temperature during x N 1-x deposited as 100 to 400 ° C..
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5099963A JP2606548B2 (en) | 1993-04-27 | 1993-04-27 | Cu wiring and method for forming the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5099963A JP2606548B2 (en) | 1993-04-27 | 1993-04-27 | Cu wiring and method for forming the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06310512A JPH06310512A (en) | 1994-11-04 |
JP2606548B2 true JP2606548B2 (en) | 1997-05-07 |
Family
ID=14261337
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5099963A Expired - Fee Related JP2606548B2 (en) | 1993-04-27 | 1993-04-27 | Cu wiring and method for forming the same |
Country Status (1)
Country | Link |
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JP (1) | JP2606548B2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6219125B1 (en) | 1996-07-26 | 2001-04-17 | Canon Kabushiki Kaisha | Electrode plate, process for producing the plate, for an LCD having a laminated electrode with a metal nitride layer |
JP2000165002A (en) * | 1998-11-26 | 2000-06-16 | Furontekku:Kk | Electronic device board therefor, its manufacture and electronic device |
JP5214125B2 (en) * | 2006-09-11 | 2013-06-19 | 三星ディスプレイ株式會社 | Wiring structure, wiring forming method, thin film transistor substrate and manufacturing method thereof |
JPWO2008044757A1 (en) * | 2006-10-12 | 2010-02-18 | 株式会社アルバック | Conductive film forming method, thin film transistor, thin film transistor panel, and thin film transistor manufacturing method |
US8105937B2 (en) * | 2008-08-13 | 2012-01-31 | International Business Machines Corporation | Conformal adhesion promoter liner for metal interconnects |
JP5420964B2 (en) * | 2009-04-28 | 2014-02-19 | 株式会社神戸製鋼所 | Display device and Cu alloy film used therefor |
JP6262483B2 (en) * | 2013-10-01 | 2018-01-17 | 株式会社カネカ | Conductive film substrate and manufacturing method thereof |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6312138A (en) * | 1986-07-02 | 1988-01-19 | Fujitsu Ltd | Pattern method of copper |
JPH02301907A (en) * | 1989-05-17 | 1990-12-14 | Hitachi Ltd | Metal circuit and its manufacture |
JPH0355844A (en) * | 1989-07-25 | 1991-03-11 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1993
- 1993-04-27 JP JP5099963A patent/JP2606548B2/en not_active Expired - Fee Related
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Publication number | Publication date |
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JPH06310512A (en) | 1994-11-04 |
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